diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-06-16 15:25:57 -0700 |
| commit | 625854785bee062d641934c779cb019348d11760 (patch) | |
| tree | dc4f543905c70871dd770c20be594d5f3f09d987 /tests | |
| parent | f24ae2ec2a43a5197934668b6f9638ed118994d8 (diff) | |
| download | gem5-625854785bee062d641934c779cb019348d11760.tar.xz | |
stats: update stats for SC protocol change
Some subset of UpgradeReq messages shifted to the
new SCUpgradeReq type. Other than that there
are no significant differences.
Diffstat (limited to 'tests')
20 files changed, 239 insertions, 150 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 035a139c8..636d3e4ce 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -660,7 +660,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -680,7 +680,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -806,7 +806,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index a7674462a..51c672072 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:50:36 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:50:38 -M5 executing on zizzer +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:40:27 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 125751000 Exiting @ tick 1907689250500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index a30544a1e..011675055 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 140959 # Simulator instruction rate (inst/s) -host_mem_usage 294084 # Number of bytes of host memory used -host_seconds 398.50 # Real time elapsed on the host -host_tick_rate 4787234846 # Simulator tick rate (ticks/s) +host_inst_rate 198866 # Simulator instruction rate (inst/s) +host_mem_usage 278256 # Number of bytes of host memory used +host_seconds 282.46 # Real time elapsed on the host +host_tick_rate 6753860070 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56171530 # Number of instructions simulated sim_seconds 1.907689 # Number of seconds simulated @@ -1250,26 +1250,46 @@ system.l2c.ReadReq_mshr_miss_rate::2 inf # ms system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 311951 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 839822000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 86460 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 54412 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 140872 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 83177.133796 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 132167.444461 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 17600 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 13825 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 31425 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 92935.170455 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 118311.681736 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40007.112172 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1635659000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 17600 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 13825 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 31425 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1257223500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.785511 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 2.273056 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses 31425 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 68860 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 40587 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 109447 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 80683.066918 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 136887.081775 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40094.049918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7191494988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40119.011942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 5555835988 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 86460 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 54412 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 140872 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5648129000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.629331 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.588988 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 68860 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 40587 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 109447 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4390905500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.589413 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.696602 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 140872 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 109447 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1423289998 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 451661 # number of Writeback accesses(hits+misses) diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 8128ce648..3fe2f1fcc 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -355,7 +355,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -375,7 +375,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -501,7 +501,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6a353dabf..dea7a38d9 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -7,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:50:36 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:51:37 -M5 executing on zizzer +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:39:35 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1867360295500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 867b96dc0..330dece92 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146942 # Simulator instruction rate (inst/s) -host_mem_usage 291780 # Number of bytes of host memory used -host_seconds 361.25 # Real time elapsed on the host -host_tick_rate 5169110276 # Simulator tick rate (ticks/s) +host_inst_rate 205161 # Simulator instruction rate (inst/s) +host_mem_usage 276364 # Number of bytes of host memory used +host_seconds 258.74 # Real time elapsed on the host +host_tick_rate 7217130781 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53083414 # Number of instructions simulated sim_seconds 1.867360 # Number of seconds simulated @@ -705,21 +705,36 @@ system.l2c.ReadReq_mshr_miss_rate::1 inf # ms system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 130096 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 130096 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52274.462658 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 29987 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29987 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52320.338813 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.217194 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1568930000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 29987 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29987 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1199516500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses 29987 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 100109 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 100109 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52260.720754 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.358873 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6800698494 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40126.157488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 5231768494 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 130096 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 130096 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5216506000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 100109 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 100109 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4016989500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130096 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 100109 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index e7e943434..decabad7f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -264,7 +264,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -284,7 +284,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -410,7 +410,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr index 5a1d0bef0..83c71fc5c 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr @@ -2,6 +2,4 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: 97861500: Trying to launch CPU number 1! -For more information see: http://www.m5sim.org/warn/8f7d2563 hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 643403e5a..74b825924 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:12 -M5 executing on SC2B0619 +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:44:34 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... +info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 591b54757..7f610a74e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2090501 # Simulator instruction rate (inst/s) -host_mem_usage 278608 # Number of bytes of host memory used -host_seconds 30.21 # Real time elapsed on the host -host_tick_rate 61910551280 # Simulator tick rate (ticks/s) +host_inst_rate 3116744 # Simulator instruction rate (inst/s) +host_mem_usage 276812 # Number of bytes of host memory used +host_seconds 20.26 # Real time elapsed on the host +host_tick_rate 92302855126 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -699,14 +699,22 @@ system.l2c.ReadReq_miss_rate::1 0.040193 # mi system.l2c.ReadReq_misses::0 958815 # number of ReadReq misses system.l2c.ReadReq_misses::1 5721 # number of ReadReq misses system.l2c.ReadReq_misses::total 964536 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 117429 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 7578 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 125007 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 26914 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 2297 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29211 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 26914 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 2297 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29211 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 90515 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 5281 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 95796 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 117429 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 7578 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 125007 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 90515 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 5281 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 95796 # number of UpgradeReq misses system.l2c.Writeback_accesses::0 427641 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 427641 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 427641 # number of Writeback hits diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 5eca545be..372087060 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -157,7 +157,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +177,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -303,7 +303,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index a264b4253..af78d2d19 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:39:16 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 8a27a93dd..7a54ae203 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2156504 # Simulator instruction rate (inst/s) -host_mem_usage 277176 # Number of bytes of host memory used -host_seconds 27.84 # Real time elapsed on the host -host_tick_rate 65706739181 # Simulator tick rate (ticks/s) +host_inst_rate 3274924 # Simulator instruction rate (inst/s) +host_mem_usage 275440 # Number of bytes of host memory used +host_seconds 18.33 # Real time elapsed on the host +host_tick_rate 99783911231 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -405,11 +405,16 @@ system.l2c.ReadReq_hits::total 1696652 # nu system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 124945 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 29867 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29867 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 29867 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29867 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 95078 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 95078 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 124945 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 124945 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 95078 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 95078 # number of UpgradeReq misses system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 428893 # number of Writeback hits diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 9ac931352..004d84e5f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -258,7 +258,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -278,7 +278,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -404,7 +404,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr index e077a7fd9..83c71fc5c 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -2,6 +2,4 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: 591544000: Trying to launch CPU number 1! -For more information see: http://www.m5sim.org/warn/8f7d2563 hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index e1106068b..24b896c4e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:33:27 -M5 executing on SC2B0619 +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:43:55 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... +info: Launching CPU 1 @ 591544000 Exiting @ tick 1972135461000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 2f0d6d26e..c2f737377 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 561145 # Simulator instruction rate (inst/s) -host_mem_usage 275328 # Number of bytes of host memory used -host_seconds 105.89 # Real time elapsed on the host -host_tick_rate 18624028525 # Simulator tick rate (ticks/s) +host_inst_rate 1520606 # Simulator instruction rate (inst/s) +host_mem_usage 273632 # Number of bytes of host memory used +host_seconds 39.08 # Real time elapsed on the host +host_tick_rate 50467758461 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated @@ -858,26 +858,46 @@ system.l2c.ReadReq_mshr_miss_rate::2 inf # ms system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 120870 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 6368 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 127238 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 53414.453545 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 1013851.287688 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 27944 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 1988 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29932 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 55471.228171 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 779722.334004 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.405452 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1550088000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 27944 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 1988 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29932 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1197352000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.071142 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 15.056338 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses 29932 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 92926 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4380 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 97306 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52795.955922 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 1120118.036530 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6456205000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.114731 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 4906117000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 120870 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 6368 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 127238 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5090187000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.052685 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 19.980842 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 92926 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 4380 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 97306 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 3892835000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.047134 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 22.215982 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 127238 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 97306 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 430351 # number of Writeback accesses(hits+misses) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index e4db07faf..96d83e36f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -154,7 +154,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -174,7 +174,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -300,7 +300,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 36f5fe7a9..7b8726b2e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:12 -M5 executing on SC2B0619 +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:44:55 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1930164593000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index fafd614fd..f93fce19a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 828053 # Simulator instruction rate (inst/s) -host_mem_usage 274124 # Number of bytes of host memory used -host_seconds 67.88 # Real time elapsed on the host -host_tick_rate 28436098912 # Simulator tick rate (ticks/s) +host_inst_rate 1511189 # Simulator instruction rate (inst/s) +host_mem_usage 272256 # Number of bytes of host memory used +host_seconds 37.19 # Real time elapsed on the host +host_tick_rate 51895589412 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56205703 # Number of instructions simulated sim_seconds 1.930165 # Number of seconds simulated @@ -501,21 +501,36 @@ system.l2c.ReadReq_mshr_miss_rate::1 inf # ms system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 126223 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 126223 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52001.810288 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 30004 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 30004 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.366085 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.366085 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1560339000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 30004 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 30004 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 1200291000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses 30004 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 96219 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 96219 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52001.013313 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.391669 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 5003485500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 126223 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 126223 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 96219 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 96219 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 3849375000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 96219 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses) |