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authorAndreas Hansson <andreas.hansson@arm.com>2012-07-12 12:56:13 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-07-12 12:56:13 -0400
commitf00cba34eb8e6bf947721f72de314f4e8bd6a8f8 (patch)
tree432ab17d82d72d5042758f25066dc64558c9a7f8 /tests
parent55bfe13705a3eccdffb6846dd87df5f190b04c99 (diff)
downloadgem5-f00cba34eb8e6bf947721f72de314f4e8bd6a8f8.tar.xz
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/memtest-ruby.py6
-rw-r--r--tests/configs/memtest.py6
2 files changed, 10 insertions, 2 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 008daa1ad..560a8fd65 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -79,6 +79,7 @@ options.num_cpus = nb_cores
# system simulated
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory())
Ruby.create_system(options, system)
@@ -91,7 +92,7 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
# physmem, respectively
#
cpus[i].test = ruby_port.slave
- cpus[i].functional = system.funcmem.port
+ cpus[i].functional = system.funcbus.slave
#
# Since the memtester is incredibly bursty, increase the deadlock
@@ -105,6 +106,9 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
#
ruby_port.access_phys_mem = False
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
# -----------------------
# run simulation
# -----------------------
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 0add2158f..57f45b1d4 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -57,6 +57,7 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
membus = CoherentBus(clock="500GHz", width=16))
@@ -73,10 +74,13 @@ for cpu in cpus:
cpu.l1c = L1(size = '32kB', assoc = 4)
cpu.l1c.cpu_side = cpu.test
cpu.l1c.mem_side = system.toL2Bus.slave
- system.funcmem.port = cpu.functional
+ system.funcbus.slave = cpu.functional
system.system_port = system.membus.slave
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
# connect memory to membus
system.physmem.port = system.membus.master