mem: Move crossbar default latencies to subclasses

This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the different uses in the system. We
use the crossbar in a wide range of places: interfacing cores to the
L2, as a system interconnect, connecting I/O and peripherals,
etc. Needless to say, these crossbars have very different performance,
and the clock frequency alone is not enough to distinguish these
scenarios.

Instead of trying to capture every possible case, this patch
introduces dedicated subclasses for the three primary use-cases:
L2XBar, SystemXBar and IOXbar. More can be added if needed, and the
defaults can be overridden.

8 files changed, 12 insertions, 12 deletions

diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 5637ca3f5..c440d48d9 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -104,7 +104,7 @@ class BaseSystem(object):
         Returns:
           A bus that CPUs should use to connect to the shared cache.
         """
-        system.toL2Bus = CoherentXBar(clk_domain=system.cpu_clk_domain)
+        system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
         system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
                              size='4MB', assoc=8)
         system.l2c.cpu_side = system.toL2Bus.master
@@ -186,7 +186,7 @@ class BaseSESystem(BaseSystem):
 
     def create_system(self):
         system = System(physmem = self.mem_class(),
-                        membus = CoherentXBar(),
+                        membus = SystemXBar(),
                         mem_mode = self.mem_mode)
         system.system_port = system.membus.slave
         system.physmem.port = system.membus.master
diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py
index 42dd05639..34ac75f00 100644
--- a/tests/configs/memtest-filter.py
+++ b/tests/configs/memtest-filter.py
@@ -38,7 +38,7 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
 # system simulated
 system = System(cpu = cpus,
                 physmem = SimpleMemory(),
-                membus = CoherentXBar(width=16, snoop_filter = SnoopFilter()))
+                membus = SystemXBar(width=16, snoop_filter = SnoopFilter()))
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain()
 system.clk_domain = SrcClockDomain(clock = '1GHz',
@@ -49,8 +49,8 @@ system.clk_domain = SrcClockDomain(clock = '1GHz',
 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
                                        voltage_domain = system.voltage_domain)
 
-system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16,
-                              snoop_filter = SnoopFilter())
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain,
+                        snoop_filter = SnoopFilter())
 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 42f50ce3b..5bbfeb774 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -38,7 +38,7 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
 # system simulated
 system = System(cpu = cpus,
                 physmem = SimpleMemory(),
-                membus = CoherentXBar(width=16))
+                membus = SystemXBar())
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain()
 system.clk_domain = SrcClockDomain(clock = '1GHz',
@@ -49,7 +49,7 @@ system.clk_domain = SrcClockDomain(clock = '1GHz',
 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
                                        voltage_domain = system.voltage_domain)
 
-system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16)
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 3fea4ed71..fb2d56fd1 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -38,7 +38,7 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentXBar(),
+system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
                 mem_mode = "timing",
                 clk_domain = SrcClockDomain(clock = '1GHz'))
 
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 68a07e702..c47d9f355 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -39,7 +39,7 @@ cpu = DerivO3CPU(cpu_id=0)
 
 system = System(cpu = cpu,
                 physmem = ruby_memory,
-                membus = CoherentXBar(),
+                membus = SystemXBar(),
                 mem_mode = "timing",
                 clk_domain = SrcClockDomain(clock = '1GHz'))
 
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 321cb977f..bdda6d005 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -38,7 +38,7 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentXBar(),
+system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
                 clk_domain = SrcClockDomain(clock = '1GHz'))
 
 # Create a seperate clock domain for components that should run at
diff --git a/tests/configs/tgen-dram-ctrl.py b/tests/configs/tgen-dram-ctrl.py
index d170ac077..cd6721e6d 100644
--- a/tests/configs/tgen-dram-ctrl.py
+++ b/tests/configs/tgen-dram-ctrl.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-dram-ctrl.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = DDR3_1600_x64(),
-                membus = NoncoherentXBar(width = 16),
+                membus = IOXBar(width = 16),
                 clk_domain = SrcClockDomain(clock = '1GHz',
                                             voltage_domain =
                                             VoltageDomain()))
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py
index be700ac7a..edb2f9fcd 100644
--- a/tests/configs/tgen-simple-mem.py
+++ b/tests/configs/tgen-simple-mem.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = SimpleMemory(),
-                membus = NoncoherentXBar(width = 16),
+                membus = IOXBar(width = 16),
                 clk_domain = SrcClockDomain(clock = '1GHz',
                                             voltage_domain =
                                             VoltageDomain()))