diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
| commit | 999cd8aef5dfa3c22b02b55420608fbb8d7e7822 (patch) | |
| tree | 98f11453678ed2be66b2ae3239b0ee42ad6f4e05 /tests | |
| parent | b94f84196924d60d4d4677929ddb6f677e3d96d9 (diff) | |
| download | gem5-999cd8aef5dfa3c22b02b55420608fbb8d7e7822.tar.xz | |
StoreSet: Update stats for store-set clearing
Diffstat (limited to 'tests')
69 files changed, 10206 insertions, 10133 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 55c96d241..cdf647d08 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 5c5a7a6e9..81484db61 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 18:05:21 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 14:50:17 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -39,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 145175788500 because target called exit() +Exiting @ tick 145301847500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 4f3a6d8f3..5c2b0fbb8 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145176 # Number of seconds simulated -sim_ticks 145175788500 # Number of ticks simulated +sim_seconds 0.145302 # Number of seconds simulated +sim_ticks 145301847500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116167 # Simulator instruction rate (inst/s) -host_tick_rate 29819633 # Simulator tick rate (ticks/s) -host_mem_usage 246468 # Number of bytes of host memory used -host_seconds 4868.46 # Real time elapsed on the host +host_inst_rate 168398 # Simulator instruction rate (inst/s) +host_tick_rate 43264868 # Simulator tick rate (ticks/s) +host_mem_usage 252140 # Number of bytes of host memory used +host_seconds 3358.43 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125726238 # DTB read hits -system.cpu.dtb.read_misses 26702 # DTB read misses +system.cpu.dtb.read_hits 125931819 # DTB read hits +system.cpu.dtb.read_misses 26714 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125752940 # DTB read accesses -system.cpu.dtb.write_hits 41507366 # DTB write hits -system.cpu.dtb.write_misses 32028 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 41539394 # DTB write accesses -system.cpu.dtb.data_hits 167233604 # DTB hits -system.cpu.dtb.data_misses 58730 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 167292334 # DTB accesses -system.cpu.itb.fetch_hits 71588816 # ITB hits +system.cpu.dtb.read_accesses 125958533 # DTB read accesses +system.cpu.dtb.write_hits 41424543 # DTB write hits +system.cpu.dtb.write_misses 32276 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 41456819 # DTB write accesses +system.cpu.dtb.data_hits 167356362 # DTB hits +system.cpu.dtb.data_misses 58990 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 167415352 # DTB accesses +system.cpu.itb.fetch_hits 71387266 # ITB hits system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 71588856 # ITB accesses +system.cpu.itb.fetch_accesses 71387306 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 290351578 # number of cpu cycles simulated +system.cpu.numCycles 290603696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 82068439 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75472139 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4139210 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77758293 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69764860 # Number of BTB hits +system.cpu.BPredUnit.lookups 81919814 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75390266 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4129357 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77614173 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69618230 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1965418 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 74381248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 740847057 # Number of instructions fetch has processed -system.cpu.fetch.Branches 82068439 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71730278 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 139388095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17359106 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 63481916 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1955958 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74192269 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 739424750 # Number of instructions fetch has processed +system.cpu.fetch.Branches 81919814 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71574188 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139080989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17172234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 64410456 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 71588816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1228525 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 290282404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.552160 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199400 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 71387266 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1210642 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290534603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.545049 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.198246 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 150894309 51.98% 51.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11757724 4.05% 56.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15902063 5.48% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15874475 5.47% 66.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13293221 4.58% 71.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15622251 5.38% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6768599 2.33% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3592047 1.24% 80.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56577715 19.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151453614 52.13% 52.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11687885 4.02% 56.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15898742 5.47% 61.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15854935 5.46% 67.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13240035 4.56% 71.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15603650 5.37% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6697784 2.31% 79.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3574182 1.23% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56523776 19.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 290282404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.282652 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.551552 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 90540829 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 49762589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 127167334 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9782311 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13029341 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4494723 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 873 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 729210837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3260 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 13029341 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98854754 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12652695 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 558 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 123369042 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42376014 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 715226972 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32893526 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4012041 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 545137745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 939207717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 939205613 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2104 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290534603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281895 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.544444 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90310656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 50731551 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 126219695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10423604 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12849097 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4446391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 727740839 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3152 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12849097 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 98621596 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12675857 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123066068 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43321346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 713725381 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 266 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 34127954 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3740820 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 543893835 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 937350842 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 937348775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2067 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 81282856 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 82693608 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 131825687 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43890067 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17591169 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7047053 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 644543109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 621562613 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 380292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77712656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42125820 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 290282404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.141234 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.879500 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 80038946 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 85210895 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131427932 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43788464 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14719547 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6869694 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 643138163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 621184561 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 428348 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 76303449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41228761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 290534603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.138074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876724 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 70571105 24.31% 24.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 58751148 20.24% 44.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 55824387 19.23% 63.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31456534 10.84% 74.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 33062190 11.39% 86.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24005083 8.27% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12272709 4.23% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3831324 1.32% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 507924 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 70371393 24.22% 24.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 59001774 20.31% 44.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 56407615 19.42% 63.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31734464 10.92% 74.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32252552 11.10% 85.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24569230 8.46% 94.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11680867 4.02% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3911059 1.35% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 605649 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 290282404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290534603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4555010 86.10% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 57 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 523123 9.89% 95.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 212105 4.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4149748 79.41% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 46 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 644138 12.33% 91.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 431804 8.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 451240060 72.60% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7852 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 128169032 20.62% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42145620 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 450716451 72.56% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7786 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 128329931 20.66% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42130345 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 621562613 # Type of FU issued -system.cpu.iq.rate 2.140724 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5290295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008511 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1539074805 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 722600568 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 609952454 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3412 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1900 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1604 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 626851187 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1721 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11465807 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 621184561 # Type of FU issued +system.cpu.iq.rate 2.137566 # Inst issue rate +system.cpu.iq.fu_busy_cnt 5225736 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008413 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1538554428 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 719791910 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 609163875 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3381 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1606 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 626408589 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1708 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11777609 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17311645 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67694 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 365195 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4438746 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16913890 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 148570 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 370604 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4337143 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5929 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50756 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5917 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50743 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13029341 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1515549 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101263 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 690142973 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2399318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 131825687 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43890067 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41006 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13792 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 365195 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4054325 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 604453 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4658778 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 614025387 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125753017 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7537226 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12849097 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1534890 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101054 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 688747962 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2386448 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 131427932 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43788464 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 40995 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13802 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 370604 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4041048 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 603771 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4644819 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 613556554 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125958678 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7628007 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45599835 # number of nop insts executed -system.cpu.iew.exec_refs 167311882 # number of memory reference insts executed -system.cpu.iew.exec_branches 68605174 # Number of branches executed -system.cpu.iew.exec_stores 41558865 # Number of stores executed -system.cpu.iew.exec_rate 2.114765 # Inst execution rate -system.cpu.iew.wb_sent 611451889 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 609954058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420339317 # num instructions producing a value -system.cpu.iew.wb_consumers 532241742 # num instructions consuming a value +system.cpu.iew.exec_nop 45609769 # number of nop insts executed +system.cpu.iew.exec_refs 167435052 # number of memory reference insts executed +system.cpu.iew.exec_branches 68567792 # Number of branches executed +system.cpu.iew.exec_stores 41476374 # Number of stores executed +system.cpu.iew.exec_rate 2.111317 # Inst execution rate +system.cpu.iew.wb_sent 610651273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 609165481 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420066604 # num instructions producing a value +system.cpu.iew.wb_consumers 531633628 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.100743 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789753 # average fanout of values written-back +system.cpu.iew.wb_rate 2.096207 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 88132303 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 86736991 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4138394 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 277253063 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.170786 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.607112 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4128553 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 277685506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.167405 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.598933 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91432186 32.98% 32.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 75471271 27.22% 60.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31359713 11.31% 71.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9812345 3.54% 75.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10073105 3.63% 78.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21591836 7.79% 86.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5927353 2.14% 88.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2268519 0.82% 89.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29316735 10.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91049633 32.79% 32.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 76164348 27.43% 60.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31609265 11.38% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9610599 3.46% 75.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10212120 3.68% 78.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21618987 7.79% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6091791 2.19% 88.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2481977 0.89% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 28846786 10.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 277253063 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 277685506 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29316735 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 28846786 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 937861205 # The number of ROB reads -system.cpu.rob.rob_writes 1393014626 # The number of ROB writes -system.cpu.timesIdled 2237 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 69174 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 937368285 # The number of ROB reads +system.cpu.rob.rob_writes 1390043178 # The number of ROB writes +system.cpu.timesIdled 2213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69093 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.513395 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.513395 # CPI: Total CPI of All Threads -system.cpu.ipc 1.947819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.947819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 864633877 # number of integer regfile reads -system.cpu.int_regfile_writes 501928899 # number of integer regfile writes -system.cpu.fp_regfile_reads 273 # number of floating regfile reads -system.cpu.fp_regfile_writes 57 # number of floating regfile writes +system.cpu.cpi 0.513840 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.513840 # CPI: Total CPI of All Threads +system.cpu.ipc 1.946130 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.946130 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 864034550 # number of integer regfile reads +system.cpu.int_regfile_writes 501250515 # number of integer regfile writes +system.cpu.fp_regfile_reads 281 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 799.817467 # Cycle average of tags in use -system.cpu.icache.total_refs 71587538 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 76076.023379 # Average number of references to valid blocks. +system.cpu.icache.replacements 34 # number of replacements +system.cpu.icache.tagsinuse 800.952347 # Cycle average of tags in use +system.cpu.icache.total_refs 71385990 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 75700.943796 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 799.817467 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.390536 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 71587538 # number of ReadReq hits -system.cpu.icache.demand_hits 71587538 # number of demand (read+write) hits -system.cpu.icache.overall_hits 71587538 # number of overall hits -system.cpu.icache.ReadReq_misses 1278 # number of ReadReq misses -system.cpu.icache.demand_misses 1278 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1278 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 45985500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 45985500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 45985500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 71588816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 71588816 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 71588816 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 800.952347 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.391090 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 71385990 # number of ReadReq hits +system.cpu.icache.demand_hits 71385990 # number of demand (read+write) hits +system.cpu.icache.overall_hits 71385990 # number of overall hits +system.cpu.icache.ReadReq_misses 1276 # number of ReadReq misses +system.cpu.icache.demand_misses 1276 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1276 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 46038500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 46038500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 46038500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 71387266 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 71387266 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 71387266 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35982.394366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35982.394366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35982.394366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36080.329154 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36080.329154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36080.329154 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 333 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 333 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33582500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33582500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33582500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33661000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33661000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33661000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35688.097768 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35688.097768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35688.097768 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35695.652174 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470793 # number of replacements -system.cpu.dcache.tagsinuse 4093.950327 # Cycle average of tags in use -system.cpu.dcache.total_refs 151670470 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474889 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 319.380887 # Average number of references to valid blocks. +system.cpu.dcache.replacements 470870 # number of replacements +system.cpu.dcache.tagsinuse 4093.952106 # Cycle average of tags in use +system.cpu.dcache.total_refs 151563529 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474966 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 319.103955 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.950327 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4093.952106 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113522942 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147524 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits 113415940 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147585 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151670466 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151670466 # number of overall hits -system.cpu.dcache.ReadReq_misses 730602 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303797 # number of WriteReq misses -system.cpu.dcache.demand_misses 2034399 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2034399 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11799452000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19635094216 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31434546216 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31434546216 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114253544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 151563525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151563525 # number of overall hits +system.cpu.dcache.ReadReq_misses 731363 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303736 # number of WriteReq misses +system.cpu.dcache.demand_misses 2035099 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2035099 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11802867000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19634898764 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31437765764 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31437765764 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 114147303 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153704865 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153704865 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006395 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033048 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013236 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16150.314398 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15059.932042 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15451.514780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15451.514780 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 884996 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 153598624 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153598624 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006407 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033047 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013249 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013249 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16138.178989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15060.486758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15447.782031 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15447.782031 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 886996 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7629.275862 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7646.517241 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423112 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 511747 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047763 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1559510 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1559510 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218855 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256034 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474889 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474889 # number of overall MSHR misses +system.cpu.dcache.writebacks 423193 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 512453 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047680 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1560133 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1560133 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218910 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256056 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474966 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474966 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640196500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3028456494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4668652994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4668652994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640097000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3028332494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4668429494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4668429494 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001918 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7494.443810 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11828.337229 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9831.040504 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9831.040504 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.003092 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003092 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7492.106345 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11826.836684 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74461 # number of replacements -system.cpu.l2cache.tagsinuse 17667.693378 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478022 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90361 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290136 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74473 # number of replacements +system.cpu.l2cache.tagsinuse 17668.898791 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478122 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90370 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.290716 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1746.744701 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15920.948677 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053306 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485869 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186848 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423112 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196221 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383069 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383069 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32948 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59813 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92761 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92761 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133336500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2066482500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3199819000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3199819000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219796 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423112 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475830 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475830 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.149903 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233614 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194946 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194946 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.732791 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.052881 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34495.305139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34495.305139 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 460000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1750.296576 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15918.602215 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053415 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485797 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186900 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423193 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196240 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 383140 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 383140 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32953 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59816 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92769 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92769 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133504500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2066596000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3200100500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3200100500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219853 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423193 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256056 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475909 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475909 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.149887 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233605 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194930 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194930 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.611750 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.217601 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34495.364831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34495.364831 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 453500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 71 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6478.873239 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5967.105263 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59333 # number of writebacks +system.cpu.l2cache.writebacks 59331 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32948 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59813 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92761 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92761 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32953 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59816 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92769 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1878097000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2900110500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2900110500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022169500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1878238500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2900408000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2900408000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149903 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233614 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194946 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194946 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.984460 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31399.478374 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.329837 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.329837 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149887 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233605 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194930 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194930 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.011926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31400.269159 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 485873d05..fea8ea4a1 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index eb566e6f8..a9117199d 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 00:35:36 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 20:12:24 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 181676511500 because target called exit() +Exiting @ tick 181028108500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 212b723af..701011da6 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.181677 # Number of seconds simulated -sim_ticks 181676511500 # Number of ticks simulated +sim_seconds 0.181028 # Number of seconds simulated +sim_ticks 181028108500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82416 # Simulator instruction rate (inst/s) -host_tick_rate 24857445 # Simulator tick rate (ticks/s) -host_mem_usage 257796 # Number of bytes of host memory used -host_seconds 7308.74 # Real time elapsed on the host -sim_insts 602359820 # Number of instructions simulated +host_inst_rate 110603 # Simulator instruction rate (inst/s) +host_tick_rate 33239774 # Simulator tick rate (ticks/s) +host_mem_usage 263548 # Number of bytes of host memory used +host_seconds 5446.13 # Real time elapsed on the host +sim_insts 602359805 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 363353024 # number of cpu cycles simulated +system.cpu.numCycles 362056218 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 93642406 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86055517 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3937297 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 88612742 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 82226729 # Number of BTB hits +system.cpu.BPredUnit.lookups 93448154 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 85911629 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3923569 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 88397798 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81789381 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1811116 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1799 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 80077128 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 720176236 # Number of instructions fetch has processed -system.cpu.fetch.Branches 93642406 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84037845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163199656 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20933611 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102893232 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 623 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 77424762 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1579270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 362477887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.976296 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1790445 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1821 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 79878814 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 718366767 # Number of instructions fetch has processed +system.cpu.fetch.Branches 93448154 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83579826 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162526152 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20714981 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102669649 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 77174070 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1530906 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 361172763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.127936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.978152 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199278398 54.98% 54.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25830413 7.13% 62.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19932307 5.50% 67.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 25118126 6.93% 74.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12539166 3.46% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13666852 3.77% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4829528 1.33% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7994396 2.21% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53288701 14.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198646777 55.00% 55.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25571456 7.08% 62.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 19827264 5.49% 67.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25093348 6.95% 74.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12488036 3.46% 77.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13650153 3.78% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4767489 1.32% 83.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7787203 2.16% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53341037 14.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 362477887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257717 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.982029 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 102756406 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83077250 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 141158544 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19181042 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16304645 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6938686 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2613 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 758024516 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7262 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 16304645 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 116075491 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10185612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 146924183 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72878598 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 743558817 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 188 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 58921601 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10117687 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 591 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 767454765 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3458233737 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3458233609 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 361172763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258104 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.984130 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 102343616 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83020024 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 140521738 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19192459 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16094926 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6886310 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2563 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 756045465 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7091 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 16094926 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 115645953 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9675212 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 105916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 146342748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73308008 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 741744489 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59347402 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10155907 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 308 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 765934734 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3449682594 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3449682466 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417418 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 140037342 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6399 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6398 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 130096693 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 183828757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85345746 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 25811031 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37497456 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 715547655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7366 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 667339389 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 840250 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 112563133 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 285197370 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1065 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 362477887 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.841049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.675765 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 138517335 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6417 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6420 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 130475053 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 183427028 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85118109 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 19617047 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24959505 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 714042486 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 668482439 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 813187 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 110903932 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 272103092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1046 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 361172763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.850866 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.720469 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89414922 24.67% 24.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90190265 24.88% 49.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 79396670 21.90% 71.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 45359007 12.51% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28036434 7.73% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16328709 4.50% 96.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8232346 2.27% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 5060866 1.40% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 458668 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89609578 24.81% 24.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 92103808 25.50% 50.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76957239 21.31% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 43677932 12.09% 83.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26190048 7.25% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 17902760 4.96% 95.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7158113 1.98% 97.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6378593 1.77% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1194692 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 362477887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 361172763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 175813 5.16% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2586346 75.94% 81.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 643459 18.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 174743 4.36% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2924154 73.03% 77.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 905037 22.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 414934483 62.18% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6549 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174108289 26.09% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 78290065 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 414572332 62.02% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6557 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174888345 26.16% 88.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79015202 11.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 667339389 # Type of FU issued -system.cpu.iq.rate 1.836614 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3405618 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005103 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1701402497 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 828782976 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 653330026 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 668482439 # Type of FU issued +system.cpu.iq.rate 1.846350 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4003934 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005990 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1702954726 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 825626408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 654174988 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 670744987 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 672486353 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 28288943 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 28890587 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34876158 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 159827 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 665311 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 15124729 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34474432 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123741 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 677004 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 14897095 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15440 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12578 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 16171 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12604 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16304645 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 784511 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 50454 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 715624477 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2065189 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 183828757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85345746 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6034 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13250 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5066 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 665311 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4094363 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 486296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4580659 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659689382 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 170637671 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7650007 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16094926 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 778321 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 50892 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 714119394 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2033981 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 183427028 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85118109 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6015 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12993 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 677004 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4081658 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 498372 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4580030 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 660769173 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171345747 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7713266 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69456 # number of nop insts executed -system.cpu.iew.exec_refs 247330517 # number of memory reference insts executed -system.cpu.iew.exec_branches 76920251 # Number of branches executed -system.cpu.iew.exec_stores 76692846 # Number of stores executed -system.cpu.iew.exec_rate 1.815560 # Inst execution rate -system.cpu.iew.wb_sent 655349780 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 653330042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 425170180 # num instructions producing a value -system.cpu.iew.wb_consumers 661395893 # num instructions consuming a value +system.cpu.iew.exec_nop 69564 # number of nop insts executed +system.cpu.iew.exec_refs 248875630 # number of memory reference insts executed +system.cpu.iew.exec_branches 76892303 # Number of branches executed +system.cpu.iew.exec_stores 77529883 # Number of stores executed +system.cpu.iew.exec_rate 1.825046 # Inst execution rate +system.cpu.iew.wb_sent 656292597 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 654175004 # cumulative count of insts written-back +system.cpu.iew.wb_producers 424501609 # num instructions producing a value +system.cpu.iew.wb_consumers 659455960 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.798059 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642838 # average fanout of values written-back +system.cpu.iew.wb_rate 1.806833 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643715 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359871 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 113270616 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6301 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3996549 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 346173243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.740053 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.116155 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 111769419 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6298 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3982936 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345077838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.745577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.124891 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 112054418 32.37% 32.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 109168598 31.54% 63.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49782434 14.38% 78.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10491888 3.03% 81.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23443534 6.77% 88.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14637280 4.23% 92.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8029663 2.32% 94.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1511197 0.44% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17054231 4.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 111837000 32.41% 32.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 108539519 31.45% 63.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49573446 14.37% 78.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10197254 2.96% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23493632 6.81% 87.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14599312 4.23% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8154465 2.36% 94.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1281875 0.37% 94.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 17401335 5.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 346173243 # Number of insts commited each cycle -system.cpu.commit.count 602359871 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 345077838 # Number of insts commited each cycle +system.cpu.commit.count 602359856 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173615 # Number of memory references committed -system.cpu.commit.loads 148952598 # Number of loads committed +system.cpu.commit.refs 219173609 # Number of memory references committed +system.cpu.commit.loads 148952595 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828605 # Number of branches committed +system.cpu.commit.branches 70828602 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522655 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522643 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 17054231 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 17401335 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1044748887 # The number of ROB reads -system.cpu.rob.rob_writes 1447602374 # The number of ROB writes -system.cpu.timesIdled 36933 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 875137 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359820 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359820 # Number of Instructions Simulated -system.cpu.cpi 0.603216 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.603216 # CPI: Total CPI of All Threads -system.cpu.ipc 1.657781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.657781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3292742614 # number of integer regfile reads -system.cpu.int_regfile_writes 679039343 # number of integer regfile writes +system.cpu.rob.rob_reads 1041805166 # The number of ROB reads +system.cpu.rob.rob_writes 1444392656 # The number of ROB writes +system.cpu.timesIdled 37065 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 883455 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359805 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated +system.cpu.cpi 0.601063 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.601063 # CPI: Total CPI of All Threads +system.cpu.ipc 1.663719 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.663719 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3299876653 # number of integer regfile reads +system.cpu.int_regfile_writes 679084326 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 961073357 # number of misc regfile reads -system.cpu.misc_regfile_writes 2664 # number of misc regfile writes -system.cpu.icache.replacements 52 # number of replacements -system.cpu.icache.tagsinuse 658.859257 # Cycle average of tags in use -system.cpu.icache.total_refs 77423742 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 99644.455598 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 960654614 # number of misc regfile reads +system.cpu.misc_regfile_writes 2658 # number of misc regfile writes +system.cpu.icache.replacements 39 # number of replacements +system.cpu.icache.tagsinuse 659.213464 # Cycle average of tags in use +system.cpu.icache.total_refs 77173072 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 101410.081472 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 658.859257 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.321709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 77423742 # number of ReadReq hits -system.cpu.icache.demand_hits 77423742 # number of demand (read+write) hits -system.cpu.icache.overall_hits 77423742 # number of overall hits -system.cpu.icache.ReadReq_misses 1020 # number of ReadReq misses -system.cpu.icache.demand_misses 1020 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35800500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35800500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 77424762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 77424762 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 77424762 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 659.213464 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.321882 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 77173072 # number of ReadReq hits +system.cpu.icache.demand_hits 77173072 # number of demand (read+write) hits +system.cpu.icache.overall_hits 77173072 # number of overall hits +system.cpu.icache.ReadReq_misses 998 # number of ReadReq misses +system.cpu.icache.demand_misses 998 # number of demand (read+write) misses +system.cpu.icache.overall_misses 998 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 34962500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 34962500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 34962500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 77174070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 77174070 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 77174070 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35098.529412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35098.529412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35098.529412 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35032.565130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35032.565130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35032.565130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 243 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 243 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 243 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 777 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 777 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 777 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 762 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 762 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 762 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26636000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26035000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26035000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26035000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34280.566281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34166.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440951 # number of replacements -system.cpu.dcache.tagsinuse 4094.785016 # Cycle average of tags in use -system.cpu.dcache.total_refs 208890975 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445047 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 469.368348 # Average number of references to valid blocks. +system.cpu.dcache.replacements 441073 # number of replacements +system.cpu.dcache.tagsinuse 4094.780664 # Cycle average of tags in use +system.cpu.dcache.total_refs 208769486 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445169 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 468.966810 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.785016 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999703 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 140815101 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 68073201 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1331 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 208888302 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 208888302 # number of overall hits -system.cpu.dcache.ReadReq_misses 248858 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1344330 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 4094.780664 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999702 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 140903051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67863771 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1333 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 208766822 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 208766822 # number of overall hits +system.cpu.dcache.ReadReq_misses 249137 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1553760 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1593188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1593188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3280375500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 26109782527 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 29390158027 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 29390158027 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 141063959 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1802897 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1802897 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3284237500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 27026235527 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30310473027 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30310473027 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 141152188 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1351 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1331 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 210481490 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 210481490 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.019366 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.006662 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.007569 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.007569 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13181.716079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19422.152691 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 21555.555556 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18447.388524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18447.388524 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 1342 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 210569719 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 210569719 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001765 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.022383 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.006706 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008562 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008562 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13182.455838 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17394.086298 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 22166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 16812.093551 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 16812.093551 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -422,70 +422,72 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51168 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1096973 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 395116 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51340 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1306387 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1148141 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1148141 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197690 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247357 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445047 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445047 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1357727 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1357727 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197797 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247373 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445170 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445170 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1624799500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2561111027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4185910527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4185910527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1624472000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2544428527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4168900527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4168900527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8218.926096 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.905598 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8212.824259 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.797266 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72983 # number of replacements -system.cpu.l2cache.tagsinuse 17823.829612 # Cycle average of tags in use -system.cpu.l2cache.total_refs 421659 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88508 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.764078 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72968 # number of replacements +system.cpu.l2cache.tagsinuse 17823.256167 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421257 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.760396 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1903.131187 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15920.698425 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058079 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485861 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165659 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395037 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 188979 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354638 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354638 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32805 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58381 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91186 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91186 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126836000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2004580000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3131416000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3131416000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198464 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247360 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 445824 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 445824 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236016 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204534 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204534 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.519890 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.171015 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34340.973395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34340.973395 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1903.843188 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15919.412978 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058101 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485822 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165755 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395116 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 189016 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354771 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354771 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32799 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58360 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91159 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91159 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126738500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2004231000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3130969500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3130969500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198554 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395116 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247376 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 445930 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 445930 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235916 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204424 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204424 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34352.830879 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34342.546265 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34346.246668 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34346.246668 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -494,28 +496,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58139 # number of writebacks +system.cpu.l2cache.writebacks 58122 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32796 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58381 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91177 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91177 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32790 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58360 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020208500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822855000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2843063500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2843063500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1020255000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822537500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2842792500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2842792500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165249 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236016 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204513 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.711306 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31223.428855 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165144 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235916 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204404 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204404 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.821592 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31229.223783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index d391b02a1..69d6d5791 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index a3848a023..f40ea4f95 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 18 2011 18:04:45 -gem5 started Jul 18 2011 18:04:49 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 16:58:37 +gem5 started Aug 17 2011 16:59:36 +gem5 executing on nadc-0388 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 568878317500 because target called exit() +Exiting @ tick 424846003000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index cb1a626e1..386994981 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,251 +1,252 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.568878 # Number of seconds simulated -sim_ticks 568878317500 # Number of ticks simulated +sim_seconds 0.424846 # Number of seconds simulated +sim_ticks 424846003000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127390 # Simulator instruction rate (inst/s) -host_tick_rate 51557660 # Simulator tick rate (ticks/s) -host_mem_usage 254284 # Number of bytes of host memory used -host_seconds 11033.83 # Real time elapsed on the host +host_inst_rate 130905 # Simulator instruction rate (inst/s) +host_tick_rate 39566335 # Simulator tick rate (ticks/s) +host_mem_usage 260032 # Number of bytes of host memory used +host_seconds 10737.56 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1137756636 # number of cpu cycles simulated +system.cpu.numCycles 849692007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 106888514 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 95381218 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5420176 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 103841112 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 102522993 # Number of BTB hits +system.cpu.BPredUnit.lookups 103951242 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 92817618 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5441892 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 101027131 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 99845588 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180638334 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1773593568 # Number of instructions fetch has processed -system.cpu.fetch.Branches 106888514 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 102524223 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 381465937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37837382 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 543268181 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1639 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 176102907 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 948661 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1137451065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.563275 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.753191 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1240 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 176461208 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1731297968 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103951242 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99846828 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 372380430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 32542357 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 273950532 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1598 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 171982366 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1072419 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 849334249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.043796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.987927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 755985128 66.46% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 84858619 7.46% 73.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 46317326 4.07% 78.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24386522 2.14% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 34286806 3.01% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 34702861 3.05% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 15288834 1.34% 87.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7898837 0.69% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 133726132 11.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 476953819 56.16% 56.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 82874443 9.76% 65.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45104012 5.31% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23823207 2.80% 74.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 33449263 3.94% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 34018296 4.01% 81.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14934889 1.76% 83.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7594649 0.89% 84.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 130581671 15.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1137451065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093947 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.558851 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 242051252 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 485212822 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 328784553 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49325481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 32076957 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1761674668 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 32076957 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 305517434 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 121834770 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 66846353 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 312365178 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 298810373 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1743986914 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 179337186 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 63010596 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 40441846 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1455333902 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2943882462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2909924571 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33957891 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 849334249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122340 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.037559 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 228750775 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 225010682 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 340329593 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 28702732 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 26540467 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1719853048 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 26540467 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 263479088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 41404306 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55665718 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333164025 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 129080645 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1702621917 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 27946870 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 65424391 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16478266 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1420563184 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2876973295 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2842990293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33983002 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 210563450 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3348344 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3348760 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 542381303 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 470273369 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 190181130 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 405202372 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 165490113 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1617272450 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3218242 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1489328778 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 214120992 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 291680058 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 974571 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1137451065 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.140672 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 175792732 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3237844 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3287220 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 297721307 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 456905033 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 186186881 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 277685429 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 94682535 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1573041480 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3078086 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1493571680 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 168879 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 169173312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193746620 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 834415 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 849334249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.758520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.350284 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 308893636 27.16% 27.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 389103497 34.21% 61.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 284410316 25.00% 86.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 106768220 9.39% 95.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 33533421 2.95% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12093348 1.06% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2169743 0.19% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 349965 0.03% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128919 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 177901650 20.95% 20.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 206358445 24.30% 45.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 226462970 26.66% 71.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151667203 17.86% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 64968416 7.65% 97.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14273144 1.68% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6071046 0.71% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1430974 0.17% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 200401 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1137451065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 849334249 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 267660 8.55% 8.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 151678 4.84% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2460340 78.58% 91.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 251345 8.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 106837 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 176348 8.29% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1497549 70.41% 83.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 346224 16.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 892252171 59.91% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2624686 0.18% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 423006461 28.40% 88.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171445460 11.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 886788388 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2623578 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 430759220 28.84% 88.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173400494 11.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1489328778 # Type of FU issued -system.cpu.iq.rate 1.309005 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3131023 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002102 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4101702594 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1825725243 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1471768719 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17605097 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9240911 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8506597 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1483444207 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9015594 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 136711373 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1493571680 # Type of FU issued +system.cpu.iq.rate 1.757780 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2126958 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3820899737 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1736825318 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1473365597 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17873709 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9212850 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8524107 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1486479437 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9219201 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209970408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 67760525 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20730 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 356316 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 23332988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 54392189 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 142413 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 763229 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 19338739 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 46765 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 609 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 45345 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 32076957 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2310683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98308 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1723301655 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4186060 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 470273369 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 190181130 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3115724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 51873 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4910 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 356316 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5266619 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 459051 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5725670 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1483096593 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 420520679 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6232185 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 26540467 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2525220 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 145175 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1675654819 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4255922 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 456905033 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 186186881 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2976415 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59600 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9064 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 763229 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5291175 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 468114 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5759289 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1486215446 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 427697474 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7356234 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 102810963 # number of nop insts executed -system.cpu.iew.exec_refs 590732580 # number of memory reference insts executed -system.cpu.iew.exec_branches 90117242 # Number of branches executed -system.cpu.iew.exec_stores 170211901 # Number of stores executed -system.cpu.iew.exec_rate 1.303527 # Inst execution rate -system.cpu.iew.wb_sent 1481375672 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1480275316 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1168908244 # num instructions producing a value -system.cpu.iew.wb_consumers 1211941530 # num instructions consuming a value +system.cpu.iew.exec_nop 99535253 # number of nop insts executed +system.cpu.iew.exec_refs 599761085 # number of memory reference insts executed +system.cpu.iew.exec_branches 90544158 # Number of branches executed +system.cpu.iew.exec_stores 172063611 # Number of stores executed +system.cpu.iew.exec_rate 1.749123 # Inst execution rate +system.cpu.iew.wb_sent 1483627085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1481889704 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1175309728 # num instructions producing a value +system.cpu.iew.wb_consumers 1225337993 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.301047 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.964492 # average fanout of values written-back +system.cpu.iew.wb_rate 1.744032 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.959172 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 233686324 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 186029259 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5420176 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1105374719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.347528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786900 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5441892 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 822794393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.810323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.360899 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 387659384 35.07% 35.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 461508986 41.75% 76.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51139183 4.63% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 98630108 8.92% 90.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 32299027 2.92% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8730687 0.79% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 27864776 2.52% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10533124 0.95% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27009444 2.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 271095175 32.95% 32.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 302645797 36.78% 69.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 45322356 5.51% 75.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 68686908 8.35% 83.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22732084 2.76% 86.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9729610 1.18% 87.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 29628308 3.60% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10807412 1.31% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 62146743 7.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1105374719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 822794393 # Number of insts commited each cycle system.cpu.commit.count 1489523295 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed @@ -255,50 +256,50 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 27009444 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 62146743 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2801510024 # The number of ROB reads -system.cpu.rob.rob_writes 3478548339 # The number of ROB writes -system.cpu.timesIdled 10892 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 305571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2436135334 # The number of ROB reads +system.cpu.rob.rob_writes 3377694632 # The number of ROB writes +system.cpu.timesIdled 11301 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 357758 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.809443 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809443 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235417 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235417 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2001717837 # number of integer regfile reads -system.cpu.int_regfile_writes 1303407681 # number of integer regfile writes -system.cpu.fp_regfile_reads 16935756 # number of floating regfile reads -system.cpu.fp_regfile_writes 10440358 # number of floating regfile writes -system.cpu.misc_regfile_reads 596613763 # number of misc regfile reads +system.cpu.cpi 0.604503 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.604503 # CPI: Total CPI of All Threads +system.cpu.ipc 1.654251 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.654251 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2015965671 # number of integer regfile reads +system.cpu.int_regfile_writes 1304123959 # number of integer regfile writes +system.cpu.fp_regfile_reads 16988422 # number of floating regfile reads +system.cpu.fp_regfile_writes 10452078 # number of floating regfile writes +system.cpu.misc_regfile_reads 605607850 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes -system.cpu.icache.replacements 165 # number of replacements -system.cpu.icache.tagsinuse 1040.317886 # Cycle average of tags in use -system.cpu.icache.total_refs 176101137 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1300 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 135462.413077 # Average number of references to valid blocks. +system.cpu.icache.replacements 166 # number of replacements +system.cpu.icache.tagsinuse 1030.164560 # Cycle average of tags in use +system.cpu.icache.total_refs 171980565 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 132598.739399 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1040.317886 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.507968 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 176101137 # number of ReadReq hits -system.cpu.icache.demand_hits 176101137 # number of demand (read+write) hits -system.cpu.icache.overall_hits 176101137 # number of overall hits -system.cpu.icache.ReadReq_misses 1770 # number of ReadReq misses -system.cpu.icache.demand_misses 1770 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1770 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 61911500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 61911500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 61911500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 176102907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 176102907 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 176102907 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1030.164560 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.503010 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 171980565 # number of ReadReq hits +system.cpu.icache.demand_hits 171980565 # number of demand (read+write) hits +system.cpu.icache.overall_hits 171980565 # number of overall hits +system.cpu.icache.ReadReq_misses 1801 # number of ReadReq misses +system.cpu.icache.demand_misses 1801 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1801 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 62794000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 62794000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 62794000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 171982366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 171982366 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 171982366 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34978.248588 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34978.248588 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34978.248588 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34866.185453 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34866.185453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34866.185453 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,140 +309,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 469 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 469 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 469 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1301 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1301 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1301 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 503 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 503 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 503 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45277500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45277500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45277500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45168500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45168500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45168500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34802.075327 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34802.075327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34802.075327 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.536210 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475458 # number of replacements -system.cpu.dcache.tagsinuse 4095.400143 # Cycle average of tags in use -system.cpu.dcache.total_refs 447983825 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479554 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 934.167633 # Average number of references to valid blocks. +system.cpu.dcache.replacements 475459 # number of replacements +system.cpu.dcache.tagsinuse 4095.196777 # Cycle average of tags in use +system.cpu.dcache.total_refs 381789765 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 479555 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 796.133426 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.400143 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999854 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 282962670 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 165019836 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 4095.196777 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 216852847 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 164935599 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 447982506 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 447982506 # number of overall hits -system.cpu.dcache.ReadReq_misses 815560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1826980 # number of WriteReq misses +system.cpu.dcache.demand_hits 381788446 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 381788446 # number of overall hits +system.cpu.dcache.ReadReq_misses 816608 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1911217 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2642540 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2642540 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10724956500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 26607670410 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 37332626910 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 37332626910 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 283778230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 2727825 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2727825 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11966798000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 30001558232 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency 41968356232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 41968356232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 217669455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 450625046 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 450625046 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002874 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010950 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 384516271 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 384516271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011455 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.005864 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005864 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13150.419957 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 14563.744765 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14127.554137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14127.554137 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.007094 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.007094 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14654.274756 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15697.620015 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15385.281766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15385.281766 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2375 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2071.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 426814 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 603466 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1559527 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2162993 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2162993 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 212094 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 267453 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 426734 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 604334 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1643943 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2248277 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2248277 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 212274 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 267274 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 479547 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 479547 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 479548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 479548 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1622799000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3442234519 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5065033519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5065033519 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1589212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3626989841 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5216201841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5216201841 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000747 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001064 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001064 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7651.319698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12870.427772 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10562.121166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10562.121166 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001247 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001247 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7486.606933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13570.305533 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75848 # number of replacements -system.cpu.l2cache.tagsinuse 17699.311990 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464479 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.084108 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75834 # number of replacements +system.cpu.l2cache.tagsinuse 17835.857801 # Cycle average of tags in use +system.cpu.l2cache.total_refs 464745 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91356 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.087186 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1967.262312 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15732.049678 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.060036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.480104 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 179745 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 426814 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 207036 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 386781 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 386781 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33650 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60424 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94074 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94074 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1149817000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2071878000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3221695000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3221695000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 213395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 426814 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 267460 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 480855 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 480855 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157689 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.225918 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.195639 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.195639 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34169.895988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34288.991129 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34246.391139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34246.391139 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2067.900619 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15767.957182 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.063107 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.481200 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 179917 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 426734 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 206874 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 386791 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 386791 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33655 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60407 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 94062 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94062 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1145507000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2078924500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3224431500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3224431500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 213572 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 426734 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 267281 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 480853 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 480853 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157582 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.226006 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195615 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195615 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.755311 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34415.291274 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34279.852650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34279.852650 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,27 +451,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59264 # number of writebacks +system.cpu.l2cache.writebacks 59251 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33650 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60424 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94074 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94074 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33655 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60407 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044115000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1884920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2929035000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2929035000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1043470000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892046500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2935516500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2935516500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157689 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225918 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.195639 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.195639 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31028.677563 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31194.889448 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.435933 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.435933 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195615 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195615 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.902689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31321.643187 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 29b391479..244f95975 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index a4b9477d1..03608f531 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:01:24 -gem5 started Jul 15 2011 20:50:21 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 18 2011 15:15:16 +gem5 started Aug 18 2011 15:56:00 +gem5 executing on nadc-0330 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1062,4 +1064,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 749294021000 because target called exit() +Exiting @ tick 631043541000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 06ad1be7c..e79e605fc 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.749294 # Number of seconds simulated -sim_ticks 749294021000 # Number of ticks simulated +sim_seconds 0.631044 # Number of seconds simulated +sim_ticks 631043541000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60097 # Simulator instruction rate (inst/s) -host_tick_rate 27771108 # Simulator tick rate (ticks/s) -host_mem_usage 253640 # Number of bytes of host memory used -host_seconds 26981.06 # Real time elapsed on the host +host_inst_rate 115557 # Simulator instruction rate (inst/s) +host_tick_rate 44971725 # Simulator tick rate (ticks/s) +host_mem_usage 259448 # Number of bytes of host memory used +host_seconds 14032.01 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1498588043 # number of cpu cycles simulated +system.cpu.numCycles 1262087083 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 174353147 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 174353147 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 8954437 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 165220115 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 164182726 # Number of BTB hits +system.cpu.BPredUnit.lookups 172291796 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 172291796 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7138140 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 165694672 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 164669298 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 197081055 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1427085390 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174353147 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 164182726 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 405643185 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 122961003 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 787624963 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 296 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 184521623 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1125658 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1498287760 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.715646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.067557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187457062 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1372690648 # Number of instructions fetch has processed +system.cpu.fetch.Branches 172291796 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 164669298 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 395189805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 112734719 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 580214048 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 390 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 176517375 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1196842 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1261930799 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.983622 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216635 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1095772488 73.13% 73.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26898081 1.80% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18204566 1.22% 76.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17325497 1.16% 77.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23844032 1.59% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 17164690 1.15% 80.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40138916 2.68% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38301790 2.56% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220637700 14.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 869789775 68.93% 68.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26036678 2.06% 70.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 17623388 1.40% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17507853 1.39% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23833900 1.89% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16948501 1.34% 77.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37076715 2.94% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38063595 3.02% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215050394 17.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1498287760 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116345 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952287 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300082946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 691709075 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 302993844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 95563685 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 107938210 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2548886917 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 107938210 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 357219052 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 188499779 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 326836039 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 517791392 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2482037348 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3801 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 365556322 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 131873603 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2483397127 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6018409804 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6018402452 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7352 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1261930799 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136513 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.087635 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 280972137 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 498778976 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 296140618 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 86969632 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 99069436 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2448347491 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 99069436 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 329963846 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 111715541 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3471 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 317046121 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 404132384 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2409604498 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5352 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 248907784 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 129341699 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2413708682 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5838625893 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5838622529 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3364 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 865402477 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 169 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 866525950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 641640659 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 260570368 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 562700768 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 217406187 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2410485981 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 96 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1860645622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 297905 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 788955121 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1689446934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1498287760 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.241848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.192555 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 795714032 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 735209031 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 621902213 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 256079721 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 462456843 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 162376544 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2335230964 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1868917555 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 372085 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 713469187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1453396284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1261930799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.480998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.347284 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 431380009 28.79% 28.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 604501817 40.35% 69.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252266719 16.84% 85.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 123988851 8.28% 94.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 58817201 3.93% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20817096 1.39% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5535754 0.37% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 767498 0.05% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 212815 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 328585186 26.04% 26.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 421239585 33.38% 59.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 248611798 19.70% 79.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 160686589 12.73% 91.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 61778588 4.90% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 27094790 2.15% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12009524 0.95% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1648751 0.13% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 275988 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1498287760 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1261930799 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 150800 3.27% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3625649 78.65% 81.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 833140 18.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 173659 2.51% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6577211 95.02% 97.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 171078 2.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28076414 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1193303219 64.13% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 446918343 24.02% 89.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192347646 10.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26325646 1.41% 1.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1180659411 63.17% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 467364876 25.01% 89.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194567622 10.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1860645622 # Type of FU issued -system.cpu.iq.rate 1.241599 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4609589 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5224486461 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3205506305 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1835062624 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 37 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2036 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1837178777 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 118533940 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1868917555 # Type of FU issued +system.cpu.iq.rate 1.480815 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6921948 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003704 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5007059820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3055406588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1845403489 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1849513807 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 50 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 191278132 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 222598534 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4428 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6067505 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 72384311 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 202860088 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 64357 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6719705 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 67893664 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30883 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 674 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36961 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 107938210 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4267962 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121894 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2410486077 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 630348 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 641640659 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 260570368 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 96 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66625 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6067505 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4521579 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4614873 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 9136452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1840276566 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 443019520 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 20369056 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 99069436 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1201433 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 112801 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2335231055 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 659652 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 621902213 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 256079721 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57218 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6719705 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4534206 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2790969 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7325175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1852764474 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 461769012 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16153081 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 634826939 # number of memory reference insts executed -system.cpu.iew.exec_branches 111934330 # Number of branches executed -system.cpu.iew.exec_stores 191807419 # Number of stores executed -system.cpu.iew.exec_rate 1.228007 # Inst execution rate -system.cpu.iew.wb_sent 1838313315 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1835062636 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1427807499 # num instructions producing a value -system.cpu.iew.wb_consumers 2086812885 # num instructions consuming a value +system.cpu.iew.exec_refs 655479520 # number of memory reference insts executed +system.cpu.iew.exec_branches 112349751 # Number of branches executed +system.cpu.iew.exec_stores 193710508 # Number of stores executed +system.cpu.iew.exec_rate 1.468016 # Inst execution rate +system.cpu.iew.wb_sent 1850700108 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1845403509 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1443346270 # num instructions producing a value +system.cpu.iew.wb_consumers 2115960944 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.224528 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.684205 # average fanout of values written-back +system.cpu.iew.wb_rate 1.462184 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682123 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 789002361 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 713749948 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8954478 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1390349550 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.166249 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.425241 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7138191 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1162861363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.394400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.690304 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 517686759 37.23% 37.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 532094045 38.27% 75.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 126340876 9.09% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122997225 8.85% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 42691092 3.07% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23602651 1.70% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988906 0.36% 98.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10568517 0.76% 99.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 9379479 0.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 395572650 34.02% 34.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 431612406 37.12% 71.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 98230430 8.45% 79.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 129131818 11.10% 90.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30975376 2.66% 93.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25883779 2.23% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22467188 1.93% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 13999993 1.20% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14987723 1.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1390349550 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1162861363 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 9379479 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14987723 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791466414 # The number of ROB reads -system.cpu.rob.rob_writes 4929477020 # The number of ROB writes -system.cpu.timesIdled 44919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 300283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3483117570 # The number of ROB reads +system.cpu.rob.rob_writes 4770120987 # The number of ROB writes +system.cpu.timesIdled 44517 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 156284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.924202 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.924202 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082014 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082014 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3236351438 # number of integer regfile reads -system.cpu.int_regfile_writes 1827281055 # number of integer regfile writes -system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 926454727 # number of misc regfile reads -system.cpu.icache.replacements 14 # number of replacements -system.cpu.icache.tagsinuse 821.249711 # Cycle average of tags in use -system.cpu.icache.total_refs 184520340 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 203664.834437 # Average number of references to valid blocks. +system.cpu.cpi 0.778348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.778348 # CPI: Total CPI of All Threads +system.cpu.ipc 1.284772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.284772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3289423155 # number of integer regfile reads +system.cpu.int_regfile_writes 1840387955 # number of integer regfile writes +system.cpu.fp_regfile_reads 20 # number of floating regfile reads +system.cpu.misc_regfile_reads 943704220 # number of misc regfile reads +system.cpu.icache.replacements 12 # number of replacements +system.cpu.icache.tagsinuse 813.354682 # Cycle average of tags in use +system.cpu.icache.total_refs 176516095 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 197445.296421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 821.249711 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.401001 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 184520379 # number of ReadReq hits -system.cpu.icache.demand_hits 184520379 # number of demand (read+write) hits -system.cpu.icache.overall_hits 184520379 # number of overall hits -system.cpu.icache.ReadReq_misses 1244 # number of ReadReq misses -system.cpu.icache.demand_misses 1244 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43837000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43837000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43837000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 184521623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 184521623 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 184521623 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 813.354682 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.397146 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 176516138 # number of ReadReq hits +system.cpu.icache.demand_hits 176516138 # number of demand (read+write) hits +system.cpu.icache.overall_hits 176516138 # number of overall hits +system.cpu.icache.ReadReq_misses 1237 # number of ReadReq misses +system.cpu.icache.demand_misses 1237 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1237 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43406000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43406000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43406000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 176517375 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 176517375 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 176517375 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35238.745981 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35238.745981 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35238.745981 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35089.733226 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35089.733226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35089.733226 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,159 +306,167 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 908 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 339 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 339 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 898 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 898 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 898 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32023000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 31587000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 31587000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 31587000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35267.621145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35267.621145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35267.621145 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35174.832962 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459267 # number of replacements -system.cpu.dcache.tagsinuse 4095.145013 # Cycle average of tags in use -system.cpu.dcache.total_refs 511187603 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463363 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1103.211959 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459230 # number of replacements +system.cpu.dcache.tagsinuse 4094.984798 # Cycle average of tags in use +system.cpu.dcache.total_refs 457142531 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463326 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 986.654172 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 317737000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.145013 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 324252389 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186935214 # number of WriteReq hits -system.cpu.dcache.demand_hits 511187603 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 511187603 # number of overall hits -system.cpu.dcache.ReadReq_misses 216893 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1250843 # number of WriteReq misses -system.cpu.dcache.demand_misses 1467736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1467736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2202140000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24456528497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 26658668497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 26658668497 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 324469282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4094.984798 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999752 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 270249416 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186893112 # number of WriteReq hits +system.cpu.dcache.demand_hits 457142528 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 457142528 # number of overall hits +system.cpu.dcache.ReadReq_misses 217407 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1292945 # number of WriteReq misses +system.cpu.dcache.demand_misses 1510352 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1510352 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2208510500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25332209498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 27540719998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 27540719998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 270466823 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 512655339 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 512655339 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000668 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006647 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002863 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002863 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10153.116975 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19552.036904 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18163.122317 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18163.122317 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1683000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 471232500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 455 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29502 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3698.901099 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15972.900142 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses 458652880 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 458652880 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006871 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.003293 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003293 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10158.414862 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19592.642764 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18234.636693 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18234.636693 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1882500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 494592500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 34873 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3905.601660 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14182.677143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 410236 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3187 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1001186 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1004373 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1004373 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213706 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249657 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463363 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463363 # number of overall MSHR misses +system.cpu.dcache.writebacks 410188 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1043440 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1047022 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1047022 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213825 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249505 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463330 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463330 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1537618500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2504912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4042530500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4042530500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1535603000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2500577500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4036180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4036180500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001327 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7195.017922 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10033.413844 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8724.327363 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8724.327363 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000791 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.001010 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001010 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7181.587747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10022.153865 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73626 # number of replacements -system.cpu.l2cache.tagsinuse 18020.121122 # Cycle average of tags in use -system.cpu.l2cache.total_refs 453087 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89234 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.077515 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73611 # number of replacements +system.cpu.l2cache.tagsinuse 18032.065292 # Cycle average of tags in use +system.cpu.l2cache.total_refs 453266 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89232 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.079635 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1915.061823 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16105.059300 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058443 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491487 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181487 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 410236 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190884 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372371 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372371 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33119 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58779 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91898 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91898 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130363000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2022275000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3152638000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3152638000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214606 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 410236 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249663 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464269 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464269 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154325 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235433 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197941 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197941 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34130.348139 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.719373 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34305.839082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34305.839082 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 116500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1960.203068 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16071.862223 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.059821 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.490474 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181561 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410188 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 190780 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372341 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372341 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33157 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 58724 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91881 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91881 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130411500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2017247500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3147659000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3147659000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214718 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410188 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249504 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464222 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464222 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154421 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235363 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197925 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197925 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34092.695358 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34351.329950 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34257.996757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34257.996757 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 204000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 95 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 121 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1226.315789 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1685.950413 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58523 # number of writebacks +system.cpu.l2cache.writebacks 58498 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33119 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58779 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91898 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91898 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33157 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58724 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91881 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91881 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1026905500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1830910000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2857815500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2857815500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1028041500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829105500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2857147000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2857147000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154325 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235433 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197941 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197941 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.537033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.049831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31097.689830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31097.689830 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235363 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197925 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197925 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.262840 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31147.495062 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index ce4b09a6a..f372f8ce3 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -130,6 +130,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu0.tracer trapLatency=13 @@ -565,6 +566,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu1.tracer trapLatency=13 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index e8efa0522..72ae91dc7 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 15 2011 20:24:21 -gem5 started Aug 15 2011 20:25:29 -gem5 executing on nadc-0270 +gem5 compiled Aug 17 2011 16:33:41 +gem5 started Aug 17 2011 16:35:58 +gem5 executing on nadc-0388 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 98887000 -Exiting @ tick 1899411597500 because m5_exit instruction encountered +Exiting @ tick 1897470973500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 2eeafd392..d4f86dcbd 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.899412 # Number of seconds simulated -sim_ticks 1899411597500 # Number of ticks simulated +sim_seconds 1.897471 # Number of seconds simulated +sim_ticks 1897470973500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123946 # Simulator instruction rate (inst/s) -host_tick_rate 4137994790 # Simulator tick rate (ticks/s) -host_mem_usage 343492 # Number of bytes of host memory used -host_seconds 459.02 # Real time elapsed on the host -sim_insts 56893410 # Number of instructions simulated -system.l2c.replacements 397094 # number of replacements -system.l2c.tagsinuse 35529.229053 # Cycle average of tags in use -system.l2c.total_refs 2438232 # Total number of references to valid blocks. -system.l2c.sampled_refs 432488 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.637687 # Average number of references to valid blocks. +host_inst_rate 112670 # Simulator instruction rate (inst/s) +host_tick_rate 3808310962 # Simulator tick rate (ticks/s) +host_mem_usage 344004 # Number of bytes of host memory used +host_seconds 498.24 # Real time elapsed on the host +sim_insts 56137023 # Number of instructions simulated +system.l2c.replacements 397425 # number of replacements +system.l2c.tagsinuse 35089.523512 # Cycle average of tags in use +system.l2c.total_refs 2483901 # Total number of references to valid blocks. +system.l2c.sampled_refs 433413 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.731026 # Average number of references to valid blocks. system.l2c.warmup_cycle 9244135000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10221.529700 # Average occupied blocks per context -system.l2c.occ_blocks::1 2327.457536 # Average occupied blocks per context -system.l2c.occ_blocks::2 22980.241816 # Average occupied blocks per context -system.l2c.occ_percent::0 0.155968 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.035514 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.350651 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1442413 # number of ReadReq hits -system.l2c.ReadReq_hits::1 407625 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1850038 # number of ReadReq hits -system.l2c.Writeback_hits::0 800001 # number of Writeback hits -system.l2c.Writeback_hits::total 800001 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 188 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 259 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 148509 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 19811 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168320 # number of ReadExReq hits -system.l2c.demand_hits::0 1590922 # number of demand (read+write) hits -system.l2c.demand_hits::1 427436 # number of demand (read+write) hits +system.l2c.occ_blocks::0 11999.654790 # Average occupied blocks per context +system.l2c.occ_blocks::1 233.124353 # Average occupied blocks per context +system.l2c.occ_blocks::2 22856.744369 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183100 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003557 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.348766 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1722706 # number of ReadReq hits +system.l2c.ReadReq_hits::1 146059 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1868765 # number of ReadReq hits +system.l2c.Writeback_hits::0 827102 # number of Writeback hits +system.l2c.Writeback_hits::total 827102 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 179 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 226 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 26 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 168351 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 11011 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179362 # number of ReadExReq hits +system.l2c.demand_hits::0 1891057 # number of demand (read+write) hits +system.l2c.demand_hits::1 157070 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2018358 # number of demand (read+write) hits -system.l2c.overall_hits::0 1590922 # number of overall hits -system.l2c.overall_hits::1 427436 # number of overall hits +system.l2c.demand_hits::total 2048127 # number of demand (read+write) hits +system.l2c.overall_hits::0 1891057 # number of overall hits +system.l2c.overall_hits::1 157070 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2018358 # number of overall hits -system.l2c.ReadReq_misses::0 301840 # number of ReadReq misses -system.l2c.ReadReq_misses::1 7227 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309067 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3348 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 792 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4140 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 439 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 492 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 931 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 106737 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 17826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124563 # number of ReadExReq misses -system.l2c.demand_misses::0 408577 # number of demand (read+write) misses -system.l2c.demand_misses::1 25053 # number of demand (read+write) misses +system.l2c.overall_hits::total 2048127 # number of overall hits +system.l2c.ReadReq_misses::0 305325 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4048 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309373 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2451 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3007 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 48 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 82 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 130 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 113992 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 10735 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124727 # number of ReadExReq misses +system.l2c.demand_misses::0 419317 # number of demand (read+write) misses +system.l2c.demand_misses::1 14783 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 433630 # number of demand (read+write) misses -system.l2c.overall_misses::0 408577 # number of overall misses -system.l2c.overall_misses::1 25053 # number of overall misses +system.l2c.demand_misses::total 434100 # number of demand (read+write) misses +system.l2c.overall_misses::0 419317 # number of overall misses +system.l2c.overall_misses::1 14783 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 433630 # number of overall misses -system.l2c.ReadReq_miss_latency 16078822000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 5852000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 5401500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6533699500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22612521500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22612521500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1744253 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 414852 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2159105 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 800001 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 800001 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3536 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 863 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4399 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 474 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 527 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1001 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 255246 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 37637 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292883 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1999499 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 452489 # number of demand (read+write) accesses +system.l2c.overall_misses::total 434100 # number of overall misses +system.l2c.ReadReq_miss_latency 16104881500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 3975000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 681000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6543645500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22648527000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22648527000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2028031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 150107 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2178138 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 827102 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 827102 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2630 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 603 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3233 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 183 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 282343 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21746 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304089 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2310374 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 171853 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2451988 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1999499 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 452489 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2482227 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2310374 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 171853 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2451988 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.173048 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.017421 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.946833 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.917729 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.926160 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.933586 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.418173 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.473630 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.204340 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.055367 # miss rate for demand accesses +system.l2c.overall_accesses::total 2482227 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.150552 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026967 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.931939 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.922056 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.648649 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.752294 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.403736 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.493654 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.181493 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.086021 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.204340 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.055367 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.181493 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.086021 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 53269.354625 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2224826.622388 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52746.684680 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3978478.631423 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1747.909200 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7388.888889 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1621.787026 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7149.280576 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 12304.100228 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 10978.658537 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 14187.500000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 8304.878049 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 61213.070444 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 366526.394031 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57404.427504 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 609561.760596 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 55344.577644 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 902587.374765 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54012.899549 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1532065.683555 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 55344.577644 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 902587.374765 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54012.899549 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1532065.683555 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -138,70 +138,70 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122463 # number of writebacks +system.l2c.writebacks 122219 # number of writebacks system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309050 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 4140 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 931 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124563 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 433613 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 433613 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 309356 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 130 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124727 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434083 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434083 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12366985500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 165615000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 37241500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5018687000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17385672500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17385672500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838004500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1515144998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2353149498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.177182 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.744964 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12384389500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 120345500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 5200000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5026892500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17411282000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17411282000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838237000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1420706998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2258943998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.152540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.060903 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.170814 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.797219 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.143346 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.986733 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.964135 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.766603 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.756757 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.192661 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.488012 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 3.309589 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.441757 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 5.735630 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.216861 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.958284 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.187884 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 2.525897 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.216861 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.958284 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.187884 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 2.525897 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40016.131694 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.623188 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.611171 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40290.351067 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40094.906057 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40094.906057 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40032.808480 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.782507 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40303.162106 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41701 # number of replacements -system.iocache.tagsinuse 0.379564 # Cycle average of tags in use +system.iocache.replacements 41699 # number of replacements +system.iocache.tagsinuse 0.463134 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708346603000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.379564 # Average occupied blocks per context -system.iocache.occ_percent::1 0.023723 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709323096000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.463134 # Average occupied blocks per context +system.iocache.occ_percent::1 0.028946 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -218,10 +218,10 @@ system.iocache.demand_misses::total 41731 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency 20618998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5720800806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741419804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741419804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 20616998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5721081806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741698804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741698804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -241,26 +241,26 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115189.932961 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115178.759777 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137678.109501 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137684.872112 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137581.649230 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137588.334907 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137581.649230 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137588.334907 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64641068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64637068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6181.607344 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6180.633773 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41522 # number of writebacks +system.iocache.writebacks 41520 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses @@ -268,10 +268,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11310998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3559941996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571252994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571252994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11308998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560223994 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571532992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571532992 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63189.932961 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85674.383808 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85577.939517 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85577.939517 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63178.759777 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85681.170437 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8691348 # DTB read hits -system.cpu0.dtb.read_misses 30841 # DTB read misses -system.cpu0.dtb.read_acv 585 # DTB read access violations -system.cpu0.dtb.read_accesses 626526 # DTB read accesses -system.cpu0.dtb.write_hits 5727483 # DTB write hits -system.cpu0.dtb.write_misses 5665 # DTB write misses -system.cpu0.dtb.write_acv 282 # DTB write access violations -system.cpu0.dtb.write_accesses 212486 # DTB write accesses -system.cpu0.dtb.data_hits 14418831 # DTB hits -system.cpu0.dtb.data_misses 36506 # DTB misses -system.cpu0.dtb.data_acv 867 # DTB access violations -system.cpu0.dtb.data_accesses 839012 # DTB accesses -system.cpu0.itb.fetch_hits 1018007 # ITB hits -system.cpu0.itb.fetch_misses 28254 # ITB misses -system.cpu0.itb.fetch_acv 951 # ITB acv -system.cpu0.itb.fetch_accesses 1046261 # ITB accesses +system.cpu0.dtb.read_hits 9537119 # DTB read hits +system.cpu0.dtb.read_misses 35694 # DTB read misses +system.cpu0.dtb.read_acv 589 # DTB read access violations +system.cpu0.dtb.read_accesses 644456 # DTB read accesses +system.cpu0.dtb.write_hits 6201700 # DTB write hits +system.cpu0.dtb.write_misses 7404 # DTB write misses +system.cpu0.dtb.write_acv 340 # DTB write access violations +system.cpu0.dtb.write_accesses 219479 # DTB write accesses +system.cpu0.dtb.data_hits 15738819 # DTB hits +system.cpu0.dtb.data_misses 43098 # DTB misses +system.cpu0.dtb.data_acv 929 # DTB access violations +system.cpu0.dtb.data_accesses 863935 # DTB accesses +system.cpu0.itb.fetch_hits 1065001 # ITB hits +system.cpu0.itb.fetch_misses 28395 # ITB misses +system.cpu0.itb.fetch_acv 959 # ITB acv +system.cpu0.itb.fetch_accesses 1093396 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -337,275 +337,275 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103036446 # number of cpu cycles simulated +system.cpu0.numCycles 112251413 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12345310 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10395868 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 412413 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 11143165 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5756291 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13715156 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11502951 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 484161 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 12377728 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 6363664 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 808447 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 32944 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 25643568 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63130050 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12345310 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6564738 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12229123 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1931790 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 31463202 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 192852 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 226876 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7797411 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 265802 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 71034720 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.888721 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.206546 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 918279 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37972 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28099564 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69844028 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13715156 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 7281943 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 13538078 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2172072 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34812736 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 193219 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 330912 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 98 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8567969 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 303515 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 78411579 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.890736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.207630 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 58805597 82.78% 82.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 896633 1.26% 84.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1683822 2.37% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 790380 1.11% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2590451 3.65% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578678 0.81% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 651939 0.92% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 969955 1.37% 94.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4067265 5.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64873501 82.73% 82.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 956509 1.22% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1906420 2.43% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 900643 1.15% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2836490 3.62% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 653196 0.83% 91.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 748865 0.96% 92.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1020020 1.30% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4515935 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 71034720 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.119815 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.612696 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26620678 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 31169441 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11195503 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 833782 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1215315 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 497181 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32875 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61799188 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 97991 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1215315 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27633845 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 10392034 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17602675 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10482679 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3708170 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58338786 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6838 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 387997 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1347242 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39031988 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 70900966 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 70475489 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 425477 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33170605 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5861375 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1485068 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 227968 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10243220 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9180149 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6097470 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1603652 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1903642 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51204618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1864754 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49739725 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 70469 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6805118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3728302 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1267762 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 71034720 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.700217 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.322322 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 78411579 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.122182 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.622211 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29218734 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34518564 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12397503 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 907653 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1369124 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 565623 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 38130 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 68326357 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 115471 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1369124 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30359966 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12420002 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18653448 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11559609 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4049428 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64489639 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6675 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 459269 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1452522 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 43185187 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 78281955 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77849999 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 431956 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36504578 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6680601 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1578071 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238750 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11394232 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10044360 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6546770 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1193752 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 777018 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56531127 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2009866 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 55005856 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 111558 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7605242 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3895552 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1371310 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 78411579 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.701502 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.348295 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 48628565 68.46% 68.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10107628 14.23% 82.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4889823 6.88% 89.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3044033 4.29% 93.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2225901 3.13% 96.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1246231 1.75% 98.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 700109 0.99% 99.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 154501 0.22% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 37929 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54224531 69.15% 69.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10651966 13.58% 82.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5211873 6.65% 89.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3322855 4.24% 93.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2518388 3.21% 96.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1465679 1.87% 98.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 653633 0.83% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263398 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 99256 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 71034720 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 78411579 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 52156 10.93% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 267781 56.13% 67.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 157153 32.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 63058 8.97% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 343865 48.92% 57.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 295935 42.10% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 33971995 68.30% 68.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 53580 0.11% 68.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15560 0.03% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.45% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9077168 18.25% 86.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5791424 11.64% 98.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 825016 1.66% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37799296 68.72% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60344 0.11% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9967542 18.12% 86.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6280275 11.42% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 877731 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49739725 # Type of FU issued -system.cpu0.iq.rate 0.482739 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 477090 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.009592 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 170451707 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59601257 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48417922 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 610021 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 293075 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 290010 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 49893944 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 319543 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 495668 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 55005856 # Type of FU issued +system.cpu0.iq.rate 0.490024 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 702858 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012778 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 188615716 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65871549 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53572345 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 621990 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 297473 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294666 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55378554 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326832 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 547956 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1332465 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15476 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20341 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 527918 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1439562 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 14656 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 23453 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 541104 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 14091 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 218656 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 167543 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1215315 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6999311 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 544202 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 56199276 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 754553 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9180149 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6097470 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1645846 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 470730 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6896 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20341 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291584 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 326384 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 617968 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49204821 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8748371 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 534903 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1369124 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8683441 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 605421 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 62052001 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 831027 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10044360 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6546770 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1774362 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 483184 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10442 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 23453 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 350905 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 357470 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 708375 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54360123 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9599991 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 645732 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3129904 # number of nop insts executed -system.cpu0.iew.exec_refs 14495988 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7765506 # Number of branches executed -system.cpu0.iew.exec_stores 5747617 # Number of stores executed -system.cpu0.iew.exec_rate 0.477548 # Inst execution rate -system.cpu0.iew.wb_sent 48811342 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48707932 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23956930 # num instructions producing a value -system.cpu0.iew.wb_consumers 32092147 # num instructions consuming a value +system.cpu0.iew.exec_nop 3511008 # number of nop insts executed +system.cpu0.iew.exec_refs 15823517 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8665836 # Number of branches executed +system.cpu0.iew.exec_stores 6223526 # Number of stores executed +system.cpu0.iew.exec_rate 0.484271 # Inst execution rate +system.cpu0.iew.wb_sent 53987864 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53867011 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26614200 # num instructions producing a value +system.cpu0.iew.wb_consumers 35806994 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.472725 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.746504 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.479878 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743268 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 48759720 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 7342909 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 596992 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 565842 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 69819405 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.698369 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.595257 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53695815 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 8260876 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638556 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 645745 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77042455 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.696964 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608185 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 51124042 73.22% 73.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8032267 11.50% 84.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4140271 5.93% 90.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2329968 3.34% 93.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1273302 1.82% 95.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 518646 0.74% 96.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 361032 0.52% 97.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 714639 1.02% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1325238 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56792844 73.72% 73.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8505609 11.04% 84.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4528626 5.88% 90.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2490278 3.23% 93.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1477167 1.92% 95.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 617055 0.80% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 444256 0.58% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 490319 0.64% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1696301 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 69819405 # Number of insts commited each cycle -system.cpu0.commit.count 48759720 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 77042455 # Number of insts commited each cycle +system.cpu0.commit.count 53695815 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13417236 # Number of memory references committed -system.cpu0.commit.loads 7847684 # Number of loads committed -system.cpu0.commit.membars 202015 # Number of memory barriers committed -system.cpu0.commit.branches 7296729 # Number of branches committed -system.cpu0.commit.fp_insts 287598 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45136958 # Number of committed integer instructions. -system.cpu0.commit.function_calls 626830 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1325238 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14610464 # Number of memory references committed +system.cpu0.commit.loads 8604798 # Number of loads committed +system.cpu0.commit.membars 217772 # Number of memory barriers committed +system.cpu0.commit.branches 8097271 # Number of branches committed +system.cpu0.commit.fp_insts 292136 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49674100 # Number of committed integer instructions. +system.cpu0.commit.function_calls 705369 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1696301 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124403287 # The number of ROB reads -system.cpu0.rob.rob_writes 113421475 # The number of ROB writes -system.cpu0.timesIdled 1076474 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32001726 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 45967748 # Number of Instructions Simulated -system.cpu0.committedInsts_total 45967748 # Number of Instructions Simulated -system.cpu0.cpi 2.241494 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.241494 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.446131 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.446131 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 64511715 # number of integer regfile reads -system.cpu0.int_regfile_writes 35217125 # number of integer regfile writes -system.cpu0.fp_regfile_reads 141815 # number of floating regfile reads -system.cpu0.fp_regfile_writes 144143 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1768684 # number of misc regfile reads -system.cpu0.misc_regfile_writes 843519 # number of misc regfile writes +system.cpu0.rob.rob_reads 137112360 # The number of ROB reads +system.cpu0.rob.rob_writes 125284104 # The number of ROB writes +system.cpu0.timesIdled 1232970 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33839834 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 50579161 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50579161 # Number of Instructions Simulated +system.cpu0.cpi 2.219321 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.219321 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.450588 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.450588 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71273377 # number of integer regfile reads +system.cpu0.int_regfile_writes 38974201 # number of integer regfile writes +system.cpu0.fp_regfile_reads 144005 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146400 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1864820 # number of misc regfile reads +system.cpu0.misc_regfile_writes 888952 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -637,233 +637,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 880531 # number of replacements -system.cpu0.icache.tagsinuse 509.999835 # Cycle average of tags in use -system.cpu0.icache.total_refs 6871052 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 881041 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.798788 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23352841000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 509.999835 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996093 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 6871052 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6871052 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 6871052 # number of demand (read+write) hits +system.cpu0.icache.replacements 972255 # number of replacements +system.cpu0.icache.tagsinuse 509.997473 # Cycle average of tags in use +system.cpu0.icache.total_refs 7540990 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 972767 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.752103 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23351428000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 509.997473 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996089 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 7540990 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7540990 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7540990 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6871052 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 6871052 # number of overall hits +system.cpu0.icache.demand_hits::total 7540990 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7540990 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6871052 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 926359 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 926359 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 926359 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7540990 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 1026979 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1026979 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 1026979 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 926359 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 926359 # number of overall misses +system.cpu0.icache.demand_misses::total 1026979 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 1026979 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 926359 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 13849490998 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 13849490998 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 13849490998 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 7797411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7797411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 7797411 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 1026979 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 15345865496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 15345865496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 15345865496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 8567969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8567969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 8567969 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7797411 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 7797411 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 8567969 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 8567969 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7797411 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.118803 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.118803 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 8567969 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.119863 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.119863 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.118803 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.119863 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14950.457650 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14942.725699 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14950.457650 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14942.725699 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14950.457650 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14942.725699 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1091498 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1169997 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 105 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 10395.219048 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11584.128713 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 208 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 45158 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 45158 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 45158 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 881201 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 881201 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 881201 # number of overall MSHR misses +system.cpu0.icache.writebacks 201 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 54044 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 54044 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 54044 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 972935 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 972935 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 972935 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10516036498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 10516036498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 10516036498 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 11633224497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 11633224497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 11633224497 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113012 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113555 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.113012 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.113555 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.113012 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.113555 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11933.754612 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11933.754612 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11933.754612 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11956.836271 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1121199 # number of replacements -system.cpu0.dcache.tagsinuse 488.854716 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10572300 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1121711 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.425155 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1341445 # number of replacements +system.cpu0.dcache.tagsinuse 503.508011 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11371142 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1341956 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.473558 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 489.854716 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 504.508011 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.956747 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::0 0.985367 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 6494021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6494021 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 3693282 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3693282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 174657 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174657 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 196468 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 196468 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 10187303 # number of demand (read+write) hits +system.cpu0.dcache.ReadReq_hits::0 7002154 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7002154 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 3971242 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3971242 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 182799 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 182799 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 208802 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208802 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 10973396 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10187303 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 10187303 # number of overall hits +system.cpu0.dcache.demand_hits::total 10973396 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 10973396 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10187303 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1375687 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1375687 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1662707 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1662707 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 20152 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20152 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 3348 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3348 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 3038394 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 10973396 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1698188 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1698188 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1810110 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1810110 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 21696 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21696 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 665 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 665 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 3508298 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3038394 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3038394 # number of overall misses +system.cpu0.dcache.demand_misses::total 3508298 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 3508298 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3038394 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 31827617500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 51165322075 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 294994000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 41962000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 82992939575 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 82992939575 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 7869708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7869708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5355989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5355989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 194809 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194809 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 199816 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199816 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 13225697 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 3508298 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 37024597500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 55205693695 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 326548500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 6352500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 92230291195 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 92230291195 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8700342 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8700342 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 5781352 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5781352 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 204495 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 204495 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 209467 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209467 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14481694 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13225697 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 13225697 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14481694 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14481694 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13225697 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.174808 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.310439 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.103445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.016755 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.229734 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14481694 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.195186 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.313095 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106096 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003175 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.242257 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.229734 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.242257 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23135.798695 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 21802.413808 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30772.302080 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30498.529755 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14638.447797 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15051.092367 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12533.452808 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9552.631579 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 27314.739160 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 26289.183871 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 27314.739160 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 26289.183871 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 855518470 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 221500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 97807 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8747.006554 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 22150 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 889959290 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 98831 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9004.859710 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 602926 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 516336 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1401114 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4413 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1917450 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1917450 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 859351 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 261593 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 15739 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 3348 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1120944 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1120944 # number of overall MSHR misses +system.cpu0.dcache.writebacks 791115 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 651520 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1525368 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4914 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 2176888 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 2176888 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 1046668 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 284742 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16782 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 665 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1331410 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1331410 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 21884756500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 7717990970 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 167906500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 31911000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 29602747470 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 29602747470 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 634931500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1090823998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 1725755498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109197 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 24224955000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 8301968289 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194959000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4349000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 32526923289 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 32526923289 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 917419500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1254211998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2171631498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120302 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.048841 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049252 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.080792 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082066 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.016755 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003175 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.084755 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.091937 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.084755 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.091937 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 25466.609686 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29503.813061 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10668.180952 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 9531.362007 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 26408.765710 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 26408.765710 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23144.831981 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29156.107244 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11617.149327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6539.849624 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -874,22 +874,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2335038 # DTB read hits -system.cpu1.dtb.read_misses 11141 # DTB read misses -system.cpu1.dtb.read_acv 15 # DTB read access violations -system.cpu1.dtb.read_accesses 329726 # DTB read accesses -system.cpu1.dtb.write_hits 1301059 # DTB write hits -system.cpu1.dtb.write_misses 3075 # DTB write misses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_accesses 125932 # DTB write accesses -system.cpu1.dtb.data_hits 3636097 # DTB hits -system.cpu1.dtb.data_misses 14216 # DTB misses -system.cpu1.dtb.data_acv 78 # DTB access violations -system.cpu1.dtb.data_accesses 455658 # DTB accesses -system.cpu1.itb.fetch_hits 423788 # ITB hits -system.cpu1.itb.fetch_misses 7837 # ITB misses -system.cpu1.itb.fetch_acv 166 # ITB acv -system.cpu1.itb.fetch_accesses 431625 # ITB accesses +system.cpu1.dtb.read_hits 1324275 # DTB read hits +system.cpu1.dtb.read_misses 10298 # DTB read misses +system.cpu1.dtb.read_acv 4 # DTB read access violations +system.cpu1.dtb.read_accesses 333543 # DTB read accesses +system.cpu1.dtb.write_hits 770562 # DTB write hits +system.cpu1.dtb.write_misses 3363 # DTB write misses +system.cpu1.dtb.write_acv 49 # DTB write access violations +system.cpu1.dtb.write_accesses 128416 # DTB write accesses +system.cpu1.dtb.data_hits 2094837 # DTB hits +system.cpu1.dtb.data_misses 13661 # DTB misses +system.cpu1.dtb.data_acv 53 # DTB access violations +system.cpu1.dtb.data_accesses 461959 # DTB accesses +system.cpu1.itb.fetch_hits 370005 # ITB hits +system.cpu1.itb.fetch_misses 7545 # ITB misses +system.cpu1.itb.fetch_acv 134 # ITB acv +system.cpu1.itb.fetch_accesses 377550 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -902,500 +902,500 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 20152954 # number of cpu cycles simulated +system.cpu1.numCycles 9912659 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3242658 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2662310 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 131441 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 2892914 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1375784 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1745252 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1443345 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 65834 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1584413 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 702878 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 235158 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 7774 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 6188689 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 16200802 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3242658 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1610942 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3090469 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 613653 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 7714239 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65046 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 159598 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1940544 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 74817 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 17655267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.917619 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.257026 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 119333 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5152 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3326193 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8368967 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1745252 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 822211 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1597560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 342353 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3930227 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65364 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47873 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1048710 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 37506 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9217508 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.907942 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.250031 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14564798 82.50% 82.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 197815 1.12% 83.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 462974 2.62% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 255072 1.44% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 513820 2.91% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 162072 0.92% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 211046 1.20% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 121453 0.69% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1166217 6.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7619948 82.67% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 115536 1.25% 83.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 231432 2.51% 86.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 132066 1.43% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 251396 2.73% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 87805 0.95% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 105965 1.15% 92.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 72910 0.79% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 600450 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 17655267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.160902 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.803892 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6415483 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7821687 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2861971 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 154408 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 401717 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 149324 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8351 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 15726471 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21041 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 401717 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6681295 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2118018 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4943945 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2656010 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 854280 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 14736815 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 186 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 221815 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 138242 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 9911157 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 18088761 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 17988130 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 100631 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7897558 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2013599 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 424269 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 36275 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2592161 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2485755 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1426985 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 360752 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 285996 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12852454 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 484885 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 12271073 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 26221 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2300844 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1315458 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356394 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 17655267 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.695038 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.354056 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9217508 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.176063 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.844271 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3400940 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4036286 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1484850 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 73785 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 221646 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 74292 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4556 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8102747 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13778 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 221646 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3537754 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 421646 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3194279 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1408453 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 433728 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7527296 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 45933 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 92379 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5035349 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9221754 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9169185 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52569 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3992895 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1042454 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 304748 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22314 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1288706 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1415531 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 837109 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 144169 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 91214 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6583258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 323533 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6259296 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22632 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1284449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 724409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 248666 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9217508 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.679066 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.329101 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12407145 70.27% 70.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2235941 12.66% 82.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1035355 5.86% 88.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 796484 4.51% 93.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 626149 3.55% 96.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 333560 1.89% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 156466 0.89% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 49558 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 14609 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 6458729 70.07% 70.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1222372 13.26% 83.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 577704 6.27% 89.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 392327 4.26% 93.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 292985 3.18% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 159359 1.73% 98.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 73107 0.79% 99.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 30242 0.33% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10683 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 17655267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9217508 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 13105 7.34% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 95150 53.29% 60.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 70292 39.37% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2814 1.95% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 81545 56.44% 58.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60126 41.61% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 8216703 66.96% 66.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 19600 0.16% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11030 0.09% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.02% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2431476 19.81% 87.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1328460 10.83% 97.90% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 257837 2.10% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3976 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3873185 61.88% 61.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10062 0.16% 62.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10067 0.16% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1379075 22.03% 84.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 790293 12.63% 96.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 190650 3.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 12271073 # Type of FU issued -system.cpu1.iq.rate 0.608897 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 178547 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014550 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 42255695 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15570864 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11866318 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 146486 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 71642 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 70264 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12369614 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 76027 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 105474 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6259296 # Type of FU issued +system.cpu1.iq.rate 0.631445 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 144485 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023083 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 21824812 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8155075 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6057514 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 78405 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 38858 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37639 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6359227 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40578 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 60856 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 463598 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 9284 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4789 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 195743 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 266775 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6711 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3171 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 114531 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5212 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 50812 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 348 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 21986 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 401717 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1622444 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 62821 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 14027082 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 177744 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2485755 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1426985 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 441055 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 11459 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3097 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4789 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 106850 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 88794 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 195644 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 12103351 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2352431 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 167722 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 221646 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 305727 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 11882 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7168806 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98535 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1415531 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 837109 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 301857 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4025 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4971 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3171 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 47886 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 59778 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 107664 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6180810 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1338159 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 78486 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 689743 # number of nop insts executed -system.cpu1.iew.exec_refs 3661778 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1907962 # Number of branches executed -system.cpu1.iew.exec_stores 1309347 # Number of stores executed -system.cpu1.iew.exec_rate 0.600575 # Inst execution rate -system.cpu1.iew.wb_sent 11974198 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11936582 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5946561 # num instructions producing a value -system.cpu1.iew.wb_consumers 8293064 # num instructions consuming a value +system.cpu1.iew.exec_nop 262015 # number of nop insts executed +system.cpu1.iew.exec_refs 2115427 # number of memory reference insts executed +system.cpu1.iew.exec_branches 905329 # Number of branches executed +system.cpu1.iew.exec_stores 777268 # Number of stores executed +system.cpu1.iew.exec_rate 0.623527 # Inst execution rate +system.cpu1.iew.wb_sent 6122723 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6095153 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2947422 # num instructions producing a value +system.cpu1.iew.wb_consumers 4027218 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.592299 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.717052 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614886 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.731875 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 11515527 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 2436187 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 128491 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 177413 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 17253550 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.667429 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.563448 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5779093 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1316908 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 74867 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 99712 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 8995862 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642417 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.546372 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12827961 74.35% 74.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1952306 11.32% 85.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 928648 5.38% 91.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 493505 2.86% 93.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 338427 1.96% 95.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 153865 0.89% 96.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 124614 0.72% 97.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119099 0.69% 98.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 315125 1.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6736606 74.89% 74.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1094915 12.17% 87.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 391523 4.35% 91.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 242834 2.70% 94.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 155077 1.72% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 75617 0.84% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76298 0.85% 97.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 67487 0.75% 98.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 155505 1.73% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 17253550 # Number of insts commited each cycle -system.cpu1.commit.count 11515527 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 8995862 # Number of insts commited each cycle +system.cpu1.commit.count 5779093 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3253399 # Number of memory references committed -system.cpu1.commit.loads 2022157 # Number of loads committed -system.cpu1.commit.membars 41280 # Number of memory barriers committed -system.cpu1.commit.branches 1729331 # Number of branches committed -system.cpu1.commit.fp_insts 68665 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 10682634 # Number of committed integer instructions. -system.cpu1.commit.function_calls 174972 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 315125 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1871334 # Number of memory references committed +system.cpu1.commit.loads 1148756 # Number of loads committed +system.cpu1.commit.membars 20308 # Number of memory barriers committed +system.cpu1.commit.branches 819762 # Number of branches committed +system.cpu1.commit.fp_insts 36255 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5407958 # Number of committed integer instructions. +system.cpu1.commit.function_calls 88494 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 155505 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 30796624 # The number of ROB reads -system.cpu1.rob.rob_writes 28304513 # The number of ROB writes -system.cpu1.timesIdled 230784 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2497687 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 10925662 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10925662 # Number of Instructions Simulated -system.cpu1.cpi 1.844552 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.844552 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.542137 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.542137 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 15857410 # number of integer regfile reads -system.cpu1.int_regfile_writes 8648406 # number of integer regfile writes -system.cpu1.fp_regfile_reads 40377 # number of floating regfile reads -system.cpu1.fp_regfile_writes 39511 # number of floating regfile writes -system.cpu1.misc_regfile_reads 441161 # number of misc regfile reads -system.cpu1.misc_regfile_writes 195544 # number of misc regfile writes -system.cpu1.icache.replacements 205961 # number of replacements -system.cpu1.icache.tagsinuse 502.866762 # Cycle average of tags in use -system.cpu1.icache.total_refs 1723284 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 206473 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.346292 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1708291874000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 502.866762 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.982162 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 1723284 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1723284 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 1723284 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 15845699 # The number of ROB reads +system.cpu1.rob.rob_writes 14412433 # The number of ROB writes +system.cpu1.timesIdled 81222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 695151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 5557862 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5557862 # Number of Instructions Simulated +system.cpu1.cpi 1.783538 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.783538 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.560683 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.560683 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8056762 # number of integer regfile reads +system.cpu1.int_regfile_writes 4390923 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24497 # number of floating regfile reads +system.cpu1.fp_regfile_writes 23023 # number of floating regfile writes +system.cpu1.misc_regfile_reads 283037 # number of misc regfile reads +system.cpu1.misc_regfile_writes 133939 # number of misc regfile writes +system.cpu1.icache.replacements 109497 # number of replacements +system.cpu1.icache.tagsinuse 452.896457 # Cycle average of tags in use +system.cpu1.icache.total_refs 933398 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 110009 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.484742 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874842259000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 452.896457 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.884563 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 933398 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 933398 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 933398 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1723284 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 1723284 # number of overall hits +system.cpu1.icache.demand_hits::total 933398 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 933398 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1723284 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 217260 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 217260 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 217260 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 933398 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 115312 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 115312 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 115312 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 217260 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 217260 # number of overall misses +system.cpu1.icache.demand_misses::total 115312 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 115312 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 217260 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 3300371999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 3300371999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 3300371999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1940544 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1940544 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1940544 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 115312 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 1734763499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 1734763499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 1734763499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1048710 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1048710 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1048710 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1940544 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1940544 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1048710 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1048710 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1940544 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.111958 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.111958 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1048710 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.109956 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.109956 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.111958 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.109956 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15190.886491 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.084735 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15190.886491 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15044.084735 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15190.886491 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15044.084735 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 349000 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 115999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10575.757576 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6444.388889 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 52 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 10723 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 10723 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 10723 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 206537 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 206537 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 206537 # number of overall MSHR misses +system.cpu1.icache.writebacks 32 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 5233 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 5233 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 5233 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 110079 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 110079 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 110079 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 2520725000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 2520725000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 2520725000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 1320813499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 1320813499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 1320813499 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.106433 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.104966 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.106433 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.104966 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.106433 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.104966 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12204.713925 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12204.713925 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12204.713925 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11998.778141 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 248685 # number of replacements -system.cpu1.dcache.tagsinuse 476.656972 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2836087 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 248990 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 11.390365 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39851697000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 476.656972 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.930971 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1838875 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1838875 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 950135 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 950135 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 25812 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 25812 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 24969 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 24969 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 2789010 # number of demand (read+write) hits +system.cpu1.dcache.replacements 62178 # number of replacements +system.cpu1.dcache.tagsinuse 392.683341 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1692677 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62506 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 27.080232 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1874637412500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 392.683341 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.766960 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 1125457 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1125457 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 544800 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 544800 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 16569 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16569 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 14697 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 14697 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 1670257 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2789010 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 2789010 # number of overall hits +system.cpu1.dcache.demand_hits::total 1670257 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 1670257 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2789010 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 315850 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 315850 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 245510 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 245510 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 5339 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5339 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 3179 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3179 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 561360 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 1670257 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 106593 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 106593 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 157299 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 157299 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 1471 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1471 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 688 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 263892 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 561360 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 561360 # number of overall misses +system.cpu1.dcache.demand_misses::total 263892 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 263892 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 561360 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 4714821500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 8024030885 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 65075500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 42948000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 12738852385 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 12738852385 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 2154725 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2154725 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 1195645 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1195645 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 31151 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 31151 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 28148 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 28148 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 3350370 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 263892 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 1779114500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 5160494262 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 19390000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 8230500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 6939608762 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 6939608762 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 1232050 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1232050 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 702099 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 702099 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 18040 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18040 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 15385 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15385 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 1934149 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3350370 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 3350370 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1934149 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 1934149 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3350370 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.146585 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.205337 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.171391 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.112939 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.167552 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 1934149 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.086517 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.224041 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081541 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044719 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.136438 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.167552 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.136438 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14927.406997 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16690.725470 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32683.112236 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32806.910800 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12188.705750 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13181.509177 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13509.908776 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11962.936047 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 22692.839506 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 26297.154753 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 22692.839506 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 26297.154753 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 135872392 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 106000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 10757 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12631.067398 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 26500 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 86924497 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6880 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12634.374564 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 196815 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 98942 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 203211 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 1094 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 302153 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 302153 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 216908 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 42299 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 4245 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 3179 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 259207 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 259207 # number of overall MSHR misses +system.cpu1.dcache.writebacks 35754 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 63001 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 133631 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 299 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 196632 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 196632 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 43592 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 23668 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1172 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 67260 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 67260 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2649753500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1268849871 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 33277000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 33400500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3918603371 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3918603371 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 300850000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 586892500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 887742500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.100666 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 554109500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 750522486 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11597500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6158000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 1304631986 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 1304631986 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 18620500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 319072500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 337693000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035382 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.035378 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033710 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.136272 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064967 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.112939 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044719 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.077367 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.034775 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.077367 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.034775 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12216.024766 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29997.160004 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7839.104829 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10506.605851 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 15117.660291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 15117.660291 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12711.265829 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31710.431215 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9895.477816 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8950.581395 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1403,31 +1403,31 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5037 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 186073 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65315 40.13% 40.13% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.15% 40.27% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1923 1.18% 41.46% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 222 0.14% 41.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 95069 58.41% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162766 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63957 49.17% 49.17% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.18% 49.35% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1923 1.48% 50.83% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 222 0.17% 51.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63735 49.00% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130074 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863353937000 98.10% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90928000 0.00% 98.11% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 390512500 0.02% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 85006500 0.00% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35490372000 1.87% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1899410756000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.979208 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199477 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71613 40.63% 40.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.76% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1921 1.09% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102492 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 176271 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70248 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1921 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 70240 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142654 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1858831999000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90898500 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 391654500 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4204500 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38151374000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897470130500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980939 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.670408 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685322 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed @@ -1459,59 +1459,59 @@ system.cpu0.kern.syscall::144 2 0.93% 99.07% # nu system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 307 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3778 2.20% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155399 90.68% 93.10% # number of callpals executed -system.cpu0.kern.callpal::rdps 6322 3.69% 96.79% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.79% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::rti 4984 2.91% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.22% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 171369 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7417 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3842 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.16% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169337 91.54% 93.71% # number of callpals executed +system.cpu0.kern.callpal::rdps 6360 3.44% 97.14% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::rti 4767 2.58% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 184989 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7265 # number of protection mode switches system.cpu0.kern.mode_switch::user 1246 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1245 system.cpu0.kern.mode_good::user 1246 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.167858 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.171370 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897486158000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1924590000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895606727500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1863395000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3779 # number of times the context was actually changed +system.cpu0.kern.swap_context 3843 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4032 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54228 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17280 37.82% 37.82% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 4.20% 42.02% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 307 0.67% 42.69% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26187 57.31% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45695 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17261 47.36% 47.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 5.27% 52.64% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 307 0.84% 53.48% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16954 46.52% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 36443 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869444423500 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 345691000 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 121909500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29169069500 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1899081093500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998900 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2270 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 38355 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10172 33.29% 33.29% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 6.28% 39.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.34% 39.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18361 60.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30557 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10160 45.68% 45.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 8.63% 54.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.47% 54.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10056 45.22% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22240 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871109076500 98.61% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343280000 0.02% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 41782500 0.00% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25970941500 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897465080500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998820 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.647420 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.547683 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed @@ -1528,35 +1528,35 @@ system.cpu1.kern.syscall::74 10 9.01% 97.30% # nu system.cpu1.kern.syscall::132 3 2.70% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 111 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 222 0.47% 0.47% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.47% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.48% # number of callpals executed -system.cpu1.kern.callpal::swpctx 871 1.85% 2.32% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.33% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.34% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40736 86.30% 88.64% # number of callpals executed -system.cpu1.kern.callpal::rdps 2431 5.15% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.80% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.81% # number of callpals executed -system.cpu1.kern.callpal::rti 2730 5.78% 99.59% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.31% 99.90% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 391 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.31% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26005 82.46% 83.77% # number of callpals executed +system.cpu1.kern.callpal::rdps 2390 7.58% 91.35% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.35% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.37% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed +system.cpu1.kern.callpal::rti 2527 8.01% 99.39% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.46% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 47204 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1142 # number of protection mode switches +system.cpu1.kern.callpal::total 31535 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches system.cpu1.kern.mode_switch::user 492 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2462 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 761 +system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 521 system.cpu1.kern.mode_good::user 492 -system.cpu1.kern.mode_good::idle 269 -system.cpu1.kern.mode_switch_good::kernel 0.666375 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 29 +system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.109261 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.775636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 35491661500 1.87% 1.87% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 858235500 0.05% 1.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862377378000 98.09% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 872 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.014139 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.613679 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2030212000 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 852485500 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893908030500 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 392 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 4bc0cb36c..a8911f6cc 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -130,6 +130,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index a2519d6a4..b71599069 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 15 2011 20:24:21 -gem5 started Aug 15 2011 20:25:48 -gem5 executing on nadc-0270 +gem5 compiled Aug 17 2011 16:33:41 +gem5 started Aug 17 2011 16:35:09 +gem5 executing on nadc-0388 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858708914500 because m5_exit instruction encountered +Exiting @ tick 1857897393500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index eab7f5386..c17b9a135 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858709 # Number of seconds simulated -sim_ticks 1858708914500 # Number of ticks simulated +sim_seconds 1.857897 # Number of seconds simulated +sim_ticks 1857897393500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124964 # Simulator instruction rate (inst/s) -host_tick_rate 4374927606 # Simulator tick rate (ticks/s) -host_mem_usage 340632 # Number of bytes of host memory used -host_seconds 424.85 # Real time elapsed on the host -sim_insts 53091761 # Number of instructions simulated -system.l2c.replacements 391302 # number of replacements -system.l2c.tagsinuse 34944.632545 # Cycle average of tags in use -system.l2c.total_refs 2405534 # Total number of references to valid blocks. -system.l2c.sampled_refs 424233 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.670313 # Average number of references to valid blocks. +host_inst_rate 111366 # Simulator instruction rate (inst/s) +host_tick_rate 3896929552 # Simulator tick rate (ticks/s) +host_mem_usage 340840 # Number of bytes of host memory used +host_seconds 476.76 # Real time elapsed on the host +sim_insts 53094627 # Number of instructions simulated +system.l2c.replacements 391325 # number of replacements +system.l2c.tagsinuse 34942.141711 # Cycle average of tags in use +system.l2c.total_refs 2407783 # Total number of references to valid blocks. +system.l2c.sampled_refs 424213 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.675882 # Average number of references to valid blocks. system.l2c.warmup_cycle 5611809000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12322.596332 # Average occupied blocks per context -system.l2c.occ_blocks::1 22622.036213 # Average occupied blocks per context -system.l2c.occ_percent::0 0.188028 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.345185 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1801216 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1801216 # number of ReadReq hits -system.l2c.Writeback_hits::0 835065 # number of Writeback hits -system.l2c.Writeback_hits::total 835065 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.l2c.occ_blocks::0 12320.874417 # Average occupied blocks per context +system.l2c.occ_blocks::1 22621.267294 # Average occupied blocks per context +system.l2c.occ_percent::0 0.188002 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.345173 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1800422 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1800422 # number of ReadReq hits +system.l2c.Writeback_hits::0 834998 # number of Writeback hits +system.l2c.Writeback_hits::total 834998 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183191 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183191 # number of ReadExReq hits -system.l2c.demand_hits::0 1984407 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183185 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183185 # number of ReadExReq hits +system.l2c.demand_hits::0 1983607 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984407 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984407 # number of overall hits +system.l2c.demand_hits::total 1983607 # number of demand (read+write) hits +system.l2c.overall_hits::0 1983607 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1984407 # number of overall hits -system.l2c.ReadReq_misses::0 308126 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308126 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116919 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116919 # number of ReadExReq misses -system.l2c.demand_misses::0 425045 # number of demand (read+write) misses +system.l2c.overall_hits::total 1983607 # number of overall hits +system.l2c.ReadReq_misses::0 308136 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308136 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 36 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 36 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116850 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116850 # number of ReadExReq misses +system.l2c.demand_misses::0 424986 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 425045 # number of demand (read+write) misses -system.l2c.overall_misses::0 425045 # number of overall misses +system.l2c.demand_misses::total 424986 # number of demand (read+write) misses +system.l2c.overall_misses::0 424986 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 425045 # number of overall misses -system.l2c.ReadReq_miss_latency 16035962500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 424986 # number of overall misses +system.l2c.ReadReq_miss_latency 16038372500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6137530000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22173492500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22173492500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2109342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109342 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835065 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835065 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 44 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency 6129219000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22167591500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22167591500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2108558 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108558 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 834998 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 834998 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300110 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300110 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409452 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300035 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300035 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2408593 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409452 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409452 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2408593 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2408593 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409452 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146077 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.704545 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389587 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176407 # miss rate for demand accesses +system.l2c.overall_accesses::total 2408593 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146136 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.692308 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389455 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176446 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176407 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176446 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52043.522780 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52049.655022 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 13709.677419 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 11805.555556 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52493.863273 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52453.735558 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52167.399922 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52160.757060 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52167.399922 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52160.757060 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117722 # number of writebacks +system.l2c.writebacks 117715 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308126 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116919 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 425045 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 425045 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308136 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116850 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 424986 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 424986 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12333217500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4715307000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17048524500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17048524500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 809593500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1114721998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1924315498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146077 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12334391000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1500000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4708487500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17042878500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17042878500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810033000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115131998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925164998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146136 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.704545 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.692308 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389587 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389455 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176407 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176446 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176407 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176446 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40026.539468 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40329.689785 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40029.048862 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41666.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40295.143346 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -143,13 +143,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.266801 # Cycle average of tags in use +system.iocache.tagsinuse 1.260372 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338851000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.266801 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079175 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338825000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.260372 # Average occupied blocks per context +system.iocache.occ_percent::1 0.078773 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -167,9 +167,9 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722275806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742213804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742213804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency 5722330806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742268804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742268804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -192,19 +192,19 @@ system.iocache.ReadReq_avg_miss_latency::0 inf # system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137713.607191 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137714.930834 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137620.462648 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137621.780803 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137620.462648 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137621.780803 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64594068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64585068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6170.621704 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6173.300325 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -217,9 +217,9 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561421998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572363996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572363996 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561477996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572419994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572419994 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -234,9 +234,9 @@ system.iocache.overall_mshr_miss_rate::0 inf # ms system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85710.001877 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85711.349538 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10154080 # DTB read hits -system.cpu.dtb.read_misses 43144 # DTB read misses -system.cpu.dtb.read_acv 557 # DTB read access violations -system.cpu.dtb.read_accesses 952445 # DTB read accesses -system.cpu.dtb.write_hits 6614848 # DTB write hits -system.cpu.dtb.write_misses 9467 # DTB write misses -system.cpu.dtb.write_acv 320 # DTB write access violations -system.cpu.dtb.write_accesses 334339 # DTB write accesses -system.cpu.dtb.data_hits 16768928 # DTB hits -system.cpu.dtb.data_misses 52611 # DTB misses -system.cpu.dtb.data_acv 877 # DTB access violations -system.cpu.dtb.data_accesses 1286784 # DTB accesses -system.cpu.itb.fetch_hits 1336327 # ITB hits -system.cpu.itb.fetch_misses 39787 # ITB misses -system.cpu.itb.fetch_acv 1065 # ITB acv -system.cpu.itb.fetch_accesses 1376114 # ITB accesses +system.cpu.dtb.read_hits 10156439 # DTB read hits +system.cpu.dtb.read_misses 47122 # DTB read misses +system.cpu.dtb.read_acv 587 # DTB read access violations +system.cpu.dtb.read_accesses 977122 # DTB read accesses +system.cpu.dtb.write_hits 6633598 # DTB write hits +system.cpu.dtb.write_misses 11598 # DTB write misses +system.cpu.dtb.write_acv 414 # DTB write access violations +system.cpu.dtb.write_accesses 348122 # DTB write accesses +system.cpu.dtb.data_hits 16790037 # DTB hits +system.cpu.dtb.data_misses 58720 # DTB misses +system.cpu.dtb.data_acv 1001 # DTB access violations +system.cpu.dtb.data_accesses 1325244 # DTB accesses +system.cpu.itb.fetch_hits 1333506 # ITB hits +system.cpu.itb.fetch_misses 39875 # ITB misses +system.cpu.itb.fetch_acv 1125 # ITB acv +system.cpu.itb.fetch_accesses 1373381 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,275 +285,275 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 117237485 # number of cpu cycles simulated +system.cpu.numCycles 116343633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14455551 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12084424 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 532367 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13050115 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6745735 # Number of BTB hits +system.cpu.BPredUnit.lookups 14429393 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12066685 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 532769 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13006399 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6718907 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 978348 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45278 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29236023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74164805 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14455551 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7724083 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14385478 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2439202 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37224537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 262840 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335923 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9135306 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 83080083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.892691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.209867 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 975114 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45137 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29132882 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 73870037 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14429393 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7694021 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14329837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2400358 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36580859 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259840 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335514 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9103703 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 330872 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 82240103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.898224 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.215946 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68694605 82.68% 82.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1023953 1.23% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033478 2.45% 86.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 975932 1.17% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2976777 3.58% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 700548 0.84% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 794915 0.96% 92.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1072238 1.29% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4807637 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67910266 82.58% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1028745 1.25% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2026192 2.46% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 969086 1.18% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2957231 3.60% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 692695 0.84% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 793723 0.97% 92.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070407 1.30% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4791758 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 83080083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123301 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632603 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30551542 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36838313 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13095678 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1034253 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1560296 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 613869 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42144 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 72480994 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 127271 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1560296 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31800995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12812731 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19871114 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12262779 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4772166 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 68475649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4094 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 996372 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1464404 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45853535 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 83251938 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82772461 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479477 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38260770 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7592757 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700825 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251533 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12956852 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10812074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7051744 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2165147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2346616 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 60096918 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2117388 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 58031681 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8738509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4816872 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1449642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 83080083 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.698503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.311149 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 82240103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.124024 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.634930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30393620 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36243117 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13115942 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 960226 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1527197 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 611480 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42119 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 72202344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128169 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1527197 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31599738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12790599 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19770106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12256569 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4295892 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68223425 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6893 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 500375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1520799 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45688467 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 82930883 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82451857 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479026 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38262876 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7425583 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700626 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251543 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12011289 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10748783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7011270 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1273745 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 840870 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59873388 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116185 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 58064745 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115927 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8494287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4438181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1448436 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 82240103 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.706039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.353017 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56639169 68.17% 68.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11994103 14.44% 82.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5929931 7.14% 89.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3560683 4.29% 94.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2591551 3.12% 97.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1336446 1.61% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 797054 0.96% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 184259 0.22% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 46887 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56753994 69.01% 69.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11193552 13.61% 82.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5499635 6.69% 89.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3512602 4.27% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2643529 3.21% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1548822 1.88% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 707324 0.86% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 273213 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 107432 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 83080083 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 82240103 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68783 12.83% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 305726 57.04% 69.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161454 30.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64991 8.48% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 378109 49.32% 57.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323577 42.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39661101 68.34% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62145 0.11% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25610 0.04% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10623971 18.31% 86.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6695582 11.54% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952355 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39655118 68.29% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62174 0.11% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10635929 18.32% 86.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722688 11.58% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952312 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 58031681 # Type of FU issued -system.cpu.iq.rate 0.494993 # Inst issue rate -system.cpu.iq.fu_busy_cnt 535963 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009236 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 199072460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 70641414 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56449878 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 689765 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333951 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328040 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58199260 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361103 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 552721 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 58064745 # Type of FU issued +system.cpu.iq.rate 0.499080 # Inst issue rate +system.cpu.iq.fu_busy_cnt 766677 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013204 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 198560467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 70176120 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56485252 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 691729 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 332805 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328298 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58461376 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362765 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 576950 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1698615 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15451 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 23451 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 659180 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1635037 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13784 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 26178 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 618376 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 200829 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18266 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170591 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1560296 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8872665 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 625505 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65852816 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871025 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10812074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7051744 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1870069 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 491565 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7470 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 23451 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 385257 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383183 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 768440 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57350351 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10227555 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 681329 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1527197 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8965647 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616674 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65615916 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 866303 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10748783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7011270 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1869859 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 484759 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15737 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26178 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 387398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 770562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57355078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10233934 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 709666 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3638510 # number of nop insts executed -system.cpu.iew.exec_refs 16867130 # number of memory reference insts executed -system.cpu.iew.exec_branches 9102477 # Number of branches executed -system.cpu.iew.exec_stores 6639575 # Number of stores executed -system.cpu.iew.exec_rate 0.489181 # Inst execution rate -system.cpu.iew.wb_sent 56909286 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56777918 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28083144 # num instructions producing a value -system.cpu.iew.wb_consumers 37838196 # num instructions consuming a value +system.cpu.iew.exec_nop 3626343 # number of nop insts executed +system.cpu.iew.exec_refs 16894519 # number of memory reference insts executed +system.cpu.iew.exec_branches 9105401 # Number of branches executed +system.cpu.iew.exec_stores 6660585 # Number of stores executed +system.cpu.iew.exec_rate 0.492980 # Inst execution rate +system.cpu.iew.wb_sent 56953037 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56813550 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28082126 # num instructions producing a value +system.cpu.iew.wb_consumers 37827297 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.484298 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742190 # average fanout of values written-back +system.cpu.iew.wb_rate 0.488325 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742377 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56286421 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9443080 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667746 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 702134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 81519787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.690463 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.566765 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56289333 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9199733 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667749 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 702560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80712906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.697402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.610815 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59658965 73.18% 73.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9249179 11.35% 84.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5213125 6.39% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2451549 3.01% 93.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1701758 2.09% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 617367 0.76% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 434350 0.53% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 791574 0.97% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1401920 1.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59526212 73.75% 73.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8907000 11.04% 84.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4712189 5.84% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2603041 3.23% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533921 1.90% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 653559 0.81% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475046 0.59% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 520427 0.64% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1781511 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 81519787 # Number of insts commited each cycle -system.cpu.commit.count 56286421 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 80712906 # Number of insts commited each cycle +system.cpu.commit.count 56289333 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15506023 # Number of memory references committed -system.cpu.commit.loads 9113459 # Number of loads committed -system.cpu.commit.membars 227879 # Number of memory barriers committed -system.cpu.commit.branches 8462155 # Number of branches committed +system.cpu.commit.refs 15506640 # Number of memory references committed +system.cpu.commit.loads 9113746 # Number of loads committed +system.cpu.commit.membars 227885 # Number of memory barriers committed +system.cpu.commit.branches 8462674 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52124782 # Number of committed integer instructions. -system.cpu.commit.function_calls 744514 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1401920 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52127663 # Number of committed integer instructions. +system.cpu.commit.function_calls 744579 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1781511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 145596309 # The number of ROB reads -system.cpu.rob.rob_writes 133022104 # The number of ROB writes -system.cpu.timesIdled 1258228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34157402 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 53091761 # Number of Instructions Simulated -system.cpu.committedInsts_total 53091761 # Number of Instructions Simulated -system.cpu.cpi 2.208205 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.208205 # CPI: Total CPI of All Threads -system.cpu.ipc 0.452857 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.452857 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75150720 # number of integer regfile reads -system.cpu.int_regfile_writes 41017067 # number of integer regfile writes -system.cpu.fp_regfile_reads 166113 # number of floating regfile reads -system.cpu.fp_regfile_writes 167453 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996494 # number of misc regfile reads -system.cpu.misc_regfile_writes 949911 # number of misc regfile writes +system.cpu.rob.rob_reads 144169402 # The number of ROB reads +system.cpu.rob.rob_writes 132508314 # The number of ROB writes +system.cpu.timesIdled 1255085 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34103530 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53094627 # Number of Instructions Simulated +system.cpu.committedInsts_total 53094627 # Number of Instructions Simulated +system.cpu.cpi 2.191251 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.191251 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456360 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456360 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75184837 # number of integer regfile reads +system.cpu.int_regfile_writes 41033576 # number of integer regfile writes +system.cpu.fp_regfile_reads 166484 # number of floating regfile reads +system.cpu.fp_regfile_writes 167413 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996811 # number of misc regfile reads +system.cpu.misc_regfile_writes 949905 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1005090 # number of replacements -system.cpu.icache.tagsinuse 509.951538 # Cycle average of tags in use -system.cpu.icache.total_refs 8070754 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005599 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.025817 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23351335000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.951538 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995999 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8070755 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8070755 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8070755 # number of demand (read+write) hits +system.cpu.icache.replacements 1004633 # number of replacements +system.cpu.icache.tagsinuse 509.950442 # Cycle average of tags in use +system.cpu.icache.total_refs 8037423 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005142 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.996306 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23350341000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.950442 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8037424 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8037424 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8037424 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8070755 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8070755 # number of overall hits +system.cpu.icache.demand_hits::total 8037424 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8037424 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8070755 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1064551 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064551 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1064551 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8037424 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1066279 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066279 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1066279 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064551 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1064551 # number of overall misses +system.cpu.icache.demand_misses::total 1066279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1066279 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1064551 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15926988994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15926988994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15926988994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9135306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9135306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9135306 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1066279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15932595494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15932595494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15932595494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9103703 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9103703 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9103703 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9135306 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9135306 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9103703 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9103703 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9135306 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.116532 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.116532 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9103703 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.117126 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.117126 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.116532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.117126 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14961.226840 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14942.238846 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14961.226840 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14942.238846 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14961.226840 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14942.238846 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1261996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1325996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10516.633333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10607.968000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 232 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 58739 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 58739 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 58739 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005812 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005812 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005812 # number of overall MSHR misses +system.cpu.icache.writebacks 235 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 60920 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60920 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60920 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005359 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005359 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12051659996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12051659996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12051659996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12047978496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12047978496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12047978496 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110102 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110434 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.110102 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.110434 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.110102 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.110434 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.020493 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.757539 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403296 # number of replacements -system.cpu.dcache.tagsinuse 511.995990 # Cycle average of tags in use -system.cpu.dcache.total_refs 12128638 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403808 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.639813 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1402933 # number of replacements +system.cpu.dcache.tagsinuse 511.995988 # Cycle average of tags in use +system.cpu.dcache.total_refs 12110548 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403445 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.629158 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19282000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995990 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.995988 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7493448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7493448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4222901 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4222901 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192043 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192043 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220080 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220080 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11716349 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7476386 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7476386 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4221734 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4221734 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192117 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192117 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220089 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220089 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11698120 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11716349 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11716349 # number of overall hits +system.cpu.dcache.demand_hits::total 11698120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11698120 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11716349 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1778869 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1778869 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1934444 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1934444 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 23262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23262 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11698120 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1807054 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1807054 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1935931 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1935931 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 22609 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22609 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3713313 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3742985 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3713313 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3713313 # number of overall misses +system.cpu.dcache.demand_misses::total 3742985 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3742985 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3713313 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38377192500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57331444318 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 363604000 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3742985 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38901669000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57798606480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 338580500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 95708636818 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 95708636818 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9272317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9272317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6157345 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157345 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 215305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15429662 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 96700275480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 96700275480 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9283440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9283440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6157665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 214726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220091 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220091 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15441105 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15429662 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15429662 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15441105 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15441105 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15429662 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.191847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314169 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.108042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15441105 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.194653 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314394 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105292 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.240661 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.242404 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.240661 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.242404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21573.928434 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21527.673772 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29637.169294 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.716180 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15630.814203 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.474369 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25774.459847 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25835.068930 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25774.459847 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25835.068930 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 916364836 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 209000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 100291 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9137.059517 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23222.222222 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 919195309 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8982.218293 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834833 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 691203 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1635634 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5726 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2326837 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2326837 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087666 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298810 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17536 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834763 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 719698 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1637137 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5136 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2356835 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2356835 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087356 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298794 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17473 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386476 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386150 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24813377000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8487477836 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207860000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24800644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8504282309 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206126500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33300854836 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33300854836 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904007000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234009498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138016498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117303 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33304926309 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33304926309 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904508000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234433998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2138941998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117129 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048529 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048524 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081447 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081373 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089858 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089770 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089858 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089770 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22813.416067 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28404.263030 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11853.330292 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22808.210007 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28462.025037 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11796.858010 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -817,27 +817,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74884 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 241 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105815 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182822 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73517 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73519 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149159 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820013648500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 93762000 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384408000 0.02% 97.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38216235500 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858708054000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981745 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6435 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211583 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74879 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1881 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105809 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182812 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73512 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1881 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73515 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819252477000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94027000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384302500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38165726500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1857896533000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981744 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694788 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -876,8 +876,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175485 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6786 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed @@ -885,20 +885,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5215 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192443 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2101 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192432 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5954 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320349 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320289 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080914 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401263 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29483328500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2787065000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826437652500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401126 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29181178000 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2689752000 0.14% 1.72% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826025595000 98.28% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 4a2cdb533..003c8a4f1 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -132,6 +132,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 3ff5b25a6..71e7a1461 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 16 2011 18:25:06 -gem5 started Aug 16 2011 18:26:03 -gem5 executing on nadc-0270 +gem5 compiled Aug 18 2011 19:13:50 +gem5 started Aug 18 2011 19:17:05 +gem5 executing on nadc-0330 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 79671140500 because m5_exit instruction encountered +Exiting @ tick 79074238500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 149a25fba..a632bc081 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,101 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079671 # Number of seconds simulated -sim_ticks 79671140500 # Number of ticks simulated +sim_seconds 0.079074 # Number of seconds simulated +sim_ticks 79074238500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87754 # Simulator instruction rate (inst/s) -host_tick_rate 134768287 # Simulator tick rate (ticks/s) -host_mem_usage 390652 # Number of bytes of host memory used -host_seconds 591.17 # Real time elapsed on the host -sim_insts 51877383 # Number of instructions simulated -system.l2c.replacements 94989 # number of replacements -system.l2c.tagsinuse 38233.191793 # Cycle average of tags in use -system.l2c.total_refs 1049232 # Total number of references to valid blocks. -system.l2c.sampled_refs 127381 # Sample count of references to valid blocks. -system.l2c.avg_refs 8.236958 # Average number of references to valid blocks. +host_inst_rate 94294 # Simulator instruction rate (inst/s) +host_tick_rate 143722804 # Simulator tick rate (ticks/s) +host_mem_usage 389860 # Number of bytes of host memory used +host_seconds 550.19 # Real time elapsed on the host +sim_insts 51879448 # Number of instructions simulated +system.l2c.replacements 94945 # number of replacements +system.l2c.tagsinuse 38237.402486 # Cycle average of tags in use +system.l2c.total_refs 1052101 # Total number of references to valid blocks. +system.l2c.sampled_refs 127394 # Sample count of references to valid blocks. +system.l2c.avg_refs 8.258639 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6845.786735 # Average occupied blocks per context -system.l2c.occ_blocks::1 31387.405058 # Average occupied blocks per context -system.l2c.occ_percent::0 0.104458 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.478934 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 745449 # number of ReadReq hits -system.l2c.ReadReq_hits::1 96884 # number of ReadReq hits -system.l2c.ReadReq_hits::total 842333 # number of ReadReq hits -system.l2c.Writeback_hits::0 434303 # number of Writeback hits -system.l2c.Writeback_hits::total 434303 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 53 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 11 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 61363 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 61363 # number of ReadExReq hits -system.l2c.demand_hits::0 806812 # number of demand (read+write) hits -system.l2c.demand_hits::1 96884 # number of demand (read+write) hits -system.l2c.demand_hits::total 903696 # number of demand (read+write) hits -system.l2c.overall_hits::0 806812 # number of overall hits -system.l2c.overall_hits::1 96884 # number of overall hits -system.l2c.overall_hits::total 903696 # number of overall hits -system.l2c.ReadReq_misses::0 21092 # number of ReadReq misses -system.l2c.ReadReq_misses::1 91 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21183 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1724 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1724 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 107716 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107716 # number of ReadExReq misses -system.l2c.demand_misses::0 128808 # number of demand (read+write) misses -system.l2c.demand_misses::1 91 # number of demand (read+write) misses -system.l2c.demand_misses::total 128899 # number of demand (read+write) misses -system.l2c.overall_misses::0 128808 # number of overall misses -system.l2c.overall_misses::1 91 # number of overall misses -system.l2c.overall_misses::total 128899 # number of overall misses -system.l2c.ReadReq_miss_latency 1106899000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 5649720000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 6756619000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 6756619000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 766541 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 96975 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 863516 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 434303 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 434303 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1777 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1777 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 169079 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169079 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 935620 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 96975 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1032595 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 935620 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 96975 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1032595 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027516 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000938 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028454 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.970174 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.637075 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.137671 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000938 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.138610 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.137671 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000938 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.138610 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52479.565712 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12163725.274725 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12216204.840437 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 392.111369 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 6834.607637 # Average occupied blocks per context +system.l2c.occ_blocks::1 31402.794849 # Average occupied blocks per context +system.l2c.occ_percent::0 0.104288 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.479169 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 744764 # number of ReadReq hits +system.l2c.ReadReq_hits::1 111075 # number of ReadReq hits +system.l2c.ReadReq_hits::total 855839 # number of ReadReq hits +system.l2c.Writeback_hits::0 435185 # number of Writeback hits +system.l2c.Writeback_hits::total 435185 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 29 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 61163 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 61163 # number of ReadExReq hits +system.l2c.demand_hits::0 805927 # number of demand (read+write) hits +system.l2c.demand_hits::1 111075 # number of demand (read+write) hits +system.l2c.demand_hits::total 917002 # number of demand (read+write) hits +system.l2c.overall_hits::0 805927 # number of overall hits +system.l2c.overall_hits::1 111075 # number of overall hits +system.l2c.overall_hits::total 917002 # number of overall hits +system.l2c.ReadReq_misses::0 21158 # number of ReadReq misses +system.l2c.ReadReq_misses::1 88 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21246 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1695 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1695 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 107672 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107672 # number of ReadExReq misses +system.l2c.demand_misses::0 128830 # number of demand (read+write) misses +system.l2c.demand_misses::1 88 # number of demand (read+write) misses +system.l2c.demand_misses::total 128918 # number of demand (read+write) misses +system.l2c.overall_misses::0 128830 # number of overall misses +system.l2c.overall_misses::1 88 # number of overall misses +system.l2c.overall_misses::total 128918 # number of overall misses +system.l2c.ReadReq_miss_latency 1110312000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 5647552000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 6757864000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 6757864000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 765922 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 111163 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 877085 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 435185 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 435185 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1724 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1724 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 168835 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168835 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 934757 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 111163 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1045920 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 934757 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 111163 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1045920 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027624 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000792 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028416 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.983179 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.637735 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.137822 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000792 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.138614 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.137822 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000792 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.138614 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52477.171755 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12617181.818182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12669658.989937 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 429.793510 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52450.146682 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52451.445130 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52454.963977 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 74248560.439560 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 74301015.403538 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52454.963977 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 74248560.439560 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 74301015.403538 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52455.670263 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 76793909.090909 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 76846364.761172 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52455.670263 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 76793909.090909 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 76846364.761172 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,44 +105,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 87788 # number of writebacks -system.l2c.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 54 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 21129 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 1724 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 107716 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 128845 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 128845 # number of overall MSHR misses +system.l2c.writebacks 87817 # number of writebacks +system.l2c.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 52 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 21194 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1695 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 107672 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 128866 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 128866 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 846282000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 68961500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4309813000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 5156095000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 5156095000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 28946860000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 748497446 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 29695357446 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027564 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.217881 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.245445 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.970174 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 848895000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 67801500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 40000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4307970000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 5156865000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 5156865000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 28946635000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 749324446 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 29695959446 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.190657 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.218328 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.983179 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.637075 # mshr miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.637735 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.137711 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.328641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.466352 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.137711 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.328641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.466352 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40053.102371 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.870070 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40010.889747 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.137860 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.159253 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.297113 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.137860 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.159253 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.297113 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40053.552892 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.884956 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40010.123338 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40017.265997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40017.265997 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -150,27 +157,27 @@ system.l2c.soft_prefetch_mshr_full 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13454003 # DTB read hits -system.cpu.dtb.read_misses 56352 # DTB read misses -system.cpu.dtb.write_hits 7087382 # DTB write hits -system.cpu.dtb.write_misses 9992 # DTB write misses +system.cpu.dtb.read_hits 25900550 # DTB read hits +system.cpu.dtb.read_misses 64651 # DTB read misses +system.cpu.dtb.write_hits 7192881 # DTB write hits +system.cpu.dtb.write_misses 13036 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 2710 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2485 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 2886 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3633 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1097 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 572 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13510355 # DTB read accesses -system.cpu.dtb.write_accesses 7097374 # DTB write accesses +system.cpu.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25965201 # DTB read accesses +system.cpu.dtb.write_accesses 7205917 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 20541385 # DTB hits -system.cpu.dtb.misses 66344 # DTB misses -system.cpu.dtb.accesses 20607729 # DTB accesses -system.cpu.itb.inst_hits 6364119 # ITB inst hits -system.cpu.itb.inst_misses 7846 # ITB inst misses +system.cpu.dtb.hits 33093431 # DTB hits +system.cpu.dtb.misses 77687 # DTB misses +system.cpu.dtb.accesses 33171118 # DTB accesses +system.cpu.itb.inst_hits 6310237 # ITB inst hits +system.cpu.itb.inst_misses 7717 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -179,515 +186,515 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 1638 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1666 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4337 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4317 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 6371965 # ITB inst accesses -system.cpu.itb.hits 6364119 # DTB hits -system.cpu.itb.misses 7846 # DTB misses -system.cpu.itb.accesses 6371965 # DTB accesses -system.cpu.numCycles 159342282 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 6317954 # ITB inst accesses +system.cpu.itb.hits 6310237 # DTB hits +system.cpu.itb.misses 7717 # DTB misses +system.cpu.itb.accesses 6317954 # DTB accesses +system.cpu.numCycles 158148478 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 12557399 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10608534 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 646709 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11154990 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8780554 # Number of BTB hits +system.cpu.BPredUnit.lookups 12403718 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10473693 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 647177 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11077874 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8725285 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 870083 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 147860 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16065730 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 58984795 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12557399 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9650637 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 15473829 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2924896 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 92331 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 54317634 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 13079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97476 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 352 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6359256 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271099 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4481 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 88159945 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.843576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.082771 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 825346 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 148570 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15848399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 58464536 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12403718 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9550631 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 15311451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2844155 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 92931 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 55530026 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87268 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 242 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 6305391 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273417 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4478 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 88893250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.826227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.063220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 72705101 82.47% 82.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1269251 1.44% 83.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1767868 2.01% 85.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1323104 1.50% 87.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4670929 5.30% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 784846 0.89% 93.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 764674 0.87% 94.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 594095 0.67% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4280077 4.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 73600633 82.80% 82.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1267818 1.43% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758600 1.98% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1303689 1.47% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4624910 5.20% 92.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 783016 0.88% 93.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 755228 0.85% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 591057 0.66% 95.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4208299 4.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 88159945 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078808 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.370177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18165141 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 52904570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13778388 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1284946 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2026900 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1217125 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 74219 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 71956332 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 242640 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2026900 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19696589 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 30046666 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18688452 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12532114 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5169224 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 69519785 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 458017 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 271395 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2649588 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 136 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 71288380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 300070248 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 300002932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 67316 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 51888569 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 19399810 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 812076 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 663924 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14280198 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 12080470 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8183550 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3516652 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4162890 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62699092 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4040128 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 64163344 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 176578 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14335802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27947195 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1077859 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 88159945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.727806 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.267218 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 88893250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078431 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.369681 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17889712 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 54159673 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13693957 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1214512 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1935396 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1196991 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 73836 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 71078898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 241088 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1935396 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19399410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33418578 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16504909 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12375675 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5259282 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68683031 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 458239 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 182953 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2809051 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 70419738 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 296318415 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296251688 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 66727 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 51890716 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18529021 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 807343 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 660120 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14009466 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11753719 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8138684 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 887625 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1407204 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 61880073 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4035866 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 76596153 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165478 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13504163 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 24143581 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1073057 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 88893250 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.861664 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.427794 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 57192817 64.87% 64.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14605860 16.57% 81.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7161098 8.12% 89.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4501948 5.11% 94.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2827013 3.21% 97.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1117751 1.27% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 514797 0.58% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 165433 0.19% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 73228 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55657719 62.61% 62.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14175743 15.95% 78.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6670691 7.50% 86.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4258110 4.79% 90.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5767054 6.49% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1381276 1.55% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 654272 0.74% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 222610 0.25% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 105775 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 88159945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88893250 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31666 2.83% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 952275 85.11% 87.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 134939 12.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 28225 0.64% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4144387 93.61% 94.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 254758 5.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2393223 3.73% 3.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39946954 62.26% 65.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 68785 0.11% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 1 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 14271744 22.24% 88.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7481749 11.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2393223 3.12% 3.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39796206 51.96% 55.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 68882 0.09% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 880 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 55.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26733019 34.90% 90.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7603891 9.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 64163344 # Type of FU issued -system.cpu.iq.rate 0.402676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1118882 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017438 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 217833874 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81127166 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 59171315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 14043 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6386 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 62881739 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7264 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 405736 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 76596153 # Type of FU issued +system.cpu.iq.rate 0.484331 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4427371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.057801 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 246739451 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 79485386 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 59144129 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16089 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9683 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6534 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 78621825 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8476 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 479578 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2901377 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4794 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 62495 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1106451 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2574412 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7673 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75993 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1060962 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3460272 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8665 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15898252 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 9806 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2026900 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18611531 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 438534 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 66914101 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 333018 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 12080470 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8183550 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4008088 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 19000 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 218050 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 62495 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 538548 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 174972 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 63251439 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 13958320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 911905 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1935396 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 21193831 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 271998 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 66089327 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 340309 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11753719 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8138684 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4003938 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14746 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 54897 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75993 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 528463 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 171712 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 700175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 75657925 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26402371 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 938228 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174881 # number of nop insts executed -system.cpu.iew.exec_refs 21351791 # number of memory reference insts executed -system.cpu.iew.exec_branches 10154168 # Number of branches executed -system.cpu.iew.exec_stores 7393471 # Number of stores executed -system.cpu.iew.exec_rate 0.396953 # Inst execution rate -system.cpu.iew.wb_sent 62861793 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 59177701 # cumulative count of insts written-back -system.cpu.iew.wb_producers 31313815 # num instructions producing a value -system.cpu.iew.wb_consumers 56258797 # num instructions consuming a value +system.cpu.iew.exec_nop 173388 # number of nop insts executed +system.cpu.iew.exec_refs 33905993 # number of memory reference insts executed +system.cpu.iew.exec_branches 10120483 # Number of branches executed +system.cpu.iew.exec_stores 7503622 # Number of stores executed +system.cpu.iew.exec_rate 0.478398 # Inst execution rate +system.cpu.iew.wb_sent 75261887 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 59150663 # cumulative count of insts written-back +system.cpu.iew.wb_producers 31134340 # num instructions producing a value +system.cpu.iew.wb_consumers 55908801 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.371387 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.556603 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374020 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.556877 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 52000613 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 12648879 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2962269 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 619998 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 86133073 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.603724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.472813 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 52002678 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11830112 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2962809 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 620839 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 86957882 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.598021 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.499250 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 65560207 76.12% 76.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10449932 12.13% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2547278 2.96% 91.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1482527 1.72% 92.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3350826 3.89% 96.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 701267 0.81% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 459898 0.53% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 309587 0.36% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1271551 1.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67332100 77.43% 77.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9518451 10.95% 88.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2434571 2.80% 91.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1362976 1.57% 92.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3331765 3.83% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 735683 0.85% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 547610 0.63% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 322786 0.37% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1371940 1.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 86133073 # Number of insts commited each cycle -system.cpu.commit.count 52000613 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 86957882 # Number of insts commited each cycle +system.cpu.commit.count 52002678 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 16256192 # Number of memory references committed -system.cpu.commit.loads 9179093 # Number of loads committed +system.cpu.commit.refs 16257029 # Number of memory references committed +system.cpu.commit.loads 9179307 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.branches 8429232 # Number of branches committed +system.cpu.commit.branches 8429555 # Number of branches committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.int_insts 42424073 # Number of committed integer instructions. -system.cpu.commit.function_calls 530211 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1271551 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 42425734 # Number of committed integer instructions. +system.cpu.commit.function_calls 530212 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1371940 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 148569921 # The number of ROB reads -system.cpu.rob.rob_writes 131336271 # The number of ROB writes -system.cpu.timesIdled 1042391 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 71182337 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 51877383 # Number of Instructions Simulated -system.cpu.committedInsts_total 51877383 # Number of Instructions Simulated -system.cpu.cpi 3.071517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.071517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.325572 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.325572 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 282588210 # number of integer regfile reads -system.cpu.int_regfile_writes 61106256 # number of integer regfile writes -system.cpu.fp_regfile_reads 4893 # number of floating regfile reads -system.cpu.fp_regfile_writes 1856 # number of floating regfile writes -system.cpu.misc_regfile_reads 78190097 # number of misc regfile reads -system.cpu.misc_regfile_writes 511386 # number of misc regfile writes -system.cpu.icache.replacements 514643 # number of replacements -system.cpu.icache.tagsinuse 498.228732 # Cycle average of tags in use -system.cpu.icache.total_refs 5803201 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 515155 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.264961 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 4757853000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 498.228732 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.973103 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 5803201 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5803201 # number of ReadReq hits -system.cpu.icache.demand_hits::0 5803201 # number of demand (read+write) hits +system.cpu.rob.rob_reads 148477639 # The number of ROB reads +system.cpu.rob.rob_writes 129612178 # The number of ROB writes +system.cpu.timesIdled 1077202 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69255228 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 51879448 # Number of Instructions Simulated +system.cpu.committedInsts_total 51879448 # Number of Instructions Simulated +system.cpu.cpi 3.048384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.048384 # CPI: Total CPI of All Threads +system.cpu.ipc 0.328043 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.328043 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 332418442 # number of integer regfile reads +system.cpu.int_regfile_writes 60962055 # number of integer regfile writes +system.cpu.fp_regfile_reads 5604 # number of floating regfile reads +system.cpu.fp_regfile_writes 1962 # number of floating regfile writes +system.cpu.misc_regfile_reads 77838046 # number of misc regfile reads +system.cpu.misc_regfile_writes 516400 # number of misc regfile writes +system.cpu.icache.replacements 512227 # number of replacements +system.cpu.icache.tagsinuse 498.830885 # Cycle average of tags in use +system.cpu.icache.total_refs 5748931 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 512739 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.212198 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5183255000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 498.830885 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.974279 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 5748931 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5748931 # number of ReadReq hits +system.cpu.icache.demand_hits::0 5748931 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5803201 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 5803201 # number of overall hits +system.cpu.icache.demand_hits::total 5748931 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 5748931 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 5803201 # number of overall hits -system.cpu.icache.ReadReq_misses::0 555943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 555943 # number of ReadReq misses -system.cpu.icache.demand_misses::0 555943 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 5748931 # number of overall hits +system.cpu.icache.ReadReq_misses::0 556349 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 556349 # number of ReadReq misses +system.cpu.icache.demand_misses::0 556349 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 555943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 555943 # number of overall misses +system.cpu.icache.demand_misses::total 556349 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 556349 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 555943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8279205988 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8279205988 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8279205988 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 6359144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6359144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 6359144 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 556349 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8277697991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8277697991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8277697991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 6305280 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6305280 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 6305280 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6359144 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 6359144 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 6305280 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 6305280 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6359144 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.087424 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.087424 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 6305280 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.088235 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.088235 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.087424 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.088235 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14892.184969 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14878.606758 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14892.184969 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14878.606758 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14892.184969 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14878.606758 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1847492 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1588993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 239 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 215 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7730.092050 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7390.665116 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 43333 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 40711 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 40711 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 40711 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 515232 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 515232 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 515232 # number of overall MSHR misses +system.cpu.icache.writebacks 43070 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 43600 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 43600 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 43600 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 512749 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 512749 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 512749 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6216481992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6216481992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6216481992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 6199069493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6199069493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6199069493 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 5831500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 5831500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.081022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.081321 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.081022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.081321 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.081022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.081321 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12065.403531 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12065.403531 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12065.403531 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12089.871444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12089.871444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12089.871444 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 422430 # number of replacements -system.cpu.dcache.tagsinuse 511.738850 # Cycle average of tags in use -system.cpu.dcache.total_refs 13008876 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 422942 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.758061 # Average number of references to valid blocks. +system.cpu.dcache.replacements 424020 # number of replacements +system.cpu.dcache.tagsinuse 511.736879 # Cycle average of tags in use +system.cpu.dcache.total_refs 12922674 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 424532 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.439811 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48622000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.738850 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999490 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 8178281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8178281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4620670 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4620670 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 103371 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 103371 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 104399 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 104399 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 12798951 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.736879 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999486 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 8094618 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8094618 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4617752 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4617752 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 103516 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 103516 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 104961 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 104961 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 12712370 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12798951 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 12798951 # number of overall hits +system.cpu.dcache.demand_hits::total 12712370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 12712370 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 12798951 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 482976 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 482976 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2042377 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2042377 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 6546 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6546 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 11 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 2525353 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 12712370 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 499321 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 499321 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2045255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2045255 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 6620 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6620 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 2544576 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2525353 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2525353 # number of overall misses +system.cpu.dcache.demand_misses::total 2544576 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 2544576 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2525353 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 7135135000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 80554552279 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 99000500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 159000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 87689687279 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 87689687279 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 8661257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8661257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6663047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6663047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 109917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 109917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 104410 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 104410 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15324304 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 2544576 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 7292417500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 81386403267 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 99908000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 55000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 88678820767 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 88678820767 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 8593939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8593939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6663007 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6663007 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 110136 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 110136 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 104962 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 104962 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15256946 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15324304 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15324304 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15256946 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15256946 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15324304 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.055763 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.306523 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.059554 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000105 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.164794 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 15256946 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.058102 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.306957 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060108 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000010 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.166781 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.164794 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.166781 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14773.270307 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 14604.668139 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 39441.568466 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 39792.790272 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15123.816071 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15091.842900 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14454.545455 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 55000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 34723.734575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34850.136434 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34723.734575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34850.136434 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7890493 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 750500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1025 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7698.041951 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 30020 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 8903490 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 871500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1190 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 31 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7481.924370 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28112.903226 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 390970 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 234674 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1871578 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 927 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2106252 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2106252 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 248302 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 170799 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 5619 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 419101 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 419101 # number of overall MSHR misses +system.cpu.dcache.writebacks 392115 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 249191 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1874723 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1026 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2123914 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2123914 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 250130 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 170532 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 5594 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 420662 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 420662 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3306153500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 6559898993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66534000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 121000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9866052493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9866052493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 945697168 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 39145594668 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.028668 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3343532500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 6556670490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66421000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 52000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9900202990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9900202990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199457500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 947259668 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 39146717168 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.029105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025634 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025594 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051120 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050792 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000105 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000010 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.027349 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.027572 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.027349 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.027572 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13315.049818 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38407.127635 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11840.896957 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13367.179067 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38448.329287 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.614587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 52000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23534.816527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23534.816527 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 3bb35a882..23340838e 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -148,6 +148,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -1300,7 +1301,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-x86.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1320,7 +1321,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 1778e84dc..c0ff48d52 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout +Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 15 2011 11:12:24 -gem5 started Aug 15 2011 11:17:26 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:14:00 +gem5 started Aug 17 2011 19:16:38 +gem5 executing on nadc-0388 command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5151638875500 because m5_exit instruction encountered +Exiting @ tick 5139621012500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 34270b518..74858b319 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.151639 # Number of seconds simulated -sim_ticks 5151638875500 # Number of ticks simulated +sim_seconds 5.139621 # Number of seconds simulated +sim_ticks 5139621012500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136272 # Simulator instruction rate (inst/s) -host_tick_rate 835912815 # Simulator tick rate (ticks/s) -host_mem_usage 404376 # Number of bytes of host memory used -host_seconds 6162.89 # Real time elapsed on the host -sim_insts 839831731 # Number of instructions simulated -system.l2c.replacements 168782 # number of replacements -system.l2c.tagsinuse 38205.196893 # Cycle average of tags in use -system.l2c.total_refs 3762867 # Total number of references to valid blocks. -system.l2c.sampled_refs 202558 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.576739 # Average number of references to valid blocks. +host_inst_rate 264330 # Simulator instruction rate (inst/s) +host_tick_rate 1617420466 # Simulator tick rate (ticks/s) +host_mem_usage 409996 # Number of bytes of host memory used +host_seconds 3177.67 # Real time elapsed on the host +sim_insts 839951837 # Number of instructions simulated +system.l2c.replacements 170440 # number of replacements +system.l2c.tagsinuse 38394.915319 # Cycle average of tags in use +system.l2c.total_refs 3798996 # Total number of references to valid blocks. +system.l2c.sampled_refs 206462 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.400461 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11735.089031 # Average occupied blocks per context -system.l2c.occ_blocks::1 26470.107863 # Average occupied blocks per context -system.l2c.occ_percent::0 0.179063 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403902 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2331067 # number of ReadReq hits -system.l2c.ReadReq_hits::1 125887 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2456954 # number of ReadReq hits -system.l2c.Writeback_hits::0 1588356 # number of Writeback hits -system.l2c.Writeback_hits::total 1588356 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 357 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 150454 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 150454 # number of ReadExReq hits -system.l2c.demand_hits::0 2481521 # number of demand (read+write) hits -system.l2c.demand_hits::1 125887 # number of demand (read+write) hits -system.l2c.demand_hits::total 2607408 # number of demand (read+write) hits -system.l2c.overall_hits::0 2481521 # number of overall hits -system.l2c.overall_hits::1 125887 # number of overall hits -system.l2c.overall_hits::total 2607408 # number of overall hits -system.l2c.ReadReq_misses::0 64696 # number of ReadReq misses -system.l2c.ReadReq_misses::1 91 # number of ReadReq misses -system.l2c.ReadReq_misses::total 64787 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3960 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3960 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142190 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142190 # number of ReadExReq misses -system.l2c.demand_misses::0 206886 # number of demand (read+write) misses -system.l2c.demand_misses::1 91 # number of demand (read+write) misses -system.l2c.demand_misses::total 206977 # number of demand (read+write) misses -system.l2c.overall_misses::0 206886 # number of overall misses -system.l2c.overall_misses::1 91 # number of overall misses -system.l2c.overall_misses::total 206977 # number of overall misses -system.l2c.ReadReq_miss_latency 3398610000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 37586500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7439728500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 10838338500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 10838338500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2395763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 125978 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2521741 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1588356 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1588356 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4317 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292644 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292644 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2688407 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 125978 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2814385 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2688407 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 125978 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2814385 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027004 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000722 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027727 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.917304 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.485880 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.076955 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000722 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.077677 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.076955 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000722 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.077677 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52531.995796 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 37347362.637363 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 37399894.633158 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 9491.540404 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11966.871938 # Average occupied blocks per context +system.l2c.occ_blocks::1 26428.043381 # Average occupied blocks per context +system.l2c.occ_percent::0 0.182600 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.403260 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2331798 # number of ReadReq hits +system.l2c.ReadReq_hits::1 145238 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2477036 # number of ReadReq hits +system.l2c.Writeback_hits::0 1588821 # number of Writeback hits +system.l2c.Writeback_hits::total 1588821 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 321 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 321 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 149873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 149873 # number of ReadExReq hits +system.l2c.demand_hits::0 2481671 # number of demand (read+write) hits +system.l2c.demand_hits::1 145238 # number of demand (read+write) hits +system.l2c.demand_hits::total 2626909 # number of demand (read+write) hits +system.l2c.overall_hits::0 2481671 # number of overall hits +system.l2c.overall_hits::1 145238 # number of overall hits +system.l2c.overall_hits::total 2626909 # number of overall hits +system.l2c.ReadReq_misses::0 68032 # number of ReadReq misses +system.l2c.ReadReq_misses::1 90 # number of ReadReq misses +system.l2c.ReadReq_misses::total 68122 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3926 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3926 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142738 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142738 # number of ReadExReq misses +system.l2c.demand_misses::0 210770 # number of demand (read+write) misses +system.l2c.demand_misses::1 90 # number of demand (read+write) misses +system.l2c.demand_misses::total 210860 # number of demand (read+write) misses +system.l2c.overall_misses::0 210770 # number of overall misses +system.l2c.overall_misses::1 90 # number of overall misses +system.l2c.overall_misses::total 210860 # number of overall misses +system.l2c.ReadReq_miss_latency 3572833000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 39364500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7469371500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 11042204500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 11042204500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2399830 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 145328 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2545158 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1588821 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1588821 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4247 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4247 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292611 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292611 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2692441 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 145328 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2837769 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2692441 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 145328 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2837769 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.028349 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028968 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.924417 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.487808 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.078282 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000619 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.078901 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.078282 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000619 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.078901 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52516.947907 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 39698144.444444 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 39750661.392351 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 10026.617422 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52322.445320 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52329.243089 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52387.974537 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 119102620.879121 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 119155008.853658 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52387.974537 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 119102620.879121 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 119155008.853658 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52389.830147 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 122691161.111111 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 122743550.941258 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52389.830147 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 122691161.111111 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 122743550.941258 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142964 # number of writebacks +system.l2c.writebacks 142383 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 64785 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3960 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142190 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 206975 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 206975 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 68120 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3926 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142738 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 210858 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 210858 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2608555500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 158748000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5705556000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8314111500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8314111500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61533015500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222291500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62755307000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027041 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.514256 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.541298 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.917304 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2742078500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 157403500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5729564000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8471642500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8471642500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 61532429500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1222286000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 62754715500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028385 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.468733 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.497118 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.924417 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.485880 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.487808 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.076988 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.642946 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.719934 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.076988 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.642946 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.719934 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40264.806668 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40087.878788 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40126.281736 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40169.641261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40169.641261 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.078315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.450911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.529226 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.078315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.450911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.529226 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40253.647974 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.587876 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40140.425115 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47575 # number of replacements -system.iocache.tagsinuse 0.165993 # Cycle average of tags in use +system.iocache.replacements 47570 # number of replacements +system.iocache.tagsinuse 0.129176 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994554828000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.165993 # Average occupied blocks per context -system.iocache.occ_percent::1 0.010375 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994509673000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.129176 # Average occupied blocks per context +system.iocache.occ_percent::1 0.008073 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.ReadReq_misses::1 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.demand_misses::1 47625 # number of demand (read+write) misses +system.iocache.demand_misses::total 47625 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency 113908932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6372665160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6486574092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6486574092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 47625 # number of overall misses +system.iocache.overall_misses::total 47625 # number of overall misses +system.iocache.ReadReq_miss_latency 113496932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6374731160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6488228092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6488228092 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125312.356436 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125410.974586 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136401.223459 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136445.444349 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136189.592307 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136235.760462 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136189.592307 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136235.760462 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68832452 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68743556 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11274 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11268 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6105.415292 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6100.777068 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46668 # number of writebacks +system.iocache.writebacks 46667 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 905 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47629 # number of overall MSHR misses +system.iocache.demand_mshr_misses 47625 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47625 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66617982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3942909802 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4009527784 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4009527784 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66413982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3944974906 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4011388888 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4011388888 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,10 +235,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73287.108911 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84394.473502 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84182.489324 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84182.489324 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73385.615470 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84438.675214 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -255,415 +255,415 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449440116 # number of cpu cycles simulated +system.cpu.numCycles 449087853 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91251942 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91251942 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1248755 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89986362 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83883414 # Number of BTB hits +system.cpu.BPredUnit.lookups 91217869 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91217869 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1248400 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89951778 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83914735 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28443020 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 451559426 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91251942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83883414 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171343402 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6212938 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 155361 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82525667 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36777 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48486 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 28382208 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 451447456 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91217869 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83914735 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171329150 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6161718 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 187674 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 82029365 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 58090 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9929678 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 556225 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4240 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 287412747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.086350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403158 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 9909586 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 559902 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3975 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 286820350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.091965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.403436 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116615067 40.57% 40.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1502902 0.52% 41.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72824785 25.34% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1334009 0.46% 66.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1960992 0.68% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4008264 1.39% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1565099 0.54% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2187101 0.76% 70.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85414528 29.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 116059602 40.46% 40.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1498115 0.52% 40.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72812872 25.39% 66.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1272717 0.44% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2053780 0.72% 67.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3977163 1.39% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1588647 0.55% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2196057 0.77% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85361397 29.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 287412747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.203035 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.004715 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33501642 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78913894 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165819274 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4318222 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4859715 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 883193903 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 620 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4859715 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37708099 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52423571 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10078562 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165633752 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16709048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 878518097 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13834 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11653087 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2148761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 880915046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1725729327 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1725728311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1016 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843223982 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37691057 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 489641 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 492542 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43070507 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19803638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10755992 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3194647 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3198862 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 871443389 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 900411 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866326988 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165756 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 31682293 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47289832 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 148825 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 287412747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.014226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.369116 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 286820350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.203118 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.005254 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33356268 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 78574400 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165851521 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4241450 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4796711 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 882885518 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4796711 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37592669 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52283630 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10046208 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165609505 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16491627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 878188662 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14524 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11489749 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2124384 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 880584292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1724975571 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1724975011 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843343914 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37240371 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 491374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 493473 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42595982 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19743931 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10730204 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1270430 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1078815 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870972067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 898477 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 866458351 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 218010 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 31071842 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 45598434 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 144784 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 286820350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.020910 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.373009 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82109167 28.57% 28.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23029898 8.01% 36.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14429245 5.02% 41.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9845202 3.43% 45.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79549613 27.68% 72.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4871174 1.69% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72852960 25.35% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 572992 0.20% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152496 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82323990 28.70% 28.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22353891 7.79% 36.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14123864 4.92% 41.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9769344 3.41% 44.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79473928 27.71% 72.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4992964 1.74% 74.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72968378 25.44% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 634028 0.22% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 179963 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 287412747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 286820350 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 198235 9.39% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1790050 84.77% 94.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 123321 5.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 195550 8.86% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1820080 82.44% 91.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 192012 8.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 300321 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 831068974 95.93% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25494883 2.94% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9462810 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 302678 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 830926438 95.90% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25678898 2.96% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9550337 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866326988 # Type of FU issued -system.cpu.iq.rate 1.927569 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2111606 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002437 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2022483969 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 904056296 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855552025 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 163 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 498 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868138190 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1311048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 866458351 # Type of FU issued +system.cpu.iq.rate 1.929374 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2207642 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002548 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2022315315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 902983728 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 855563326 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 258 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 55 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 868363218 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1360799 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4470522 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13972 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31558 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2334229 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4398376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17098 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 43182 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2298641 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7818225 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 154758 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817204 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 161145 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4859715 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33597470 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6022609 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 872343800 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 300494 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19803638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10756022 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5535817 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26257 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31558 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 897955 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 529978 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1427933 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864227296 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25025491 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2099691 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4796711 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33445550 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6029017 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 871870544 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 303715 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19743931 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10730246 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 897675 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5516781 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26023 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 43182 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 896575 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 530355 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1426930 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 864313806 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25191099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2144544 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34264216 # number of memory reference insts executed -system.cpu.iew.exec_branches 86728541 # Number of branches executed -system.cpu.iew.exec_stores 9238725 # Number of stores executed -system.cpu.iew.exec_rate 1.922898 # Inst execution rate -system.cpu.iew.wb_sent 863623792 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855552085 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671682498 # num instructions producing a value -system.cpu.iew.wb_consumers 1172193952 # num instructions consuming a value +system.cpu.iew.exec_refs 34501157 # number of memory reference insts executed +system.cpu.iew.exec_branches 86709322 # Number of branches executed +system.cpu.iew.exec_stores 9310058 # Number of stores executed +system.cpu.iew.exec_rate 1.924598 # Inst execution rate +system.cpu.iew.wb_sent 863645103 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 855563381 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671472669 # num instructions producing a value +system.cpu.iew.wb_consumers 1171866734 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903595 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573013 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905114 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572994 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839831731 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 32406647 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 751584 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1254294 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282568841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.972131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.859839 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 839951837 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 31810372 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 753691 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1255440 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 282039656 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.978134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.864065 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102495617 36.27% 36.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13009464 4.60% 40.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4878881 1.73% 42.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76962899 27.24% 69.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4022439 1.42% 71.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1857740 0.66% 71.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1158664 0.41% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71619728 25.35% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6563409 2.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102542445 36.36% 36.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12533027 4.44% 40.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4681692 1.66% 42.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76967359 27.29% 69.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4010237 1.42% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1852910 0.66% 71.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1082027 0.38% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71603983 25.39% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6765976 2.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282568841 # Number of insts commited each cycle -system.cpu.commit.count 839831731 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 282039656 # Number of insts commited each cycle +system.cpu.commit.count 839951837 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23754906 # Number of memory references committed -system.cpu.commit.loads 15333113 # Number of loads committed +system.cpu.commit.refs 23777157 # Number of memory references committed +system.cpu.commit.loads 15345552 # Number of loads committed system.cpu.commit.membars 801 # Number of memory barriers committed -system.cpu.commit.branches 85519800 # Number of branches committed +system.cpu.commit.branches 85535847 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768449243 # Number of committed integer instructions. +system.cpu.commit.int_insts 768568499 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6563409 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6765976 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1148162427 # The number of ROB reads -system.cpu.rob.rob_writes 1749350545 # The number of ROB writes -system.cpu.timesIdled 3069835 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162027369 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 839831731 # Number of Instructions Simulated -system.cpu.committedInsts_total 839831731 # Number of Instructions Simulated -system.cpu.cpi 0.535155 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.535155 # CPI: Total CPI of All Threads -system.cpu.ipc 1.868618 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.868618 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1406651660 # number of integer regfile reads -system.cpu.int_regfile_writes 857603051 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.misc_regfile_reads 282221875 # number of misc regfile reads -system.cpu.misc_regfile_writes 407507 # number of misc regfile writes -system.cpu.icache.replacements 1029232 # number of replacements -system.cpu.icache.tagsinuse 510.471706 # Cycle average of tags in use -system.cpu.icache.total_refs 8833811 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1029744 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.578648 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54597932000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.471706 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997015 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8833811 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8833811 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8833811 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1146952939 # The number of ROB reads +system.cpu.rob.rob_writes 1748336346 # The number of ROB writes +system.cpu.timesIdled 3079654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162267503 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 839951837 # Number of Instructions Simulated +system.cpu.committedInsts_total 839951837 # Number of Instructions Simulated +system.cpu.cpi 0.534659 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.534659 # CPI: Total CPI of All Threads +system.cpu.ipc 1.870351 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.870351 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1407338355 # number of integer regfile reads +system.cpu.int_regfile_writes 857621513 # number of integer regfile writes +system.cpu.fp_regfile_reads 55 # number of floating regfile reads +system.cpu.misc_regfile_reads 282388563 # number of misc regfile reads +system.cpu.misc_regfile_writes 410581 # number of misc regfile writes +system.cpu.icache.replacements 1030220 # number of replacements +system.cpu.icache.tagsinuse 510.462524 # Cycle average of tags in use +system.cpu.icache.total_refs 8809167 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1030732 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.546515 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54553868000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.462524 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.996997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8809167 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8809167 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8809167 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8833811 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8833811 # number of overall hits +system.cpu.icache.demand_hits::total 8809167 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8809167 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8833811 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1095865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1095865 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1095865 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8809167 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1100416 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1100416 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1100416 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1095865 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1095865 # number of overall misses +system.cpu.icache.demand_misses::total 1100416 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1100416 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1095865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16411974488 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16411974488 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16411974488 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9929676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9929676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9929676 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1100416 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16477170489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16477170489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16477170489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9909583 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9909583 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9909583 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9929676 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9929676 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9909583 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9909583 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9929676 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.110363 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.110363 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9909583 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111046 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111046 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.110363 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111046 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14976.273983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14973.583162 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14976.273983 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14973.583162 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14976.273983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14973.583162 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2523491 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2487991 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 250 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 243 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10093.964000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10238.646091 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1562 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 63554 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 63554 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 63554 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1032311 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1032311 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1032311 # number of overall MSHR misses +system.cpu.icache.writebacks 1561 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 67148 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 67148 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 67148 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1033268 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1033268 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1033268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12460934991 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12460934991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12460934991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12490519491 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12490519491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12490519491 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.103962 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104270 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.103962 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.104270 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.103962 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.104270 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12070.911761 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12070.911761 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12070.911761 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12088.363804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 11904 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.021281 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25742 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 11916 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.160289 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5113551809500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.021281 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.376330 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 25787 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25787 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 13461 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 5.999270 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28519 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 13469 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.117381 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5126859452000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 5.999270 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.374954 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 28575 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28575 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 25790 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25790 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 28578 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28578 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 25790 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25790 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 12756 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 12756 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 28578 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28578 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 14318 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 14318 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 12756 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 12756 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 14318 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 14318 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 12756 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 12756 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 165450000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 165450000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 165450000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 38543 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38543 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 14318 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 14318 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 183495000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 183495000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 183495000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 42893 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 42893 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 38546 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38546 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 42896 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 42896 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 38546 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38546 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.330955 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 42896 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 42896 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.333807 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.330929 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.333784 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.330929 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.333784 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12970.366886 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.686548 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12970.366886 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.686548 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12970.366886 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.686548 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -673,83 +673,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2156 # number of writebacks +system.cpu.itb_walker_cache.writebacks 2322 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 12756 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 12756 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 12756 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 14318 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 14318 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 14318 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 126704000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 126704000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 126704000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 140154000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 140154000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 140154000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.330955 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.333807 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.330929 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.333784 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.330929 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.333784 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9932.894324 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9932.894324 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9932.894324 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9788.657634 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 123389 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.858352 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 128795 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 123405 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.043677 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101298251000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.858352 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.866147 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 128795 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 128795 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 143345 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.852844 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 148404 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 143358 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.035199 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5098934943000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.852844 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.865803 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 148429 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 148429 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 128795 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 128795 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 148429 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 148429 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 128795 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 128795 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 124284 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 124284 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 148429 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 148429 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 144294 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 144294 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 124284 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 124284 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 144294 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 144294 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 124284 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 124284 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1723739000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1723739000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1723739000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 253079 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 253079 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 144294 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 144294 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 1999592000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 1999592000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 1999592000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 292723 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 292723 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 253079 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 253079 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 292723 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 292723 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 253079 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 253079 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.491088 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 292723 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 292723 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492937 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.491088 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492937 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.491088 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492937 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13869.355669 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13857.762624 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13869.355669 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13857.762624 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13869.355669 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13857.762624 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -759,136 +759,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 38359 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 36787 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 124284 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 124284 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 124284 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 144294 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 144294 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 144294 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1347076500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1347076500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1347076500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1562734500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1562734500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1562734500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.491088 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492937 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.491088 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492937 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.491088 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492937 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10838.696051 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10838.696051 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10838.696051 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10830.211235 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1658768 # number of replacements -system.cpu.dcache.tagsinuse 511.997453 # Cycle average of tags in use -system.cpu.dcache.total_refs 17937343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1659280 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.810317 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1661784 # number of replacements +system.cpu.dcache.tagsinuse 511.998465 # Cycle average of tags in use +system.cpu.dcache.total_refs 18023326 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1662296 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.842429 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.997453 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11377605 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11377605 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6537446 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6537446 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 17915051 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.998465 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 11452816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11452816 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6548488 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6548488 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 18001304 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 17915051 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 17915051 # number of overall hits +system.cpu.dcache.demand_hits::total 18001304 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 18001304 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 17915051 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2443873 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2443873 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1875033 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1875033 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4318906 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 18001304 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2480783 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2480783 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1873809 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1873809 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4354592 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4318906 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4318906 # number of overall misses +system.cpu.dcache.demand_misses::total 4354592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4354592 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4318906 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 36695573000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63002180530 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 99697753530 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 99697753530 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13821478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13821478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8412479 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8412479 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22233957 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4354592 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37442770000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63502469838 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 100945239838 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 100945239838 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13933599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13933599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8422297 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8422297 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22355896 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22233957 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22233957 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22355896 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22355896 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22233957 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.176817 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222887 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.194248 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22355896 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.178043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222482 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.194785 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.194248 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.194785 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15015.335494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15093.125840 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33600.571579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33889.510531 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23084.029504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23181.331302 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23084.029504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23181.331302 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1066704607 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6645500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 69708 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15302.470405 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16996.163683 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1084772653 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6673000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73247 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 392 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14809.789520 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17022.959184 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1546279 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1076649 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1578166 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2654815 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2654815 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1367224 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 296867 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1664091 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1664091 # number of overall MSHR misses +system.cpu.dcache.writebacks 1548151 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1110544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1577040 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2687584 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2687584 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1370239 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 296769 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1667008 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1667008 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18012012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9730106607 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27742119107 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27742119107 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947466500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385748000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88333214500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098920 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18185435000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9767723153 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27953158153 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27953158153 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86946921000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385819000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 88332740000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098341 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035289 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035236 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074845 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074567 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074845 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074567 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13174.148859 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32775.979166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16671.034882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16671.034882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13271.724860 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32913.556177 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 2374c04cc..d17aac738 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/arm/scratch/sysexplr/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index c90ea128a..eb9dd7dcf 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 01:23:12 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 21:36:25 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 34059187000 because target called exit() +Exiting @ tick 34005216000 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 4687ee8e5..c921edf2f 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.034059 # Number of seconds simulated -sim_ticks 34059187000 # Number of ticks simulated +sim_seconds 0.034005 # Number of seconds simulated +sim_ticks 34005216000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66126 # Simulator instruction rate (inst/s) -host_tick_rate 24681632 # Simulator tick rate (ticks/s) -host_mem_usage 390692 # Number of bytes of host memory used -host_seconds 1379.94 # Real time elapsed on the host -sim_insts 91249685 # Number of instructions simulated +host_inst_rate 105088 # Simulator instruction rate (inst/s) +host_tick_rate 39162055 # Simulator tick rate (ticks/s) +host_mem_usage 396412 # Number of bytes of host memory used +host_seconds 868.32 # Real time elapsed on the host +sim_insts 91249660 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 68118375 # number of cpu cycles simulated +system.cpu.numCycles 68010433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 28264225 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22664811 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1422221 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25307717 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24243974 # Number of BTB hits +system.cpu.BPredUnit.lookups 28218889 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22621042 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1414269 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25157948 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24123842 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 113570 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 12949 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16006756 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135411326 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28264225 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24357544 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 33580343 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5963217 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14095577 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 112560 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 12935 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15977103 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135154938 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28218889 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24236402 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 33504566 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5937953 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14110938 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 149 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 15302646 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 409174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 68087836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.009786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.740415 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 185 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 15277206 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 405179 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 67980048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.009106 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.742708 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 34562720 50.76% 50.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6711035 9.86% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6005592 8.82% 69.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5006532 7.35% 76.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2908486 4.27% 81.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1809535 2.66% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1604855 2.36% 86.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3043201 4.47% 90.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6435880 9.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 34529861 50.79% 50.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6742939 9.92% 60.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5949333 8.75% 69.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5005104 7.36% 76.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2886229 4.25% 81.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1784892 2.63% 83.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1586062 2.33% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3028551 4.46% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6467077 9.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 68087836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.414928 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.987883 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18687372 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12574245 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31471424 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 979506 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4375289 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4503619 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 30122 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132907777 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31137 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4375289 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20501176 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1029913 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8340304 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30584541 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3256613 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128189435 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 288306 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1934414 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 149540723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 558211899 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 558194258 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17641 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429119 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42111599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 671866 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 673475 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7619625 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29869898 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6025284 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1488843 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 609505 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119834900 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 639591 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107581328 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 88511 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28762009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69412751 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 85229 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 68087836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.580037 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.751787 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 67980048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.414920 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.987268 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 18656916 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12586941 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31365316 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1012619 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4358256 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4495895 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 29408 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132644868 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31349 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4358256 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20449450 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1113784 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8328298 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30545374 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3184886 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128012570 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 287918 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1870803 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 149350454 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 557406814 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 557400643 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6171 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429079 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 41921370 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 670708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 672640 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7503691 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29849221 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6023274 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1356342 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 647782 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119728179 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 639242 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107493963 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 101688 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28653338 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69345788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 84885 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 67980048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.581258 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.754962 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25433380 37.35% 37.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14679481 21.56% 58.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10190142 14.97% 73.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8113823 11.92% 85.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4222569 6.20% 92.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2284074 3.35% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2481556 3.64% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 482376 0.71% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 200435 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25411198 37.38% 37.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14672249 21.58% 58.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10091036 14.84% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8117515 11.94% 85.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4245876 6.25% 91.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2261871 3.33% 95.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2477690 3.64% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 492806 0.72% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209807 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 68087836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 67980048 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 54498 10.46% 10.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191599 36.78% 47.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 274842 52.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 55128 10.57% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 195567 37.49% 48.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 270861 51.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 75715085 70.38% 70.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10984 0.01% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 147 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26496641 24.63% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5358008 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 75624393 70.35% 70.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11037 0.01% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 142 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 216 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26489525 24.64% 95.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5368647 4.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107581328 # Type of FU issued -system.cpu.iq.rate 1.579329 # Inst issue rate -system.cpu.iq.fu_busy_cnt 520966 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004843 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 283858560 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 149349424 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103392608 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1409 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1914 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 392 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108101654 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 640 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 354645 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107493963 # Type of FU issued +system.cpu.iq.rate 1.580551 # Inst issue rate +system.cpu.iq.fu_busy_cnt 521583 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004852 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 283590457 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 149134912 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 103313429 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 788 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 356 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 108015155 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 391 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 359898 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7294065 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41309 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 115131 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1278575 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7273393 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 45135 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 115664 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1276570 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30521 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 30487 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4375289 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 100045 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19331 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 120513426 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 799995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29869898 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6025284 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 634734 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10994 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1046 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 115131 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1306667 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 208134 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1514801 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105623962 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26069380 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1957366 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4358256 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 193721 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 31151 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 120406197 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 800153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29849221 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6023274 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 634379 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 11264 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1216 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 115664 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1297109 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 208567 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1505676 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 105540592 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26056532 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1953371 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38935 # number of nop insts executed -system.cpu.iew.exec_refs 31285154 # number of memory reference insts executed -system.cpu.iew.exec_branches 21282801 # Number of branches executed -system.cpu.iew.exec_stores 5215774 # Number of stores executed -system.cpu.iew.exec_rate 1.550594 # Inst execution rate -system.cpu.iew.wb_sent 103821828 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103393000 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60779146 # num instructions producing a value -system.cpu.iew.wb_consumers 97604196 # num instructions consuming a value +system.cpu.iew.exec_nop 38776 # number of nop insts executed +system.cpu.iew.exec_refs 31276826 # number of memory reference insts executed +system.cpu.iew.exec_branches 21265794 # Number of branches executed +system.cpu.iew.exec_stores 5220294 # Number of stores executed +system.cpu.iew.exec_rate 1.551829 # Inst execution rate +system.cpu.iew.wb_sent 103749789 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 103313785 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60697927 # num instructions producing a value +system.cpu.iew.wb_consumers 97489409 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.517843 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.622710 # average fanout of values written-back +system.cpu.iew.wb_rate 1.519087 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.622610 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262294 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 29250695 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554362 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1405283 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 63712548 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.432407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.197517 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 91262269 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 29143453 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554357 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1398047 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 63621793 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.434450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.199830 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 29657705 46.55% 46.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16839810 26.43% 72.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5318691 8.35% 81.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3965283 6.22% 87.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2147247 3.37% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 617953 0.97% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 460758 0.72% 92.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 194856 0.31% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4510245 7.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 29598088 46.52% 46.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16825513 26.45% 72.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5309975 8.35% 81.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3950826 6.21% 87.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2115946 3.33% 90.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 645775 1.02% 91.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 466588 0.73% 92.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 200515 0.32% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4508567 7.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 63712548 # Number of insts commited each cycle -system.cpu.commit.count 91262294 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 63621793 # Number of insts commited each cycle +system.cpu.commit.count 91262269 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322541 # Number of memory references committed -system.cpu.commit.loads 22575832 # Number of loads committed +system.cpu.commit.refs 27322531 # Number of memory references committed +system.cpu.commit.loads 22575827 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722426 # Number of branches committed +system.cpu.commit.branches 18722421 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533142 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533122 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4510245 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4508567 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 179709558 # The number of ROB reads -system.cpu.rob.rob_writes 245415120 # The number of ROB writes -system.cpu.timesIdled 1511 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30539 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249685 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249685 # Number of Instructions Simulated -system.cpu.cpi 0.746505 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.746505 # CPI: Total CPI of All Threads -system.cpu.ipc 1.339575 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.339575 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 501634552 # number of integer regfile reads -system.cpu.int_regfile_writes 122095043 # number of integer regfile writes -system.cpu.fp_regfile_reads 176 # number of floating regfile reads -system.cpu.fp_regfile_writes 493 # number of floating regfile writes -system.cpu.misc_regfile_reads 189665669 # number of misc regfile reads -system.cpu.misc_regfile_writes 11514 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 611.147709 # Cycle average of tags in use -system.cpu.icache.total_refs 15301726 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 719 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21281.955494 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 179513214 # The number of ROB reads +system.cpu.rob.rob_writes 245183550 # The number of ROB writes +system.cpu.timesIdled 1513 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30385 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 91249660 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249660 # Number of Instructions Simulated +system.cpu.cpi 0.745323 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.745323 # CPI: Total CPI of All Threads +system.cpu.ipc 1.341701 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.341701 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 501285464 # number of integer regfile reads +system.cpu.int_regfile_writes 121975389 # number of integer regfile writes +system.cpu.fp_regfile_reads 172 # number of floating regfile reads +system.cpu.fp_regfile_writes 453 # number of floating regfile writes +system.cpu.misc_regfile_reads 189360420 # number of misc regfile reads +system.cpu.misc_regfile_writes 11504 # number of misc regfile writes +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 610.965414 # Cycle average of tags in use +system.cpu.icache.total_refs 15276277 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 724 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 21099.830110 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 611.147709 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.298412 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 15301726 # number of ReadReq hits -system.cpu.icache.demand_hits 15301726 # number of demand (read+write) hits -system.cpu.icache.overall_hits 15301726 # number of overall hits -system.cpu.icache.ReadReq_misses 920 # number of ReadReq misses -system.cpu.icache.demand_misses 920 # number of demand (read+write) misses -system.cpu.icache.overall_misses 920 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32420000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32420000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32420000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 15302646 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 15302646 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 15302646 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000060 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000060 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000060 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35239.130435 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35239.130435 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35239.130435 # average overall miss latency +system.cpu.icache.occ_blocks::0 610.965414 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.298323 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 15276277 # number of ReadReq hits +system.cpu.icache.demand_hits 15276277 # number of demand (read+write) hits +system.cpu.icache.overall_hits 15276277 # number of overall hits +system.cpu.icache.ReadReq_misses 929 # number of ReadReq misses +system.cpu.icache.demand_misses 929 # number of demand (read+write) misses +system.cpu.icache.overall_misses 929 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32705500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32705500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32705500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 15277206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 15277206 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 15277206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35205.059203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35205.059203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35205.059203 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,139 +354,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 201 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 719 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 719 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 719 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 205 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 205 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 724 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 724 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 724 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24811500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24811500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24811500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 24957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 24957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 24957500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34508.344924 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34508.344924 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34508.344924 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34471.685083 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34471.685083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34471.685083 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943449 # number of replacements -system.cpu.dcache.tagsinuse 3548.737651 # Cycle average of tags in use -system.cpu.dcache.total_refs 29169762 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947545 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.784566 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12973953000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3548.737651 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.866391 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24598373 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4558911 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6726 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5752 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 29157284 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 29157284 # number of overall hits -system.cpu.dcache.ReadReq_misses 981426 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 176070 # number of WriteReq misses +system.cpu.dcache.replacements 943463 # number of replacements +system.cpu.dcache.tagsinuse 3549.969044 # Cycle average of tags in use +system.cpu.dcache.total_refs 29157181 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947559 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.770834 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12923369000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3549.969044 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.866692 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24585710 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 4558997 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 6727 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 5747 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 29144707 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 29144707 # number of overall hits +system.cpu.dcache.ReadReq_misses 969494 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 175984 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1157496 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1157496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5458949500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4506223422 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 9965172922 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9965172922 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25579799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1145478 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1145478 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5401004500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4496326950 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 126500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 9897331450 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9897331450 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 25555204 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6733 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5752 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30314780 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30314780 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.038367 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.037185 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses 6734 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 5747 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30290185 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30290185 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.037937 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.037167 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.001040 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.038183 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.038183 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5562.262972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 25593.362992 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8609.250418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8609.250418 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23278498 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.037817 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.037817 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 5570.951961 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 25549.634910 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 18071.428571 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 8640.350535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 8640.350535 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23178020 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8128 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8098 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2863.988435 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.190664 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942894 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 79978 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 129972 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 942900 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 67979 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 129940 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 209950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 209950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 901448 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 46098 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947546 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 197919 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 197919 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 901515 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 46044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 947559 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 947559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2249272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1085068550 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3334340550 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3334340550 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2251061000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1080314076 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3331375076 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3331375076 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035241 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009736 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031257 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031257 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.176649 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23538.299926 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3518.922089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3518.922089 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035277 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009724 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.031283 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.031283 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2496.975647 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23462.646078 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3515.744219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3515.744219 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 744 # number of replacements -system.cpu.l2cache.tagsinuse 9122.566359 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1596024 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15565 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.539287 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 745 # number of replacements +system.cpu.l2cache.tagsinuse 9143.143652 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1595891 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15573 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 102.478071 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 396.658867 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8725.907492 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.012105 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.266294 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 901114 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942894 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 31559 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932673 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932673 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1052 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 398.185089 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8744.958563 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.012152 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.266875 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 901164 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 942900 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 31521 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 932685 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 932685 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1058 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15592 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15592 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 36036000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 498937500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 534973500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 534973500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 902166 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942894 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 46099 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 948265 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 948265 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.001166 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.315408 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016443 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016443 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34254.752852 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34314.821183 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34310.768343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34310.768343 # average overall miss latency +system.cpu.l2cache.demand_misses 15598 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 15598 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 36283000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 498900000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 535183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 535183000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 902222 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 942900 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 46061 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 948283 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 948283 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.001173 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.315668 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.016449 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.016449 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34293.950851 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.242091 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34311.001410 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34311.001410 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,24 +499,24 @@ system.cpu.l2cache.writebacks 32 # nu system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1042 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1048 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15582 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15582 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 15588 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 15588 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 32402000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451783000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 484185000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 484185000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 32620500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451750500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 484371000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 484371000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001155 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.315408 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016432 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016432 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31095.969290 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31071.733150 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.353870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.353870 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001162 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.315668 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.016438 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.016438 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31126.431298 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.497937 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.325635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.325635 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index e75669d96..aaea60ae0 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/mcf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/arm/scratch/sysexplr/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index bc7ad177a..796b5db5e 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:01:24 -gem5 started Jul 15 2011 21:20:28 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 17:25:41 +gem5 started Aug 17 2011 17:30:37 +gem5 executing on nadc-0388 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 72477044500 because target called exit() +Exiting @ tick 71354418000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 705599adb..542fef85a 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.072477 # Number of seconds simulated -sim_ticks 72477044500 # Number of ticks simulated +sim_seconds 0.071354 # Number of seconds simulated +sim_ticks 71354418000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77321 # Simulator instruction rate (inst/s) -host_tick_rate 20144405 # Simulator tick rate (ticks/s) -host_mem_usage 388184 # Number of bytes of host memory used -host_seconds 3597.87 # Real time elapsed on the host +host_inst_rate 121216 # Simulator instruction rate (inst/s) +host_tick_rate 31091054 # Simulator tick rate (ticks/s) +host_mem_usage 393776 # Number of bytes of host memory used +host_seconds 2295.01 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 144954090 # number of cpu cycles simulated +system.cpu.numCycles 142708837 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38824502 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 38824502 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1297953 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 34176085 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 33665907 # Number of BTB hits +system.cpu.BPredUnit.lookups 38713050 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 38713050 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1277784 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 34149959 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 33632947 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29621269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 208413424 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38824502 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33665907 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 64871665 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11337306 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 39226989 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 173 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28797824 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223613 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 143548717 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.559587 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.289378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29563972 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 207959070 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38713050 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33632947 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 64671203 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11251281 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37585887 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28742973 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 228078 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 141556039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.590408 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.296325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 81263708 56.61% 56.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3814966 2.66% 59.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2940174 2.05% 61.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4531865 3.16% 64.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6958174 4.85% 69.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5381940 3.75% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7686471 5.35% 78.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4497983 3.13% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 26473436 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79448784 56.13% 56.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3733414 2.64% 58.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2922001 2.06% 60.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4489594 3.17% 64.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6936058 4.90% 68.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5469177 3.86% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7685058 5.43% 78.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4534397 3.20% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 26337556 18.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 143548717 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.267840 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.437789 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42470221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 29708132 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 53823823 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7717953 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9828588 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362980420 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 9828588 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 49423752 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5177939 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6920 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 54367682 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24743836 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 358046310 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 26 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 279275 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20623155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 321830310 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 881760386 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 881756685 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3701 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 141556039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271273 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.457226 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42383946 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 28100231 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 53949523 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7387481 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9734858 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 362029152 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 9734858 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 49345988 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4251907 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6895 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 54198746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24017645 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 357077595 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 112284 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20035490 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 320906324 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 879462898 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 879458894 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4004 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 73486118 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 72562132 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 479 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57368685 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 115894254 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38422039 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63771824 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11957885 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 350732960 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 56213524 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 115636696 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38304742 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 48747327 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8476101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 349796606 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 318496999 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118138 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 72405796 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 110903478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 319480009 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 127874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 71460780 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 105775967 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 143548717 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.218738 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 141556039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.256915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.760467 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32402965 22.57% 22.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 21621693 15.06% 37.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 28790762 20.06% 57.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 27748357 19.33% 77.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16847570 11.74% 88.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10612221 7.39% 96.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3153195 2.20% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2297476 1.60% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 74478 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32928700 23.26% 23.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18859354 13.32% 36.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25409770 17.95% 54.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 30153045 21.30% 75.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18699176 13.21% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10380312 7.33% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3284045 2.32% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1793650 1.27% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 47987 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 143548717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 141556039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25496 0.77% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3039528 91.70% 92.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 249529 7.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 25871 1.36% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1792047 94.50% 95.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78518 4.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181568475 57.01% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102910190 32.31% 89.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34001586 10.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181286722 56.74% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 231 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103851207 32.51% 89.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34325138 10.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 318496999 # Type of FU issued -system.cpu.iq.rate 2.197227 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3314553 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010407 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 783974996 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 423448386 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314158938 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 410 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2380 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321794634 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 207 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 44143933 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 319480009 # Type of FU issued +system.cpu.iq.rate 2.238684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1896436 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005936 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 782539275 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 421630860 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314706696 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1092 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2558 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 444 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321359193 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 541 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 45621060 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 25114866 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7244 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 332312 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6982288 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 24857308 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 396603 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6864991 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3439 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14779 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2744 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15359 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9828588 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 873179 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 111050 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 350733425 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 18952 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 115894254 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38422039 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 9734858 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 919734 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 96297 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 349797071 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 26061 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 115636696 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38304742 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 328 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 81820 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 332312 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1218982 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 194001 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1412983 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 316233239 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102244590 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2263760 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 6174 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 48786 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 396603 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1201294 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 194628 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1395922 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 317091801 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103103021 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2388208 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 135866033 # number of memory reference insts executed -system.cpu.iew.exec_branches 31754283 # Number of branches executed -system.cpu.iew.exec_stores 33621443 # Number of stores executed -system.cpu.iew.exec_rate 2.181610 # Inst execution rate -system.cpu.iew.wb_sent 314904091 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314159101 # cumulative count of insts written-back -system.cpu.iew.wb_producers 236907780 # num instructions producing a value -system.cpu.iew.wb_consumers 336010619 # num instructions consuming a value +system.cpu.iew.exec_refs 137049691 # number of memory reference insts executed +system.cpu.iew.exec_branches 31753831 # Number of branches executed +system.cpu.iew.exec_stores 33946670 # Number of stores executed +system.cpu.iew.exec_rate 2.221949 # Inst execution rate +system.cpu.iew.wb_sent 315540216 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 314707140 # cumulative count of insts written-back +system.cpu.iew.wb_producers 234790765 # num instructions producing a value +system.cpu.iew.wb_consumers 320680424 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.167301 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705060 # average fanout of values written-back +system.cpu.iew.wb_rate 2.205239 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.732164 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 72547467 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 71609181 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1297979 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133720129 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.080409 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.620850 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1277798 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131821181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.110378 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.644254 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52184328 39.03% 39.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25094085 18.77% 57.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17016190 12.73% 70.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12703052 9.50% 80.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3715852 2.78% 82.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3516909 2.63% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3092720 2.31% 87.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1223319 0.91% 88.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15173674 11.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 51293193 38.91% 38.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24103484 18.28% 57.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17099155 12.97% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12472180 9.46% 79.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3629365 2.75% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3499755 2.65% 85.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3079633 2.34% 87.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1175176 0.89% 88.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15469240 11.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133720129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131821181 # Number of insts commited each cycle system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed @@ -255,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15173674 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15469240 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 469286441 # The number of ROB reads -system.cpu.rob.rob_writes 711329741 # The number of ROB writes -system.cpu.timesIdled 41147 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1405373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 466153641 # The number of ROB reads +system.cpu.rob.rob_writes 709355946 # The number of ROB writes +system.cpu.timesIdled 34118 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1152798 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.521057 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.521057 # CPI: Total CPI of All Threads -system.cpu.ipc 1.919177 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.919177 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 555871897 # number of integer regfile reads -system.cpu.int_regfile_writes 282032504 # number of integer regfile writes -system.cpu.fp_regfile_reads 111 # number of floating regfile reads -system.cpu.fp_regfile_writes 126 # number of floating regfile writes -system.cpu.misc_regfile_reads 202657544 # number of misc regfile reads +system.cpu.cpi 0.512986 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.512986 # CPI: Total CPI of All Threads +system.cpu.ipc 1.949371 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.949371 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558552760 # number of integer regfile reads +system.cpu.int_regfile_writes 282337727 # number of integer regfile writes +system.cpu.fp_regfile_reads 537 # number of floating regfile reads +system.cpu.fp_regfile_writes 378 # number of floating regfile writes +system.cpu.misc_regfile_reads 203729290 # number of misc regfile reads system.cpu.icache.replacements 67 # number of replacements -system.cpu.icache.tagsinuse 826.564016 # Cycle average of tags in use -system.cpu.icache.total_refs 28796514 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27984.950437 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 827.771382 # Cycle average of tags in use +system.cpu.icache.total_refs 28741656 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1030 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 27904.520388 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 826.564016 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.403596 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28796514 # number of ReadReq hits -system.cpu.icache.demand_hits 28796514 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28796514 # number of overall hits -system.cpu.icache.ReadReq_misses 1310 # number of ReadReq misses -system.cpu.icache.demand_misses 1310 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1310 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47269000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47269000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47269000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28797824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28797824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28797824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36083.206107 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36083.206107 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36083.206107 # average overall miss latency +system.cpu.icache.occ_blocks::0 827.771382 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.404185 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28741656 # number of ReadReq hits +system.cpu.icache.demand_hits 28741656 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28741656 # number of overall hits +system.cpu.icache.ReadReq_misses 1317 # number of ReadReq misses +system.cpu.icache.demand_misses 1317 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1317 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47419000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47419000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47419000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28742973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28742973 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28742973 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36005.315110 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36005.315110 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36005.315110 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 280 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1030 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1030 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1030 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 286 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 286 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 286 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1031 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1031 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1031 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36240000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 36294500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 36294500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 36294500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35184.466019 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35184.466019 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35184.466019 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35203.200776 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35203.200776 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35203.200776 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072715 # number of replacements -system.cpu.dcache.tagsinuse 4076.040338 # Cycle average of tags in use -system.cpu.dcache.total_refs 86994905 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076811 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 41.888696 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 24878005000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.040338 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995127 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 55797094 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31197802 # number of WriteReq hits -system.cpu.dcache.demand_hits 86994896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 86994896 # number of overall hits -system.cpu.dcache.ReadReq_misses 2231267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 241949 # number of WriteReq misses -system.cpu.dcache.demand_misses 2473216 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2473216 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14264095500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4347965193 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18612060693 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18612060693 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 58028361 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2073043 # number of replacements +system.cpu.dcache.tagsinuse 4075.910712 # Cycle average of tags in use +system.cpu.dcache.total_refs 86335085 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2077139 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 41.564423 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 24475195000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4075.910712 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995095 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 55138633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 31196443 # number of WriteReq hits +system.cpu.dcache.demand_hits 86335076 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 86335076 # number of overall hits +system.cpu.dcache.ReadReq_misses 2261245 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 243308 # number of WriteReq misses +system.cpu.dcache.demand_misses 2504553 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2504553 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14586168500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4411412645 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 18997581145 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 18997581145 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 57399878 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 89468112 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 89468112 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.038451 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.007696 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.027644 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.027644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6392.823226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17970.585508 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 7525.448927 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 7525.448927 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 284000 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 88839629 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 88839629 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.039395 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.007739 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.028192 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.028192 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 6450.503373 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 18130.980671 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 7585.218259 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 7585.218259 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 284500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 84 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 87 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3380.952381 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3270.114943 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1447001 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 260149 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 136252 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 396401 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 396401 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1971118 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105697 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2076815 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2076815 # number of overall MSHR misses +system.cpu.dcache.writebacks 1447109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 289614 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 137796 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 427410 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 427410 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1971631 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 105512 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2077143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2077143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5560817000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1877216693 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7438033693 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7438033693 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5604635500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1879175645 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7483811145 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7483811145 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.033968 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003362 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.023213 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.023213 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2821.148708 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17760.359263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3581.461850 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3581.461850 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.034349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003356 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.023381 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.023381 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2842.639165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17810.065632 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3602.934966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3602.934966 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49102 # number of replacements -system.cpu.l2cache.tagsinuse 18748.930580 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3317286 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77110 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 43.020179 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 49075 # number of replacements +system.cpu.l2cache.tagsinuse 18765.136445 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3317892 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77084 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 43.042551 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6700.733856 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12048.196724 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.204490 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.367682 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1937583 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1447001 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63701 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2001284 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2001284 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34508 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 6711.152997 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12053.983448 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.204808 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.367858 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1938063 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1447109 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 63578 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2001641 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2001641 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34491 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 42051 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76559 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76559 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1180262000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1442869500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 2623131500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 2623131500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1972091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1447001 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses 42040 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 76531 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76531 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1179737500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1440022500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 2619760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 2619760000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1972554 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1447109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 105752 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2077843 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2077843 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.017498 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses 105618 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2078172 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2078172 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.017485 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.397638 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.036845 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.036845 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34202.561725 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.370693 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34262.875691 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34262.875691 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.398038 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.036826 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.036826 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34204.212693 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34253.627498 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34231.357228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34231.357228 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2884.615385 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29193 # number of writebacks +system.cpu.l2cache.writebacks 29187 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34508 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 34491 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42051 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76559 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76559 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 42040 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 76531 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76531 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1070240500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1069946000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1310019500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2380260000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2380260000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307849500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2377795500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2377795500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017498 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.397638 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.036845 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.036845 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31014.272053 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398038 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.036826 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.036826 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.019976 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31153.111698 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31090.531486 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31090.531486 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31109.645576 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index da98ab03d..0b5a9f54e 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/arm/scratch/sysexplr/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 6f903bc98..76519111d 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 01:32:47 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 19:29:05 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 298073533000 because target called exit() +Exiting @ tick 279789017500 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index 2fcdf0e96..ce0258252 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.298074 # Number of seconds simulated -sim_ticks 298073533000 # Number of ticks simulated +sim_seconds 0.279789 # Number of seconds simulated +sim_ticks 279789017500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55166 # Simulator instruction rate (inst/s) -host_tick_rate 28679876 # Simulator tick rate (ticks/s) -host_mem_usage 269720 # Number of bytes of host memory used -host_seconds 10393.12 # Real time elapsed on the host -sim_insts 573342447 # Number of instructions simulated +host_inst_rate 82238 # Simulator instruction rate (inst/s) +host_tick_rate 40132128 # Simulator tick rate (ticks/s) +host_mem_usage 268396 # Number of bytes of host memory used +host_seconds 6971.70 # Real time elapsed on the host +sim_insts 573340737 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 596147067 # number of cpu cycles simulated +system.cpu.numCycles 559578036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 233829808 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 186147170 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18448610 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 196945817 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 163449853 # Number of BTB hits +system.cpu.BPredUnit.lookups 229313741 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 182941703 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18381450 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 193404656 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 160578997 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12453913 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2627969 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 162380426 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1034385613 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233829808 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 175903766 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 266887423 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 82201728 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 101000880 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 119559 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 149451578 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4693812 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 591651753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.074862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.819629 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 11881056 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2583910 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 158920845 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1008979483 # Number of instructions fetch has processed +system.cpu.fetch.Branches 229313741 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 172460053 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 261292498 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 78073694 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 78434846 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 74310 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 146143180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4810109 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 555823153 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.154722 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.836930 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 324776586 54.89% 54.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24968353 4.22% 59.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 42079547 7.11% 66.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41036258 6.94% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43058687 7.28% 80.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15845137 2.68% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19209353 3.25% 86.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 16779568 2.84% 89.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63898264 10.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 294542931 52.99% 52.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24434943 4.40% 57.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 41500058 7.47% 64.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40458286 7.28% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42543437 7.65% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15388331 2.77% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 18846128 3.39% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 16230001 2.92% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61879038 11.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 591651753 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.392235 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.735118 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 182259766 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93638385 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 246087836 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8499427 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 61166339 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 34309417 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 95729 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1169323827 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 222317 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 61166339 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 199917017 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12999514 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52654373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 236541446 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 28373064 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1103035585 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 553 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9425467 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 15260638 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2023 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1222978410 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4879529633 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4879526297 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3336 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672201352 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 550777016 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2758214 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2758162 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 72689740 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 205506720 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 126653600 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67829085 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 74819363 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 969401999 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4509720 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 756022991 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1531556 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 398123182 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1180507714 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 631817 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 591651753 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.277818 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523431 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 555823153 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.409798 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.803108 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 176155270 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73642136 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 243542004 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5471546 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 57012197 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33378674 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 103333 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1139235628 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 221531 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 57012197 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 192762447 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6395244 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52127193 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 232252715 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15273357 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1073234487 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1226 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2982497 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8850274 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 56 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1193556306 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4743331903 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4743328950 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2953 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672198616 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 521357685 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2768330 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2768349 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48304499 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 196270626 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 121806649 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17302899 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13929275 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 937590667 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4537458 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 765577672 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3452362 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 365845767 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1020513301 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 659897 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 555823153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.377376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.646867 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262870171 44.43% 44.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 115951413 19.60% 64.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 93032822 15.72% 79.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 60874777 10.29% 90.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 37273328 6.30% 96.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12385550 2.09% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5290297 0.89% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3168401 0.54% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 804994 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 247650578 44.56% 44.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 96155335 17.30% 61.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 83204777 14.97% 76.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 61794788 11.12% 87.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 37799799 6.80% 94.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16279306 2.93% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7068984 1.27% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4337899 0.78% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1531687 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 591651753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 555823153 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 275664 3.50% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5340824 67.91% 71.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2248514 28.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140807 1.12% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6799143 54.23% 55.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5597920 44.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 517172409 68.41% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 381200 0.05% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 168107388 22.24% 90.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 70361857 9.31% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 513475935 67.07% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 381036 0.05% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 132 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 171848719 22.45% 89.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79871847 10.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 756022991 # Type of FU issued -system.cpu.iq.rate 1.268182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 7865002 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010403 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2113093981 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1372453088 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 706634766 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 304 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 765577672 # Type of FU issued +system.cpu.iq.rate 1.368134 # Inst issue rate +system.cpu.iq.fu_busy_cnt 12537870 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016377 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2102968429 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1308573624 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 707132694 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 300 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 763887839 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 154 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 6326745 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 778115390 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8455252 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 78733524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32052 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 425394 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 69049484 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 69497780 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 53390 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 614044 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 64202883 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 27275 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 28348 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 333 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 61166339 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3065417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 178437 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 983562638 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12157762 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 205506720 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 126653600 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2737845 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 99480 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4232 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 425394 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18747710 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6190012 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 24937722 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 730148660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 160105072 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 25874323 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 57012197 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2686334 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 121984 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 951489929 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12656652 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 196270626 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 121806649 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2752356 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48623 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7315 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 614044 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18618092 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6141777 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 24759869 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 733934042 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 162731362 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 31643630 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9650919 # number of nop insts executed -system.cpu.iew.exec_refs 226764096 # number of memory reference insts executed -system.cpu.iew.exec_branches 149136596 # Number of branches executed -system.cpu.iew.exec_stores 66659024 # Number of stores executed -system.cpu.iew.exec_rate 1.224779 # Inst execution rate -system.cpu.iew.wb_sent 718776639 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 706634782 # cumulative count of insts written-back -system.cpu.iew.wb_producers 402647843 # num instructions producing a value -system.cpu.iew.wb_consumers 726069262 # num instructions consuming a value +system.cpu.iew.exec_nop 9361804 # number of nop insts executed +system.cpu.iew.exec_refs 234660567 # number of memory reference insts executed +system.cpu.iew.exec_branches 147664615 # Number of branches executed +system.cpu.iew.exec_stores 71929205 # Number of stores executed +system.cpu.iew.exec_rate 1.311585 # Inst execution rate +system.cpu.iew.wb_sent 721950956 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 707132710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 399859111 # num instructions producing a value +system.cpu.iew.wb_consumers 707515910 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.185336 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554558 # average fanout of values written-back +system.cpu.iew.wb_rate 1.263689 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565159 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574686331 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 408895774 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3877903 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 20690983 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 530485415 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083322 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.748938 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 574684621 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 376818510 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3877561 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 20574438 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 498810957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.152109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.870885 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 277701641 52.35% 52.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 135265417 25.50% 77.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 46444883 8.76% 86.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 21050080 3.97% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18829655 3.55% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7074631 1.33% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8453874 1.59% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3355983 0.63% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 12309251 2.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 264965751 53.12% 53.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 115315817 23.12% 76.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 44565199 8.93% 85.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20246779 4.06% 89.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19896261 3.99% 93.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7328254 1.47% 94.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7611881 1.53% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3447651 0.69% 96.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15433364 3.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 530485415 # Number of insts commited each cycle -system.cpu.commit.count 574686331 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 498810957 # Number of insts commited each cycle +system.cpu.commit.count 574684621 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377295 # Number of memory references committed -system.cpu.commit.loads 126773187 # Number of loads committed +system.cpu.commit.refs 184376611 # Number of memory references committed +system.cpu.commit.loads 126772845 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192372 # Number of branches committed +system.cpu.commit.branches 120192030 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473702225 # Number of committed integer instructions. +system.cpu.commit.int_insts 473700857 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 12309251 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15433364 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1501751131 # The number of ROB reads -system.cpu.rob.rob_writes 2028662566 # The number of ROB writes -system.cpu.timesIdled 111416 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4495314 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573342447 # Number of Instructions Simulated -system.cpu.committedInsts_total 573342447 # Number of Instructions Simulated -system.cpu.cpi 1.039775 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.039775 # CPI: Total CPI of All Threads -system.cpu.ipc 0.961747 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.961747 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357392406 # number of integer regfile reads -system.cpu.int_regfile_writes 822350092 # number of integer regfile writes +system.cpu.rob.rob_reads 1434873586 # The number of ROB reads +system.cpu.rob.rob_writes 1960359919 # The number of ROB writes +system.cpu.timesIdled 94610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3754883 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 573340737 # Number of Instructions Simulated +system.cpu.committedInsts_total 573340737 # Number of Instructions Simulated +system.cpu.cpi 0.975996 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.975996 # CPI: Total CPI of All Threads +system.cpu.ipc 1.024595 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024595 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3384956860 # number of integer regfile reads +system.cpu.int_regfile_writes 820192225 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1272268831 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464346 # number of misc regfile writes -system.cpu.icache.replacements 14584 # number of replacements -system.cpu.icache.tagsinuse 1057.611572 # Cycle average of tags in use -system.cpu.icache.total_refs 149431777 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16238 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9202.597426 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1253867001 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463662 # number of misc regfile writes +system.cpu.icache.replacements 12859 # number of replacements +system.cpu.icache.tagsinuse 1069.062929 # Cycle average of tags in use +system.cpu.icache.total_refs 146126711 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 14705 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9937.212581 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1057.611572 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.516412 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 149431999 # number of ReadReq hits -system.cpu.icache.demand_hits 149431999 # number of demand (read+write) hits -system.cpu.icache.overall_hits 149431999 # number of overall hits -system.cpu.icache.ReadReq_misses 19579 # number of ReadReq misses -system.cpu.icache.demand_misses 19579 # number of demand (read+write) misses -system.cpu.icache.overall_misses 19579 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 272035000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 272035000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 272035000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 149451578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 149451578 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 149451578 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000131 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000131 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000131 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 13894.223403 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 13894.223403 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 13894.223403 # average overall miss latency +system.cpu.icache.occ_blocks::0 1069.062929 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.522003 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 146126714 # number of ReadReq hits +system.cpu.icache.demand_hits 146126714 # number of demand (read+write) hits +system.cpu.icache.overall_hits 146126714 # number of overall hits +system.cpu.icache.ReadReq_misses 16466 # number of ReadReq misses +system.cpu.icache.demand_misses 16466 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16466 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 235996000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 235996000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 235996000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 146143180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 146143180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 146143180 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000113 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000113 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000113 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 14332.321147 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 14332.321147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 14332.321147 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 26 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1649 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1649 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1649 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 17930 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 17930 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 17930 # number of overall MSHR misses +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1664 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1664 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1664 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 14802 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 14802 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 14802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 181899000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 181899000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 181899000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 154077500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 154077500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 154077500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000120 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000120 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000120 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10144.952593 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10144.952593 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10144.952593 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000101 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000101 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000101 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10409.235238 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10409.235238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10409.235238 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1208610 # number of replacements -system.cpu.dcache.tagsinuse 4059.103651 # Cycle average of tags in use -system.cpu.dcache.total_refs 205025542 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1212706 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 169.064507 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6026143000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4059.103651 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.990992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 147450901 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52819924 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2519475 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2232172 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 200270825 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 200270825 # number of overall hits -system.cpu.dcache.ReadReq_misses 1161160 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1419382 # number of WriteReq misses +system.cpu.dcache.replacements 1212005 # number of replacements +system.cpu.dcache.tagsinuse 4056.899454 # Cycle average of tags in use +system.cpu.dcache.total_refs 205223733 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1216101 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 168.755501 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5990497000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4056.899454 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.990454 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 147671766 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 52787083 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2532910 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 2231830 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 200458849 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 200458849 # number of overall hits +system.cpu.dcache.ReadReq_misses 1234695 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1452223 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2580542 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2580542 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 12492305000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 23242142500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 536000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 35734447500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 35734447500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 148612061 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 2686918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2686918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14259178500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25049559493 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 501000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 39308737993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39308737993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 148906461 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2519530 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2232172 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 202851367 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 202851367 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007813 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.026169 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses 2532965 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 2231830 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 203145767 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 203145767 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.008292 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.026774 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.012721 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.012721 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10758.469978 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 16374.832498 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 9745.454545 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 13847.651966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 13847.651966 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.013227 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013227 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 11548.745642 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17249.113596 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 9109.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 14629.675335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 14629.675335 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 438000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 493000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 58 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 60 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7551.724138 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8216.666667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1078008 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 287250 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1078933 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 1079434 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 358298 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1112430 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1366183 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1366183 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 873910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 340449 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1214359 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1214359 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1470728 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1470728 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 876397 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 339793 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1216190 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1216190 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6242148500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4342773500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10584922000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10584922000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6322149500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4329896000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10652045500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10652045500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005880 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005986 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005986 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7142.781865 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12756.017788 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8716.468524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8716.468524 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005886 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7213.796373 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12742.746319 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8758.537317 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8758.537317 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218841 # number of replacements -system.cpu.l2cache.tagsinuse 21122.736231 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1563440 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 239107 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.538663 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7625.121037 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13497.615194 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.232700 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.411915 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 759429 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1078034 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1135 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 231317 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 990746 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 990746 # number of overall hits -system.cpu.l2cache.ReadReq_misses 130133 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 466 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 107854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 237987 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 237987 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4450629000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 3872500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3694232000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 8144861000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 8144861000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 889562 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1078034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1601 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 339171 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1228733 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1228733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.146289 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.291068 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.317993 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.193685 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.193685 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34200.617829 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 8310.085837 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34252.155692 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34223.974419 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34223.974419 # average overall miss latency +system.cpu.l2cache.replacements 218713 # number of replacements +system.cpu.l2cache.tagsinuse 21078.689035 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1567898 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 239082 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.557993 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 207809197000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7685.698304 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13392.990732 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.234549 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.408722 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 760512 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1079434 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 60 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 232403 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 992915 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 992915 # number of overall hits +system.cpu.l2cache.ReadReq_misses 130232 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 107668 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 237900 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 237900 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 4454609000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 68500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3687681000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 8142290000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8142290000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 890744 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1079434 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 88 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 340071 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1230815 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1230815 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.146206 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.318182 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.316604 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.193287 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.193287 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34205.179986 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 2446.428571 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34250.482966 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34225.683060 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34225.683060 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 171107 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 130112 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 466 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 107854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 237966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 237966 # number of overall MSHR misses +system.cpu.l2cache.writebacks 171082 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 130210 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 107668 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 237878 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 237878 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4038190500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14451000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3344342000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7382532500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7382532500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4042910500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 868000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3338293500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7381204000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7381204000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146265 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.291068 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317993 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.193668 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.193668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31036.264910 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31010.729614 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.047917 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.476043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.476043 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146181 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.318182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.316604 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.193269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.193269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.155211 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.438013 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31029.367995 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31029.367995 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 6e985035a..6b22d733c 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 5c3a27385..434d3b8ec 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 15 2011 22:29:28 -gem5 started Aug 16 2011 00:29:05 -gem5 executing on nadc-0270 +gem5 compiled Aug 18 2011 15:15:16 +gem5 started Aug 18 2011 16:17:29 +gem5 executing on nadc-0330 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,17 +24,9 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -50,6 +42,14 @@ info: Increasing stack size by one page. * we're thinking about going to a movie this theater * which dog you said you chased - also invited to the meeting were several prominent scientists +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. - he ran home so quickly that his mother could hardly believe he had called from school - so many people attended that they spilled over into several neighboring fields - voting in favor of the bill were 36 Republicans and 4 moderate Democrats @@ -74,9 +74,11 @@ info: Increasing stack size by one page. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love +info: Increasing stack size by one page. +info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 580165782500 because target called exit() +Exiting @ tick 510840039000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index c22ac27ca..4d5ea332a 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,252 +1,253 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.580166 # Number of seconds simulated -sim_ticks 580165782500 # Number of ticks simulated +sim_seconds 0.510840 # Number of seconds simulated +sim_ticks 510840039000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108097 # Simulator instruction rate (inst/s) -host_tick_rate 41016714 # Simulator tick rate (ticks/s) -host_mem_usage 308780 # Number of bytes of host memory used -host_seconds 14144.62 # Real time elapsed on the host +host_inst_rate 116825 # Simulator instruction rate (inst/s) +host_tick_rate 39031538 # Simulator tick rate (ticks/s) +host_mem_usage 298988 # Number of bytes of host memory used +host_seconds 13087.88 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1160331566 # number of cpu cycles simulated +system.cpu.numCycles 1021680079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 262877499 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 262877499 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16588311 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 253230639 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 234035375 # Number of BTB hits +system.cpu.BPredUnit.lookups 254384753 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 254384753 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16610206 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 245027639 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 226325163 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 220532012 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1432148870 # Number of instructions fetch has processed -system.cpu.fetch.Branches 262877499 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 234035375 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 466979630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 149872263 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 313083903 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 89624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 603590 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 207528533 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4127463 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1131667315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.364134 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.250724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 212335544 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1381273626 # Number of instructions fetch has processed +system.cpu.fetch.Branches 254384753 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 226325163 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450902590 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 138126597 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 215756908 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 289533 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 200218324 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4741066 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 997472030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.589458 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 669263525 59.14% 59.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 35214145 3.11% 62.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 41599455 3.68% 65.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 35436065 3.13% 69.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23022634 2.03% 71.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 38989025 3.45% 74.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 50553577 4.47% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 40375996 3.57% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 197212893 17.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 550645930 55.20% 55.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34157576 3.42% 58.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 40518639 4.06% 62.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398845 3.45% 66.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21947419 2.20% 68.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 37358347 3.75% 72.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49115154 4.92% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39392814 3.95% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 189937306 19.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1131667315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.226554 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.234258 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289661842 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 260659329 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 390102547 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 60865041 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 130378556 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2610869598 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 131 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 130378556 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 331750332 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66732317 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25404 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 406405842 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196374864 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2558356966 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1635 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 80854908 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 99867012 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2379295437 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6012229860 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6011997427 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 232433 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 997472030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248987 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.351963 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 271753192 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 172636288 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 387288931 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47639747 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 118153872 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2516467041 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 118153872 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 307936660 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40922084 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10158 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 396952867 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 133496389 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2461579733 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3274 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26456916 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 89651322 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2291378441 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5783213965 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5782968371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 245594 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 951996410 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2701 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2688 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 416107098 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 617601057 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 240936819 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 418943952 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 163130234 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2450301589 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13994 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1951160680 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1081088 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 913572800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1588612926 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13441 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1131667315 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.724147 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.660846 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 864079414 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1434 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 310156167 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 591477986 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 228734468 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 236858488 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68220241 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2345816058 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6894 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1946813655 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1738463 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 808263725 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1297300959 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6341 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 997472030 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.951748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.794233 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 351347143 31.05% 31.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 244487319 21.60% 52.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 199318668 17.61% 70.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 156486661 13.83% 84.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 98199546 8.68% 92.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 52384868 4.63% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 22871565 2.02% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 5948232 0.53% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 623313 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 296825004 29.76% 29.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 173205263 17.36% 47.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 166698765 16.71% 63.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 150564381 15.09% 78.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 111664021 11.19% 90.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60204229 6.04% 96.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28392427 2.85% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8857592 0.89% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1060348 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1131667315 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 997472030 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2122690 14.73% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9149835 63.49% 78.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3139597 21.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2217543 14.62% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10152332 66.93% 81.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2799030 18.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2537569 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1320662421 67.69% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 454692889 23.30% 91.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173267801 8.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2499313 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1291834730 66.36% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 7 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471566042 24.22% 90.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 180913563 9.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1951160680 # Type of FU issued -system.cpu.iq.rate 1.681554 # Inst issue rate -system.cpu.iq.fu_busy_cnt 14412122 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007386 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5049479785 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3366653123 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1905319344 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2100 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 80588 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1963034295 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 129567465 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1946813655 # Type of FU issued +system.cpu.iq.rate 1.905502 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15168905 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007792 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4908001946 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3157548057 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1893221239 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4762 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 79762 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 141 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1959481671 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1576 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 155754534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233498897 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 89238 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2852385 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 91779636 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 207375826 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 336925 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3565166 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 79574659 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2147 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2286 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 130378556 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11646448 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3156259 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2450315583 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 538775 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 617601057 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 240939821 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13994 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2673819 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46064 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2852385 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15716124 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2393307 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18109431 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1917986142 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 447373751 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33174538 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 118153872 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9207603 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1436064 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2345822952 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1077995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 591477986 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 228734844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6894 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1048509 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 24437 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3565166 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15650863 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2406220 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18057083 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1908274747 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 461721448 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 38538908 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 614898275 # number of memory reference insts executed -system.cpu.iew.exec_branches 178446647 # Number of branches executed -system.cpu.iew.exec_stores 167524524 # Number of stores executed -system.cpu.iew.exec_rate 1.652964 # Inst execution rate -system.cpu.iew.wb_sent 1912144867 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1905319413 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1473027655 # num instructions producing a value -system.cpu.iew.wb_consumers 2208639649 # num instructions consuming a value +system.cpu.iew.exec_refs 635666266 # number of memory reference insts executed +system.cpu.iew.exec_branches 176848258 # Number of branches executed +system.cpu.iew.exec_stores 173944818 # Number of stores executed +system.cpu.iew.exec_rate 1.867781 # Inst execution rate +system.cpu.iew.wb_sent 1900894756 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1893221380 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1455907032 # num instructions producing a value +system.cpu.iew.wb_consumers 2156045862 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.642047 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.666939 # average fanout of values written-back +system.cpu.iew.wb_rate 1.853047 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675267 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 921335872 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 816844403 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16656646 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1001288759 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.527021 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.051909 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16638462 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 879318158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.738835 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.275232 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 413463578 41.29% 41.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 260152979 25.98% 67.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 102260608 10.21% 77.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 96065702 9.59% 87.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36102182 3.61% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27003750 2.70% 93.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 11563952 1.15% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10101799 1.01% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44574209 4.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 352136515 40.05% 40.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 212867347 24.21% 64.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 82048632 9.33% 73.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 90555710 10.30% 83.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 33314803 3.79% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25793757 2.93% 90.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15202497 1.73% 92.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12277140 1.40% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55121757 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1001288759 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 879318158 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -256,48 +257,49 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 44574209 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55121757 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3407039178 # The number of ROB reads -system.cpu.rob.rob_writes 5031819998 # The number of ROB writes -system.cpu.timesIdled 660069 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28664251 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3170029560 # The number of ROB reads +system.cpu.rob.rob_writes 4810732530 # The number of ROB writes +system.cpu.timesIdled 614029 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24208049 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.758888 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.758888 # CPI: Total CPI of All Threads -system.cpu.ipc 1.317717 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.317717 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3149568374 # number of integer regfile reads -system.cpu.int_regfile_writes 1776891813 # number of integer regfile writes -system.cpu.fp_regfile_reads 69 # number of floating regfile reads -system.cpu.misc_regfile_reads 1042858654 # number of misc regfile reads -system.cpu.icache.replacements 11377 # number of replacements -system.cpu.icache.tagsinuse 999.208417 # Cycle average of tags in use -system.cpu.icache.total_refs 207257376 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12873 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16100.161268 # Average number of references to valid blocks. +system.cpu.cpi 0.668206 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.668206 # CPI: Total CPI of All Threads +system.cpu.ipc 1.496544 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.496544 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3193160283 # number of integer regfile reads +system.cpu.int_regfile_writes 1761637277 # number of integer regfile writes +system.cpu.fp_regfile_reads 154 # number of floating regfile reads +system.cpu.fp_regfile_writes 7 # number of floating regfile writes +system.cpu.misc_regfile_reads 1050196665 # number of misc regfile reads +system.cpu.icache.replacements 10211 # number of replacements +system.cpu.icache.tagsinuse 970.164405 # Cycle average of tags in use +system.cpu.icache.total_refs 199977093 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11716 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 17068.717395 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 999.208417 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.487895 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 207264369 # number of ReadReq hits -system.cpu.icache.demand_hits 207264369 # number of demand (read+write) hits -system.cpu.icache.overall_hits 207264369 # number of overall hits -system.cpu.icache.ReadReq_misses 264164 # number of ReadReq misses -system.cpu.icache.demand_misses 264164 # number of demand (read+write) misses -system.cpu.icache.overall_misses 264164 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1771685500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1771685500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1771685500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 207528533 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 207528533 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 207528533 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001273 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001273 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001273 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6706.763601 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6706.763601 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6706.763601 # average overall miss latency +system.cpu.icache.occ_blocks::0 970.164405 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.473713 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 199983553 # number of ReadReq hits +system.cpu.icache.demand_hits 199983553 # number of demand (read+write) hits +system.cpu.icache.overall_hits 199983553 # number of overall hits +system.cpu.icache.ReadReq_misses 234771 # number of ReadReq misses +system.cpu.icache.demand_misses 234771 # number of demand (read+write) misses +system.cpu.icache.overall_misses 234771 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1605945000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1605945000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1605945000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 200218324 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 200218324 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 200218324 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001173 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001173 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001173 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6840.474335 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6840.474335 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6840.474335 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,137 +308,137 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 10 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1449 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1449 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1449 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 262715 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 262715 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 262715 # number of overall MSHR misses +system.cpu.icache.writebacks 7 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 2045 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2045 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2045 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 232726 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 232726 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 232726 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 946409000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 946409000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 946409000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 856837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 856837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 856837000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001266 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001266 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001266 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3602.417068 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3602.417068 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3602.417068 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.001162 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.001162 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.001162 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3681.741619 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3681.741619 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3681.741619 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529282 # number of replacements -system.cpu.dcache.tagsinuse 4088.724472 # Cycle average of tags in use -system.cpu.dcache.total_refs 462560130 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533378 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 182.586306 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2171355000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4088.724472 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998224 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 313694284 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147510138 # number of WriteReq hits -system.cpu.dcache.demand_hits 461204422 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 461204422 # number of overall hits -system.cpu.dcache.ReadReq_misses 3013642 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1650063 # number of WriteReq misses -system.cpu.dcache.demand_misses 4663705 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4663705 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 49018707500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 39546398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 88565105500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 88565105500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 316707926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2528466 # number of replacements +system.cpu.dcache.tagsinuse 4087.809380 # Cycle average of tags in use +system.cpu.dcache.total_refs 450171258 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2532562 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 177.753302 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2146317000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.809380 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998000 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 301389470 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147508711 # number of WriteReq hits +system.cpu.dcache.demand_hits 448898181 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 448898181 # number of overall hits +system.cpu.dcache.ReadReq_misses 3181552 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1651490 # number of WriteReq misses +system.cpu.dcache.demand_misses 4833042 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4833042 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 53701118000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 39968131000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 93669249000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 93669249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 304571022 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 465868127 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 465868127 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.009516 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011062 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010011 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010011 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16265.604043 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23966.598851 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18990.288944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18990.288944 # average overall miss latency +system.cpu.dcache.demand_accesses 453731223 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 453731223 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010446 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011072 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010652 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010652 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16878.906270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24201.255230 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19381.012828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19381.012828 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 11500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2230730 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1251973 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 635644 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1887617 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1887617 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1761669 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1014419 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2776088 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2776088 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229597 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1420514 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 666840 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2087354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2087354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1761038 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 984650 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2745688 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2745688 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14862715000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 18460103000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33322818000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33322818000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14931886500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17549642500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32481529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32481529000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005562 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006801 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005959 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005959 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8436.723925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18197.710216 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12003.516459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12003.516459 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005782 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006601 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006051 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006051 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8479.025722 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17823.229066 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11830.014554 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11830.014554 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 576428 # number of replacements -system.cpu.l2cache.tagsinuse 21465.975306 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3191905 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 595566 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.359448 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 303406560000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7746.429717 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13719.545589 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.236402 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.418687 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1431199 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2230740 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1291 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 527665 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1958864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1958864 # number of overall hits -system.cpu.l2cache.ReadReq_misses 339288 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 248403 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247962 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 587250 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 587250 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11588417000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 11435000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8493856500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20082273500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20082273500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1770487 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2230740 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 249694 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 775627 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2546114 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2546114 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191635 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994830 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.319692 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230646 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230646 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34155.104218 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 46.034066 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34254.670070 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34197.145168 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34197.145168 # average overall miss latency +system.cpu.l2cache.replacements 575462 # number of replacements +system.cpu.l2cache.tagsinuse 21596.870084 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3194136 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594624 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.371690 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 286599678000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7777.126789 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13819.743295 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.237339 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421745 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1433421 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229604 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1236 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524443 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957864 # number of overall hits +system.cpu.l2cache.ReadReq_misses 339163 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 219734 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247117 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 586280 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 586280 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11583073000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9821500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8475872500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20058945500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20058945500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1772584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229604 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 220970 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771560 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2544144 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2544144 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191338 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994406 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320282 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230443 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230443 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34151.935795 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 44.697225 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34299.026372 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34213.934468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34213.934468 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 412302 # number of writebacks +system.cpu.l2cache.writebacks 411447 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 339288 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 248403 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247962 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 587250 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 587250 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 339163 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 219734 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247117 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 586280 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 586280 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10519285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7701348000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7687301500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18206586500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18206586500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10521035500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6812324500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7664755500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18185791000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18185791000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191635 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994830 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319692 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230646 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230646 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.999552 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.441987 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.933764 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31003.127288 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31003.127288 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191338 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994406 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320282 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230443 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230443 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.587446 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.596321 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31016.706661 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.951695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.951695 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index eb7300ec9..9f597bc96 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index c5767db8f..cbdf9cdc6 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 18:05:51 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 15:37:38 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -11,4 +13,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.083333 -Exiting @ tick 90508462500 because target called exit() +Exiting @ tick 90005685500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 5bb546882..17e0eeb5a 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.090508 # Number of seconds simulated -sim_ticks 90508462500 # Number of ticks simulated +sim_seconds 0.090006 # Number of seconds simulated +sim_ticks 90005685500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100669 # Simulator instruction rate (inst/s) -host_tick_rate 24259753 # Simulator tick rate (ticks/s) -host_mem_usage 252880 # Number of bytes of host memory used -host_seconds 3730.81 # Real time elapsed on the host +host_inst_rate 147306 # Simulator instruction rate (inst/s) +host_tick_rate 35301564 # Simulator tick rate (ticks/s) +host_mem_usage 258568 # Number of bytes of host memory used +host_seconds 2549.62 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 105325909 # DTB read hits -system.cpu.dtb.read_misses 93344 # DTB read misses -system.cpu.dtb.read_acv 48634 # DTB read access violations -system.cpu.dtb.read_accesses 105419253 # DTB read accesses -system.cpu.dtb.write_hits 79718162 # DTB write hits -system.cpu.dtb.write_misses 1558 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 79719720 # DTB write accesses -system.cpu.dtb.data_hits 185044071 # DTB hits -system.cpu.dtb.data_misses 94902 # DTB misses -system.cpu.dtb.data_acv 48634 # DTB access violations -system.cpu.dtb.data_accesses 185138973 # DTB accesses -system.cpu.itb.fetch_hits 58032693 # ITB hits -system.cpu.itb.fetch_misses 351 # ITB misses +system.cpu.dtb.read_hits 105557144 # DTB read hits +system.cpu.dtb.read_misses 98530 # DTB read misses +system.cpu.dtb.read_acv 48617 # DTB read access violations +system.cpu.dtb.read_accesses 105655674 # DTB read accesses +system.cpu.dtb.write_hits 79803143 # DTB write hits +system.cpu.dtb.write_misses 1575 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 79804718 # DTB write accesses +system.cpu.dtb.data_hits 185360287 # DTB hits +system.cpu.dtb.data_misses 100105 # DTB misses +system.cpu.dtb.data_acv 48618 # DTB access violations +system.cpu.dtb.data_accesses 185460392 # DTB accesses +system.cpu.itb.fetch_hits 58034543 # ITB hits +system.cpu.itb.fetch_misses 355 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 58033044 # ITB accesses +system.cpu.itb.fetch_accesses 58034898 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 181016927 # number of cpu cycles simulated +system.cpu.numCycles 180011373 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 56908652 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 33128839 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3549307 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 40569971 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 32137344 # Number of BTB hits +system.cpu.BPredUnit.lookups 56898591 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 33211966 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3574908 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 40524300 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 31971911 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10736279 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1343 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 59988242 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 503999677 # Number of instructions fetch has processed -system.cpu.fetch.Branches 56908652 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42873623 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 93805949 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12846494 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 17811682 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7687 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 58032693 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1098562 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 180895317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.786140 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.241759 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10712923 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1454 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 60019462 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 503879026 # Number of instructions fetch has processed +system.cpu.fetch.Branches 56898591 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42684834 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 93650208 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12840667 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 16998273 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7695 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 58034543 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1110351 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 179889864 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.801042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.244247 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 87089368 48.14% 48.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8126413 4.49% 52.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9953250 5.50% 58.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6311167 3.49% 61.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13618559 7.53% 69.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9505792 5.25% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5896466 3.26% 77.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3503145 1.94% 79.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36891157 20.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 86239656 47.94% 47.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7968101 4.43% 52.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9837104 5.47% 57.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6455150 3.59% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13616411 7.57% 69.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9477434 5.27% 74.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5920004 3.29% 77.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3509603 1.95% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36866401 20.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 180895317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.314383 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.784268 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 66262768 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13721794 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 87804231 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829220 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9277304 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 10346731 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4343 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 492360513 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11994 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9277304 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 70771279 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4688791 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 402464 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 87101855 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8653624 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 479416177 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 50185 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7149377 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 311562327 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 628686073 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 332583088 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 296102985 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 179889864 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316083 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.799151 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 66046381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13163939 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 87675814 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3794037 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9209693 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 10269415 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4478 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 492179347 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12338 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9209693 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 70508732 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4469526 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 393246 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 86965796 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8342871 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 478964918 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37494 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 6850524 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 311020883 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 627865578 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 331628214 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 296237364 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 52030008 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38365 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 280 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23740235 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 110658167 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85526614 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15465988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10430696 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 434355597 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 252 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 419519707 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1756806 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 57360180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32293778 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 180895317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.319130 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.993104 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 51488564 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38437 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 301 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23116949 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 110811715 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85594435 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10526782 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6196399 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 433477285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 262 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 418941176 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1867414 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 56505676 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32298658 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 179889864 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.328876 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.003011 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44820498 24.78% 24.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 29979430 16.57% 41.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 28846817 15.95% 57.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25627519 14.17% 71.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22480714 12.43% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15907163 8.79% 92.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8306052 4.59% 97.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3747889 2.07% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1179235 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 44759242 24.88% 24.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 29396949 16.34% 41.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 28140071 15.64% 56.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26088939 14.50% 71.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22436504 12.47% 83.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15753855 8.76% 92.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8086358 4.50% 97.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3859739 2.15% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1368207 0.76% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 180895317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 179889864 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 69354 0.60% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 38404 0.33% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5709 0.05% 0.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 19332 0.17% 1.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 2037444 17.66% 18.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 875919 7.59% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5719458 49.56% 75.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2774394 24.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 136828 1.12% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 42966 0.35% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 1217 0.01% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 10365 0.09% 1.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1870140 15.36% 16.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1752756 14.40% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5345662 43.91% 75.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3013374 24.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164900286 39.31% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2243051 0.53% 39.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33844550 8.07% 47.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7897710 1.88% 49.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2993735 0.71% 50.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16825521 4.01% 54.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1580906 0.38% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 107841565 25.71% 80.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 81358802 19.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 164274346 39.21% 39.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126487 0.51% 39.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33733978 8.05% 47.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7896269 1.88% 49.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2902886 0.69% 50.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16725004 3.99% 54.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1576072 0.38% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 108193841 25.83% 80.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 81478712 19.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 419519707 # Type of FU issued -system.cpu.iq.rate 2.317572 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11540014 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027508 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 685462958 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 291219348 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 242560611 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347768593 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 200512633 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164917620 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253759021 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 177267119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14283738 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 418941176 # Type of FU issued +system.cpu.iq.rate 2.327304 # Inst issue rate +system.cpu.iq.fu_busy_cnt 12173308 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029057 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 682905692 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289620140 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 241865929 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 348907246 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 200439541 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164655906 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 252869699 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 178211204 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14135279 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15903681 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 169313 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15968 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12005886 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16057229 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 148927 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 77022 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12073707 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 213972 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 215342 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9277304 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2317535 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 350843 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 460018539 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2425230 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 110658167 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85526614 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 252 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 132 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9209693 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2342336 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 345962 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 459173536 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2310367 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 110811715 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85594435 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 262 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 272 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 15968 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3438704 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 545017 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3983721 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 411016170 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 105467950 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8503537 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 77022 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3457252 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 554336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4011588 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 410317513 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 105704327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8623663 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25662690 # number of nop insts executed -system.cpu.iew.exec_refs 185187689 # number of memory reference insts executed -system.cpu.iew.exec_branches 48286737 # Number of branches executed -system.cpu.iew.exec_stores 79719739 # Number of stores executed -system.cpu.iew.exec_rate 2.270595 # Inst execution rate -system.cpu.iew.wb_sent 408658291 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 407478231 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198809248 # num instructions producing a value -system.cpu.iew.wb_consumers 280006771 # num instructions consuming a value +system.cpu.iew.exec_nop 25695989 # number of nop insts executed +system.cpu.iew.exec_refs 185509104 # number of memory reference insts executed +system.cpu.iew.exec_branches 48173918 # Number of branches executed +system.cpu.iew.exec_stores 79804777 # Number of stores executed +system.cpu.iew.exec_rate 2.279398 # Inst execution rate +system.cpu.iew.wb_sent 407775826 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 406521835 # cumulative count of insts written-back +system.cpu.iew.wb_producers 197958297 # num instructions producing a value +system.cpu.iew.wb_consumers 277706216 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.251050 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.710016 # average fanout of values written-back +system.cpu.iew.wb_rate 2.258312 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.712834 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 61360500 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60526277 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3545034 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 171618013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.322976 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.832511 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3570557 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 170680171 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.335740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.860101 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 70646303 41.16% 41.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 26006834 15.15% 56.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15503557 9.03% 65.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13282401 7.74% 73.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8794833 5.12% 78.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6427011 3.74% 81.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5152706 3.00% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2862149 1.67% 86.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22942219 13.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71080695 41.65% 41.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25597473 15.00% 56.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15025586 8.80% 65.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12350485 7.24% 72.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8728325 5.11% 77.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6123095 3.59% 81.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5311766 3.11% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3136870 1.84% 86.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23325876 13.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 171618013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 170680171 # Number of insts commited each cycle system.cpu.commit.count 398664569 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168275214 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 44587530 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22942219 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 23325876 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 608697886 # The number of ROB reads -system.cpu.rob.rob_writes 929339596 # The number of ROB writes -system.cpu.timesIdled 2701 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 121610 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 606542164 # The number of ROB reads +system.cpu.rob.rob_writes 927610224 # The number of ROB writes +system.cpu.timesIdled 2703 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 121509 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated -system.cpu.cpi 0.481973 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.481973 # CPI: Total CPI of All Threads -system.cpu.ipc 2.074805 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.074805 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 410790761 # number of integer regfile reads -system.cpu.int_regfile_writes 176550359 # number of integer regfile writes -system.cpu.fp_regfile_reads 159677516 # number of floating regfile reads -system.cpu.fp_regfile_writes 106247961 # number of floating regfile writes +system.cpu.cpi 0.479296 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.479296 # CPI: Total CPI of All Threads +system.cpu.ipc 2.086395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.086395 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 410036032 # number of integer regfile reads +system.cpu.int_regfile_writes 175891320 # number of integer regfile writes +system.cpu.fp_regfile_reads 159397664 # number of floating regfile reads +system.cpu.fp_regfile_writes 105955330 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2105 # number of replacements -system.cpu.icache.tagsinuse 1832.667923 # Cycle average of tags in use -system.cpu.icache.total_refs 58027410 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4031 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14395.289010 # Average number of references to valid blocks. +system.cpu.icache.replacements 2104 # number of replacements +system.cpu.icache.tagsinuse 1835.532395 # Cycle average of tags in use +system.cpu.icache.total_refs 58029268 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4030 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14399.322084 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1832.667923 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.894857 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 58027410 # number of ReadReq hits -system.cpu.icache.demand_hits 58027410 # number of demand (read+write) hits -system.cpu.icache.overall_hits 58027410 # number of overall hits -system.cpu.icache.ReadReq_misses 5283 # number of ReadReq misses -system.cpu.icache.demand_misses 5283 # number of demand (read+write) misses -system.cpu.icache.overall_misses 5283 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 167989000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 167989000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 167989000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 58032693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 58032693 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 58032693 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1835.532395 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.896256 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 58029268 # number of ReadReq hits +system.cpu.icache.demand_hits 58029268 # number of demand (read+write) hits +system.cpu.icache.overall_hits 58029268 # number of overall hits +system.cpu.icache.ReadReq_misses 5275 # number of ReadReq misses +system.cpu.icache.demand_misses 5275 # number of demand (read+write) misses +system.cpu.icache.overall_misses 5275 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 167800500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 167800500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 167800500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 58034543 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 58034543 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 58034543 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 31798.031422 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 31798.031422 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 31798.031422 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 31810.521327 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 31810.521327 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 31810.521327 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1252 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1252 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1252 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4031 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4031 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4031 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 4030 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 4030 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 4030 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 123392000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 123392000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 123392000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 123364000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 123364000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 123364000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30610.766559 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30610.766559 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30610.766559 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30611.414392 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 787 # number of replacements -system.cpu.dcache.tagsinuse 3295.378268 # Cycle average of tags in use -system.cpu.dcache.total_refs 164327794 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4186 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39256.520306 # Average number of references to valid blocks. +system.cpu.dcache.replacements 783 # number of replacements +system.cpu.dcache.tagsinuse 3295.270928 # Cycle average of tags in use +system.cpu.dcache.total_refs 164706127 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 39384.535390 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3295.378268 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.804536 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 90826520 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73501267 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 3295.270928 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.804510 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 91204849 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 73501271 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 164327787 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 164327787 # number of overall hits -system.cpu.dcache.ReadReq_misses 1669 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19461 # number of WriteReq misses -system.cpu.dcache.demand_misses 21130 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 21130 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 56052000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 568707000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 624759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 624759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 90828189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 164706120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 164706120 # number of overall hits +system.cpu.dcache.ReadReq_misses 1662 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19457 # number of WriteReq misses +system.cpu.dcache.demand_misses 21119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 21119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 55598500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 568882000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 624480500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 624480500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 91206511 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 164348917 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 164348917 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 164727239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 164727239 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33584.182145 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 29222.907353 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 29567.392333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 29567.392333 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33452.767750 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 29237.909236 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 29569.605568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 29569.605568 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3875 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 662 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 676 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16268 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 16944 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 16944 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 993 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4186 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4186 # number of overall MSHR misses +system.cpu.dcache.writebacks 661 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 671 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16266 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 16937 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 16937 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 991 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3191 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31737500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 113123500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 144861000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 144861000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 31558000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 113135500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 144693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 144693500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31961.228600 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35428.593799 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34606.067845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34606.067845 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31844.601413 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35454.559699 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 11 # number of replacements -system.cpu.l2cache.tagsinuse 4003.203107 # Cycle average of tags in use -system.cpu.l2cache.total_refs 792 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4846 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.163434 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 9 # number of replacements +system.cpu.l2cache.tagsinuse 4001.784111 # Cycle average of tags in use +system.cpu.l2cache.total_refs 795 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4839 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.164290 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3625.567893 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 377.635214 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.110644 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011525 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 719 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 781 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 781 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 3624.039188 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 377.744922 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.110597 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011528 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 722 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 661 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 782 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 782 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4299 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7436 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7436 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 148172000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 108394500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 256566500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 256566500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5024 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3193 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8217 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8217 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.856887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.980583 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.904953 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.904953 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34418.583043 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34619.770042 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34503.294782 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34503.294782 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.demand_misses 7430 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7430 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 147966000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 108412500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 256378500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 256378500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 661 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 3191 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8212 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8212 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.856204 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.981197 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.904774 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.904774 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34418.702024 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34625.519004 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34505.854643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34505.854643 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 4299 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7436 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7436 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 7430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7430 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134317500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98537000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 232854500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 232854500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 134126000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 98548000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 232674000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 232674000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.856887 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980583 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.904953 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.904953 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.348432 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31471.414883 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31314.483593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31314.483593 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.856204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981197 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.904774 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.904774 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.348686 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31474.928138 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index 00bbabd01..9a16b9fb5 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 93d8a8907..9b6003954 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 01:50:03 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 20:29:21 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -13,4 +15,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.100000 -Exiting @ tick 107583551000 because target called exit() +Exiting @ tick 105165052500 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 460dc03fb..e1fef621a 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.107584 # Number of seconds simulated -sim_ticks 107583551000 # Number of ticks simulated +sim_seconds 0.105165 # Number of seconds simulated +sim_ticks 105165052500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75407 # Simulator instruction rate (inst/s) -host_tick_rate 23240692 # Simulator tick rate (ticks/s) -host_mem_usage 266760 # Number of bytes of host memory used -host_seconds 4629.10 # Real time elapsed on the host -sim_insts 349066079 # Number of instructions simulated +host_inst_rate 98655 # Simulator instruction rate (inst/s) +host_tick_rate 29722313 # Simulator tick rate (ticks/s) +host_mem_usage 272452 # Number of bytes of host memory used +host_seconds 3538.25 # Real time elapsed on the host +sim_insts 349066014 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 215167103 # number of cpu cycles simulated +system.cpu.numCycles 210330106 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38866864 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21264408 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3266019 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27927226 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21684401 # Number of BTB hits +system.cpu.BPredUnit.lookups 38627930 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21275864 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3257223 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27645633 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 21400607 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7691210 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 61222 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44512335 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 344276425 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38866864 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 29375611 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80511733 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11473489 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 81944021 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 7694267 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 65033 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 44094135 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 341080803 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38627930 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 29094874 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79585948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11338001 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 78589152 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 42084770 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 964630 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 215054786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.101541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.187737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 41622030 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 918575 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 210218055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.123854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.194738 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 135247820 62.89% 62.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9581431 4.46% 67.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6200382 2.88% 70.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6701216 3.12% 73.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5378029 2.50% 75.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5062390 2.35% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3862872 1.80% 80.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4305787 2.00% 82.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 38714859 18.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131312097 62.46% 62.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9414467 4.48% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6051481 2.88% 69.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6791526 3.23% 73.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5430399 2.58% 75.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4963864 2.36% 78.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3858971 1.84% 79.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4276288 2.03% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 38118962 18.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 215054786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180636 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.600042 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53002613 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76469979 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 73518908 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4049306 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8013980 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7649180 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 72848 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 438661628 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 207176 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8013980 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 61218599 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1131550 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 59029634 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69546972 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16114051 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 422574228 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21742 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 9279237 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 90 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 460656766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2485118171 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1371103048 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1114015123 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568671 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 76088090 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3987530 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4043809 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 51974950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 109318735 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 94590139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14520284 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 31851289 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 397726769 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3866008 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 377532932 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1512344 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 52097300 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 169247595 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 310549 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 215054786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.755520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.897504 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 210218055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.183654 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.621645 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 51714033 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73744287 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 72994348 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3887626 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7877761 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7589058 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 71126 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 434888611 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 197240 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 7877761 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59389931 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1170243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57751426 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69399524 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14629170 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419355645 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21743 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8031956 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 92 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 459021692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2465031741 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1360499222 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1104532519 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384568567 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 74453120 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3990661 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4048076 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 47737584 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 109099510 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93607240 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6092384 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2874940 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 396088689 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3868258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378790544 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2203147 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 48219539 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 157035108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 312812 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 210218055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.801893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.982792 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 81920022 38.09% 38.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36703261 17.07% 55.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 30740641 14.29% 69.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20223146 9.40% 78.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22465672 10.45% 89.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12916056 6.01% 95.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7162460 3.33% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2127001 0.99% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 796527 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82551519 39.27% 39.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35288638 16.79% 56.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24974853 11.88% 67.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18906763 8.99% 76.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21633905 10.29% 87.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15100886 7.18% 94.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8378665 3.99% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2542737 1.21% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 840089 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 215054786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 210218055 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2050 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5043 0.04% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 2503 0.02% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 2378 0.02% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 190 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 64374 0.52% 0.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 754 0.01% 0.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 176929 1.43% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7674311 61.94% 63.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4460810 36.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2335 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 47491 0.28% 0.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 2600 0.02% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 370 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 62973 0.37% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 771 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 174751 1.02% 1.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9256583 54.09% 55.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7559769 44.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 130144108 34.47% 34.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147204 0.57% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 13 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6800428 1.80% 36.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8468997 2.24% 39.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3502516 0.93% 40.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1584629 0.42% 40.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21129824 5.60% 46.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7288599 1.93% 47.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7314719 1.94% 49.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102477963 27.14% 77.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 86498646 22.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 129785467 34.26% 34.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147242 0.57% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 19 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6801299 1.80% 36.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8678326 2.29% 38.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3497449 0.92% 39.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1584673 0.42% 40.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21181771 5.59% 45.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7250646 1.91% 47.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7280640 1.92% 49.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103263582 27.26% 76.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 87144142 23.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 377532932 # Type of FU issued -system.cpu.iq.rate 1.754603 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12389345 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.032817 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 734704408 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 318594849 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250322854 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249317931 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 135263376 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118611889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262229500 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 127692777 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5202175 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378790544 # Type of FU issued +system.cpu.iq.rate 1.800934 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17112689 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.045177 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 735684674 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 312839753 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 251076312 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 251430305 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 135519502 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118553768 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266787824 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129115409 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5590978 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14669725 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2212 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 168200 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12214299 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14450513 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33283 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 183129 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11231413 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 529 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 279 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8013980 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 40240 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 528 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 401640096 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2868954 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 109318735 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 94590139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3854778 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 56 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 263 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 168200 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3197943 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 311714 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3509657 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 371554186 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101007931 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5978746 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7877761 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19485 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 400004247 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2635197 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 109099510 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93607240 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3857036 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 197 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 183129 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3190070 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 310107 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3500177 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 372762431 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101699346 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6028113 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 47319 # number of nop insts executed -system.cpu.iew.exec_refs 186146804 # number of memory reference insts executed -system.cpu.iew.exec_branches 32387035 # Number of branches executed -system.cpu.iew.exec_stores 85138873 # Number of stores executed -system.cpu.iew.exec_rate 1.726817 # Inst execution rate -system.cpu.iew.wb_sent 369518278 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368934743 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175105740 # num instructions producing a value -system.cpu.iew.wb_consumers 344287199 # num instructions consuming a value +system.cpu.iew.exec_nop 47300 # number of nop insts executed +system.cpu.iew.exec_refs 187402554 # number of memory reference insts executed +system.cpu.iew.exec_branches 32194166 # Number of branches executed +system.cpu.iew.exec_stores 85703208 # Number of stores executed +system.cpu.iew.exec_rate 1.772273 # Inst execution rate +system.cpu.iew.wb_sent 370566710 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 369630080 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175670846 # num instructions producing a value +system.cpu.iew.wb_consumers 345667025 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.714643 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508604 # average fanout of values written-back +system.cpu.iew.wb_rate 1.757381 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.508208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 349066691 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 52570633 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555459 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3235349 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 207040807 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.685980 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.257361 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 349066626 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 50932905 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3555446 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3228207 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 202340295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.725146 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.308674 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88545688 42.77% 42.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 46881849 22.64% 65.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18621860 8.99% 74.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16226218 7.84% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 12168634 5.88% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6395519 3.09% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3322513 1.60% 92.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3352949 1.62% 94.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11525577 5.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 90698081 44.82% 44.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 39477240 19.51% 64.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17960460 8.88% 73.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13374711 6.61% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 15019988 7.42% 87.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7480519 3.70% 90.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3574486 1.77% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3423610 1.69% 94.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11331200 5.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 207040807 # Number of insts commited each cycle -system.cpu.commit.count 349066691 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 202340295 # Number of insts commited each cycle +system.cpu.commit.count 349066626 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024849 # Number of memory references committed -system.cpu.commit.loads 94649009 # Number of loads committed +system.cpu.commit.refs 177024823 # Number of memory references committed +system.cpu.commit.loads 94648996 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521888 # Number of branches committed +system.cpu.commit.branches 30521875 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279585965 # Number of committed integer instructions. +system.cpu.commit.int_insts 279585913 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11525577 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11331200 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 597150031 # The number of ROB reads -system.cpu.rob.rob_writes 811292092 # The number of ROB writes -system.cpu.timesIdled 2574 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 112317 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 349066079 # Number of Instructions Simulated -system.cpu.committedInsts_total 349066079 # Number of Instructions Simulated -system.cpu.cpi 0.616408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.616408 # CPI: Total CPI of All Threads -system.cpu.ipc 1.622302 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.622302 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1772094610 # number of integer regfile reads -system.cpu.int_regfile_writes 234878865 # number of integer regfile writes -system.cpu.fp_regfile_reads 189976866 # number of floating regfile reads -system.cpu.fp_regfile_writes 134506188 # number of floating regfile writes -system.cpu.misc_regfile_reads 1008752840 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422211 # number of misc regfile writes -system.cpu.icache.replacements 14169 # number of replacements -system.cpu.icache.tagsinuse 1843.995192 # Cycle average of tags in use -system.cpu.icache.total_refs 42068048 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16047 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2621.552190 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 591006103 # The number of ROB reads +system.cpu.rob.rob_writes 807880090 # The number of ROB writes +system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 112051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 349066014 # Number of Instructions Simulated +system.cpu.committedInsts_total 349066014 # Number of Instructions Simulated +system.cpu.cpi 0.602551 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.602551 # CPI: Total CPI of All Threads +system.cpu.ipc 1.659610 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.659610 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1778945060 # number of integer regfile reads +system.cpu.int_regfile_writes 235524211 # number of integer regfile writes +system.cpu.fp_regfile_reads 190068131 # number of floating regfile reads +system.cpu.fp_regfile_writes 134456133 # number of floating regfile writes +system.cpu.misc_regfile_reads 1007398689 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422185 # number of misc regfile writes +system.cpu.icache.replacements 14113 # number of replacements +system.cpu.icache.tagsinuse 1843.325990 # Cycle average of tags in use +system.cpu.icache.total_refs 41605379 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15990 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2601.962414 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1843.995192 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.900388 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 42068048 # number of ReadReq hits -system.cpu.icache.demand_hits 42068048 # number of demand (read+write) hits -system.cpu.icache.overall_hits 42068048 # number of overall hits -system.cpu.icache.ReadReq_misses 16722 # number of ReadReq misses -system.cpu.icache.demand_misses 16722 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 202514000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 202514000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 202514000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 42084770 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 42084770 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 42084770 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000397 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000397 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000397 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12110.632699 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12110.632699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12110.632699 # average overall miss latency +system.cpu.icache.occ_blocks::0 1843.325990 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.900062 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 41605379 # number of ReadReq hits +system.cpu.icache.demand_hits 41605379 # number of demand (read+write) hits +system.cpu.icache.overall_hits 41605379 # number of overall hits +system.cpu.icache.ReadReq_misses 16651 # number of ReadReq misses +system.cpu.icache.demand_misses 16651 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16651 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 201600500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 201600500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 201600500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 41622030 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 41622030 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 41622030 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000400 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000400 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000400 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12107.410966 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12107.410966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12107.410966 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,142 +353,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 670 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 670 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 670 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 16052 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 16052 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 16052 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 658 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 658 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 658 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 15993 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 15993 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 15993 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 136437000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 136437000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 136437000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 136019500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 136019500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 136019500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000381 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000381 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000381 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8499.688512 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8499.688512 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8499.688512 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8504.939661 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8504.939661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8504.939661 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1411 # number of replacements -system.cpu.dcache.tagsinuse 3103.063494 # Cycle average of tags in use -system.cpu.dcache.total_refs 177743721 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4602 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38623.146675 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1412 # number of replacements +system.cpu.dcache.tagsinuse 3102.801650 # Cycle average of tags in use +system.cpu.dcache.total_refs 177884115 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4603 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38645.256355 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3103.063494 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.757584 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 95687864 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 82033242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 11477 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11123 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 177721106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 177721106 # number of overall hits -system.cpu.dcache.ReadReq_misses 3405 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19452 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 3102.801650 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.757520 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 95828379 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 82033251 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 11362 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 11110 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 177861630 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 177861630 # number of overall hits +system.cpu.dcache.ReadReq_misses 3434 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19443 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 22857 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 22857 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 112607000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 646340500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 22877 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 22877 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 113492500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 646306000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 758947500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 758947500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 95691269 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 759798500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 759798500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 95831813 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11479 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11123 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 177743963 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 177743963 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 11364 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 11110 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 177884507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 177884507 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000174 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33071.071953 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33227.457331 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33049.650553 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33241.063622 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33204.160651 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33204.160651 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33212.331162 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33212.331162 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 306500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27863.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1029 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1641 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16609 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 1031 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1669 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16602 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 18250 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 18250 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 2843 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4607 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4607 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 18271 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 18271 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1765 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2841 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4606 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4606 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 53753000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 100987000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 154740000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 154740000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 53909000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 100913500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 154822500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 154822500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30472.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35521.280338 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33588.018233 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33588.018233 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30543.342776 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35520.415347 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33613.221884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33613.221884 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 61 # number of replacements -system.cpu.l2cache.tagsinuse 3912.978440 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13386 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5372 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.491809 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 60 # number of replacements +system.cpu.l2cache.tagsinuse 3910.737339 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13339 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5367 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.485374 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3537.285650 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 375.692790 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107949 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011465 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 13302 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1029 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 3534.138059 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 376.599280 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.107853 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011493 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 13255 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1031 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 18 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 13320 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 13320 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4505 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 5 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits 13273 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 13273 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4498 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses 2821 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7326 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7326 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 154534500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 97281500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 251816000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 251816000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 17807 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1029 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 7319 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7319 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 154344500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 97273500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 251618000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 251618000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 17753 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1031 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 2839 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 20646 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 20646 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.252990 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 20592 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 20592 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.253366 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.993660 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.354839 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.354839 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34302.885683 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34484.757178 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34372.918373 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34372.918373 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.355429 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.355429 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34314.028457 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34481.921305 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34378.740265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34378.740265 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,28 +501,28 @@ system.cpu.l2cache.writebacks 0 # nu system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4450 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 4443 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 2821 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7271 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7271 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 7264 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7264 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 138648500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 155000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88253500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 226902000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 226902000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 138429500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88249000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 226678500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 226678500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249902 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250268 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993660 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.352175 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.352175 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.966292 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.352758 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.352758 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.763448 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31284.473591 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.436529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.436529 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31282.878412 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.740639 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.740639 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 19cfbefe1..dafa0fb4e 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 3c76f760a..fd41e0859 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 18:12:11 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 14:48:53 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1385,4 +1387,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 643295961000 because target called exit() +Exiting @ tick 643202937500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 75c67bd68..4a7021e39 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.643296 # Number of seconds simulated -sim_ticks 643295961000 # Number of ticks simulated +sim_seconds 0.643203 # Number of seconds simulated +sim_ticks 643202937500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85106 # Simulator instruction rate (inst/s) -host_tick_rate 30031356 # Simulator tick rate (ticks/s) -host_mem_usage 253300 # Number of bytes of host memory used -host_seconds 21420.81 # Real time elapsed on the host +host_inst_rate 118321 # Simulator instruction rate (inst/s) +host_tick_rate 41745715 # Simulator tick rate (ticks/s) +host_mem_usage 258992 # Number of bytes of host memory used +host_seconds 15407.64 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 519970160 # DTB read hits -system.cpu.dtb.read_misses 661937 # DTB read misses +system.cpu.dtb.read_hits 521221532 # DTB read hits +system.cpu.dtb.read_misses 658922 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 520632097 # DTB read accesses -system.cpu.dtb.write_hits 283803087 # DTB write hits -system.cpu.dtb.write_misses 53073 # DTB write misses +system.cpu.dtb.read_accesses 521880454 # DTB read accesses +system.cpu.dtb.write_hits 283840599 # DTB write hits +system.cpu.dtb.write_misses 53844 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283856160 # DTB write accesses -system.cpu.dtb.data_hits 803773247 # DTB hits -system.cpu.dtb.data_misses 715010 # DTB misses +system.cpu.dtb.write_accesses 283894443 # DTB write accesses +system.cpu.dtb.data_hits 805062131 # DTB hits +system.cpu.dtb.data_misses 712766 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 804488257 # DTB accesses -system.cpu.itb.fetch_hits 398201591 # ITB hits -system.cpu.itb.fetch_misses 218 # ITB misses +system.cpu.dtb.data_accesses 805774897 # DTB accesses +system.cpu.itb.fetch_hits 397823764 # ITB hits +system.cpu.itb.fetch_misses 725 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398201809 # ITB accesses +system.cpu.itb.fetch_accesses 397824489 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,105 +41,105 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1286591923 # number of cpu cycles simulated +system.cpu.numCycles 1286405876 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 402332344 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 266882286 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 28927707 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 333469369 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 271602812 # Number of BTB hits +system.cpu.BPredUnit.lookups 405275257 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 268833866 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 28893642 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 333881027 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 271480389 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 61007476 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1110 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 415001255 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3352758055 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402332344 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 332610288 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 645375042 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 165723588 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89718349 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 4131 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398201591 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11171919 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1286459621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.606190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.132201 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 61000600 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7280 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 414544439 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3356501340 # Number of instructions fetch has processed +system.cpu.fetch.Branches 405275257 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 332480989 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 645561828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 165819576 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89727975 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 144 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8688 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 397823764 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11262885 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1286279412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.609465 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137305 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 641084579 49.83% 49.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57052665 4.43% 54.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45174311 3.51% 57.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 74426993 5.79% 63.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134875527 10.48% 74.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43375843 3.37% 77.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44931784 3.49% 80.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8199590 0.64% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 237338329 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 640717584 49.81% 49.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 58299040 4.53% 54.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45001912 3.50% 57.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 73771739 5.74% 63.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 133047831 10.34% 73.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 43938688 3.42% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 44398585 3.45% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8225279 0.64% 81.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 238878754 18.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1286459621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.312712 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.605922 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 450770421 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 71474392 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 619091022 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8775043 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 136348743 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 30660300 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12096 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3254572128 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 45923 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 136348743 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 481111559 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 28021350 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 24247 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 596178127 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 44775595 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3152541087 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 298 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750385 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 37569615 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2105877603 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3700324633 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3588590949 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 111733684 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1286279412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315045 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.609209 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 450708217 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 71469346 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 618883502 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8794467 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 136423880 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31952374 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12567 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3256988723 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46034 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 136423880 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 480780652 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 28986921 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25443 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 596262671 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43799845 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3155534506 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 361 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 750713 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 36610303 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2106671791 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3701604314 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3589409458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 112194856 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 720908533 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2940 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 124038053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 733381291 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 346041020 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 96533451 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 26209909 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2644326551 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2155830788 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 16155123 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 820898525 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 783895996 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1286459621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.675786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.770072 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 721702721 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4177 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 80 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 124087461 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 734648354 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 345535584 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 65345430 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8881163 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2648024906 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2157432904 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17936053 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 824509507 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 785295716 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 34 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1286279412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.677266 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.768750 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 467272561 36.32% 36.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 226031192 17.57% 53.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 245053970 19.05% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131827206 10.25% 83.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 102136676 7.94% 91.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 70412736 5.47% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 25404830 1.97% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15392926 1.20% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2927524 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 465105327 36.16% 36.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 230071053 17.89% 54.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 242758793 18.87% 72.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 128578664 10.00% 82.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 105900340 8.23% 91.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 71932968 5.59% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 23608439 1.84% 98.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15399185 1.20% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2924643 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1286459621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1286279412 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 17442 0.06% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 19331 0.06% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available @@ -168,119 +168,119 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21373822 75.29% 75.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 6999070 24.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21353871 65.69% 65.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11133961 34.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1238197742 57.43% 57.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16606 0.00% 57.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27850913 1.29% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 584891416 27.13% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 289412021 13.42% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1239877099 57.47% 57.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16703 0.00% 57.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27850919 1.29% 58.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 584763483 27.10% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 289462610 13.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2155830788 # Type of FU issued -system.cpu.iq.rate 1.675613 # Inst issue rate -system.cpu.iq.fu_busy_cnt 28390334 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013169 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5494230331 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3387151672 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990359564 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 148436323 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78075979 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72618245 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2108598639 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 75619731 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67436970 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2157432904 # Type of FU issued +system.cpu.iq.rate 1.677101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 32507163 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015068 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5503111685 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3393642997 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1992487598 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 148476751 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 78968549 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72622879 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2114296007 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 75641308 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 68640915 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 222311265 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1810 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3927 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 135246124 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 223578328 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1131278 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 78241 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 134740688 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5766 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 4435 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 136348743 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3855288 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 208511 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3007924408 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2746136 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 733381291 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 346041020 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131081 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4887 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3927 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 30747465 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 896385 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 31643850 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2065446597 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 520632193 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90384191 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 136423880 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3817759 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 203214 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3011242942 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2752328 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 734648354 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 345535584 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 131783 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4925 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 78241 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 30717052 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 905851 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 31622903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2068736315 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 521880619 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 88696589 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363597781 # number of nop insts executed -system.cpu.iew.exec_refs 804489057 # number of memory reference insts executed -system.cpu.iew.exec_branches 279489807 # Number of branches executed -system.cpu.iew.exec_stores 283856864 # Number of stores executed -system.cpu.iew.exec_rate 1.605363 # Inst execution rate -system.cpu.iew.wb_sent 2064951145 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2062977809 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1176793581 # num instructions producing a value -system.cpu.iew.wb_consumers 1743269600 # num instructions consuming a value +system.cpu.iew.exec_nop 363217963 # number of nop insts executed +system.cpu.iew.exec_refs 805775787 # number of memory reference insts executed +system.cpu.iew.exec_branches 280804576 # Number of branches executed +system.cpu.iew.exec_stores 283895168 # Number of stores executed +system.cpu.iew.exec_rate 1.608152 # Inst execution rate +system.cpu.iew.wb_sent 2067101811 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2065110477 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1176977005 # num instructions producing a value +system.cpu.iew.wb_consumers 1742514296 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.603444 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675050 # average fanout of values written-back +system.cpu.iew.wb_rate 1.605334 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675448 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 982229195 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 985541279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 28915749 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1150110878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.746777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513451 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 28881185 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1149855532 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.747165 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.514043 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 542947178 47.21% 47.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 216893273 18.86% 66.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119702794 10.41% 76.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 61150627 5.32% 81.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44132968 3.84% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24929340 2.17% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19288154 1.68% 89.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16202986 1.41% 90.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 104863558 9.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 542912132 47.22% 47.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 216611408 18.84% 66.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119775528 10.42% 76.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 61140403 5.32% 81.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 44127401 3.84% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24962604 2.17% 87.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19277030 1.68% 89.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15973081 1.39% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 105075945 9.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1150110878 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1149855532 # Number of insts commited each cycle system.cpu.commit.count 2008987604 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 721864922 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 104863558 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 105075945 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4030827709 # The number of ROB reads -system.cpu.rob.rob_writes 6118968242 # The number of ROB writes -system.cpu.timesIdled 3723 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 132302 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4033672060 # The number of ROB reads +system.cpu.rob.rob_writes 6125668302 # The number of ROB writes +system.cpu.timesIdled 3523 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 126464 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.705739 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.705739 # CPI: Total CPI of All Threads -system.cpu.ipc 1.416955 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.416955 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2630015105 # number of integer regfile reads -system.cpu.int_regfile_writes 1492715832 # number of integer regfile writes -system.cpu.fp_regfile_reads 77822469 # number of floating regfile reads -system.cpu.fp_regfile_writes 52813999 # number of floating regfile writes +system.cpu.cpi 0.705636 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.705636 # CPI: Total CPI of All Threads +system.cpu.ipc 1.417160 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.417160 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2632175047 # number of integer regfile reads +system.cpu.int_regfile_writes 1493512495 # number of integer regfile writes +system.cpu.fp_regfile_reads 77824339 # number of floating regfile reads +system.cpu.fp_regfile_writes 52831274 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8239 # number of replacements -system.cpu.icache.tagsinuse 1650.299578 # Cycle average of tags in use -system.cpu.icache.total_refs 398190502 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 40035.240499 # Average number of references to valid blocks. +system.cpu.icache.replacements 8247 # number of replacements +system.cpu.icache.tagsinuse 1649.560479 # Cycle average of tags in use +system.cpu.icache.total_refs 397812655 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9954 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39965.104983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1650.299578 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.805810 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 398190502 # number of ReadReq hits -system.cpu.icache.demand_hits 398190502 # number of demand (read+write) hits -system.cpu.icache.overall_hits 398190502 # number of overall hits -system.cpu.icache.ReadReq_misses 11089 # number of ReadReq misses -system.cpu.icache.demand_misses 11089 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11089 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 182267000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 182267000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 182267000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 398201591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 398201591 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 398201591 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1649.560479 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.805449 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 397812655 # number of ReadReq hits +system.cpu.icache.demand_hits 397812655 # number of demand (read+write) hits +system.cpu.icache.overall_hits 397812655 # number of overall hits +system.cpu.icache.ReadReq_misses 11109 # number of ReadReq misses +system.cpu.icache.demand_misses 11109 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11109 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 182768000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 182768000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 182768000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 397823764 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 397823764 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 397823764 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 16436.739111 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 16436.739111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 16436.739111 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 16452.245927 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 16452.245927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 16452.245927 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1142 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1142 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1142 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9947 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9947 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9947 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1154 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1154 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1154 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 9955 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 9955 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 9955 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 119594000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 119594000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 119594000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 119824500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 119824500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 119824500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12023.122550 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12023.122550 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12023.122550 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12036.614766 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12036.614766 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12036.614766 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1526949 # number of replacements -system.cpu.dcache.tagsinuse 4095.114036 # Cycle average of tags in use -system.cpu.dcache.total_refs 660843701 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531045 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 431.629182 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1527589 # number of replacements +system.cpu.dcache.tagsinuse 4095.113908 # Cycle average of tags in use +system.cpu.dcache.total_refs 660891120 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531685 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 431.479789 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 255450000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.114036 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4095.113908 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 450600382 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 210243310 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 660843692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 660843692 # number of overall hits -system.cpu.dcache.ReadReq_misses 1927019 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 551586 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits 450647870 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 210243240 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 660891110 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 660891110 # number of overall hits +system.cpu.dcache.ReadReq_misses 1928288 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 551656 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2478605 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2478605 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 71403632500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20879059491 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2479944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2479944 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 71428228500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 20878086491 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 92282691991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 92282691991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 452527401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 92306314991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 92306314991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 452576158 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 663322297 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 663322297 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004258 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 663371054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 663371054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004261 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.002617 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.003737 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003737 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37053.932784 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37852.772715 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.003738 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003738 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 37042.303069 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37846.205771 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 29500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37231.705734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37231.705734 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 37221.128780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 37221.128780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -410,74 +410,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429 system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107353 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 467618 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 479943 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 107322 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 468211 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 480049 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 947561 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 947561 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1459401 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 71643 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits 948260 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 948260 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1460077 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 71607 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1531044 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1531044 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1531684 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1531684 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 49913659500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2493461000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 49926913500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2493150500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52407120500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52407120500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52420064000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52420064000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003225 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003226 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.090909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002308 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002308 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34201.469987 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34803.972475 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.083333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.002309 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002309 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34194.712676 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34817.133800 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34229.663223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34229.663223 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34223.811178 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34223.811178 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480560 # number of replacements -system.cpu.l2cache.tagsinuse 31934.298723 # Cycle average of tags in use -system.cpu.l2cache.total_refs 62999 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513247 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.041632 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480632 # number of replacements +system.cpu.l2cache.tagsinuse 31936.096319 # Cycle average of tags in use +system.cpu.l2cache.total_refs 63580 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513319 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.042014 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28867.873331 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3066.425392 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.880978 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.093580 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 55386 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107353 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 4785 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 60171 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 60171 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1413963 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 66858 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1480821 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1480821 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48486744500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2349128500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50835873000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50835873000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1469349 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107353 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 71643 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1540992 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1540992 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.962306 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.933211 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.960953 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.960953 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34291.381387 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.086931 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34329.519233 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34329.519233 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 28877.574420 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3058.521899 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881274 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.093339 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 55956 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 107322 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 4752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 60708 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 60708 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1414077 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 66855 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 1480932 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1480932 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48498416000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2349022500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50847438500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50847438500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1470033 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 107322 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 71607 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1541640 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1541640 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.961936 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.933638 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.960621 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.960621 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34296.870680 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.078079 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34334.755748 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34334.755748 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -489,24 +489,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 66898 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1413963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66858 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1480821 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1480821 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1414077 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1480932 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1480932 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43834024500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147795500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 45981820000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 45981820000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 43837572000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147697500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 45985269500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 45985269500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962306 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933211 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.960953 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.960953 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.828522 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.734512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.572067 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.572067 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961936 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933638 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.960621 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.960621 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.838002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.710194 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.573941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.573941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 263380878..af0d319dc 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index 9abe7d930..b7bd4cae8 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 02:25:07 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 18 2011 17:30:35 +gem5 started Aug 18 2011 18:30:12 +gem5 executing on nadc-0330 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1385,4 +1387,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 774804895000 because target called exit() +Exiting @ tick 721574387500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e5f49a16a..2aa37fbb0 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.774805 # Number of seconds simulated -sim_ticks 774804895000 # Number of ticks simulated +sim_seconds 0.721574 # Number of seconds simulated +sim_ticks 721574387500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78044 # Simulator instruction rate (inst/s) -host_tick_rate 32073308 # Simulator tick rate (ticks/s) -host_mem_usage 264164 # Number of bytes of host memory used -host_seconds 24157.31 # Real time elapsed on the host -sim_insts 1885341976 # Number of instructions simulated +host_inst_rate 93472 # Simulator instruction rate (inst/s) +host_tick_rate 35774469 # Simulator tick rate (ticks/s) +host_mem_usage 269932 # Number of bytes of host memory used +host_seconds 20170.09 # Real time elapsed on the host +sim_insts 1885333781 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1549609791 # number of cpu cycles simulated +system.cpu.numCycles 1443148776 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 528720404 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 405201149 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 32899214 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 420084737 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 301658852 # Number of BTB hits +system.cpu.BPredUnit.lookups 514101790 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 393960342 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 32849417 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 411992130 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 292369997 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 69231604 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2844202 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 441882986 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2652302812 # Number of instructions fetch has processed -system.cpu.fetch.Branches 528720404 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 370890456 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718660047 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 237987325 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 141427708 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5060 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 410572411 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11240316 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1497398135 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.463229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.115993 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 61143344 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2847666 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 422838137 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2603354590 # Number of instructions fetch has processed +system.cpu.fetch.Branches 514101790 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 353513341 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 695385496 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 212683081 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 100667444 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 34744 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 396353337 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 13400662 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1391803250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587957 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156576 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 778775531 52.01% 52.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 50816086 3.39% 55.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117376582 7.84% 63.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 64268768 4.29% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 98483271 6.58% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 55328075 3.69% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 42969714 2.87% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33373173 2.23% 82.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 256006935 17.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 696457133 50.04% 50.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48140413 3.46% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 109472309 7.87% 61.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 63203054 4.54% 65.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 93420590 6.71% 72.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 55467471 3.99% 76.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38010894 2.73% 79.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 34903580 2.51% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 252727806 18.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1497398135 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.341196 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.711594 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 490492895 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 110799689 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 685856855 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14839948 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 195408748 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 70149015 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13528 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3592611687 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 23480 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 195408748 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 532538328 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 41527455 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3530778 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 657203589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 67189237 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3464582939 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 83 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4053070 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 53839616 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3447136427 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16419760198 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15673686759 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 746073439 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993166703 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1453969719 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 280977 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 281142 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 192553677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1121958053 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 549497958 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 186141114 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 133678303 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3274000051 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 286918 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2696986204 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 15942313 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1388610041 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3416788899 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 75361 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1497398135 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.801115 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.821957 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1391803250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.356236 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.803941 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 467512838 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 82010941 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 659587023 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9830183 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 172862265 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 71310699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13247 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3482203473 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 23181 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 172862265 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 507308890 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29017787 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3569068 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 628144166 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50901074 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3355358425 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4098898 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 41311851 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3338398637 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 15926092867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15179476932 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 746615935 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153591 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1345245041 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 293826 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 289544 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 148458476 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1060445315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 528215229 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 34855006 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 42545066 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3129553839 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 287167 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2641710303 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18698476 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1243985610 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3101856113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 77249 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1391803250 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.898049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.895078 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 520879280 34.79% 34.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 250662816 16.74% 51.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 249981874 16.69% 68.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 183430350 12.25% 80.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 145558199 9.72% 90.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 90126006 6.02% 96.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37572713 2.51% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15725690 1.05% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3461207 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 496637821 35.68% 35.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 187318392 13.46% 49.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216683253 15.57% 64.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 183278078 13.17% 77.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 154759947 11.12% 89.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 88115850 6.33% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48435610 3.48% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11635919 0.84% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4938380 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1497398135 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1391803250 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 466158 0.65% 0.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23952 0.03% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 43631235 60.82% 61.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 27621714 38.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2241949 2.46% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23931 0.03% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55591183 61.06% 63.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 33183599 36.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1249934524 46.35% 46.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 15347152 0.57% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 8678 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.25% 47.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502225 0.20% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24546538 0.91% 48.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 926115609 34.34% 82.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 467279715 17.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1209438891 45.78% 45.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11231174 0.43% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 6786 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876480 0.26% 46.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5505922 0.21% 46.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24487735 0.93% 47.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 908321415 34.38% 82.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 474466611 17.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2696986204 # Type of FU issued -system.cpu.iq.rate 1.740429 # Inst issue rate -system.cpu.iq.fu_busy_cnt 71743059 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.026601 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6850131362 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4543112182 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2499696981 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128924553 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123913779 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57056788 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2702891798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 65837465 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 68903819 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2641710303 # Type of FU issued +system.cpu.iq.rate 1.830518 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91040662 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034463 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6653435449 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4251253883 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2425638071 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 131527545 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 124012557 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 57076576 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2665613044 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 67137921 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 72083065 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 490567545 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 34373 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5468301 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 272499336 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 429056446 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 91786 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 2776714 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 251218246 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 85 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 88 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 195408748 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16548936 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1477418 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3274352719 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7542599 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1121958053 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 549497958 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 274197 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1475285 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 266 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5468301 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 35960500 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8891555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 44852055 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2594017984 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 869263464 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 102968220 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 172862265 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16375195 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1473977 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3129909418 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 11871497 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1060445315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 528215229 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 275665 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1470985 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 210 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 2776714 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 34610253 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8646611 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 43256864 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2550234981 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 850160020 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 91475322 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 65750 # number of nop insts executed -system.cpu.iew.exec_refs 1311874105 # number of memory reference insts executed -system.cpu.iew.exec_branches 351627111 # Number of branches executed -system.cpu.iew.exec_stores 442610641 # Number of stores executed -system.cpu.iew.exec_rate 1.673981 # Inst execution rate -system.cpu.iew.wb_sent 2572992074 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2556753769 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1518871802 # num instructions producing a value -system.cpu.iew.wb_consumers 2751373427 # num instructions consuming a value +system.cpu.iew.exec_nop 68412 # number of nop insts executed +system.cpu.iew.exec_refs 1303401841 # number of memory reference insts executed +system.cpu.iew.exec_branches 346693404 # Number of branches executed +system.cpu.iew.exec_stores 453241821 # Number of stores executed +system.cpu.iew.exec_rate 1.767132 # Inst execution rate +system.cpu.iew.wb_sent 2511392174 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2482714647 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457352486 # num instructions producing a value +system.cpu.iew.wb_consumers 2693773506 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.649934 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552041 # average fanout of values written-back +system.cpu.iew.wb_rate 1.720346 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.541008 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1885352992 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1388961384 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 211557 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 38421689 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1301989389 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.448056 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.137383 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1885344797 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1244525975 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 209918 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 38374226 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1218940987 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.546707 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.221520 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 590521474 45.36% 45.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 345830520 26.56% 71.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 113709906 8.73% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 73638275 5.66% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 53779351 4.13% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24377206 1.87% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19730682 1.52% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 7415491 0.57% 94.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 72986484 5.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 542456201 44.50% 44.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 304987693 25.02% 69.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110181944 9.04% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79585029 6.53% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 53872031 4.42% 89.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24566271 2.02% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17102531 1.40% 92.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9210832 0.76% 93.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76978455 6.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1301989389 # Number of insts commited each cycle -system.cpu.commit.count 1885352992 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 1218940987 # Number of insts commited each cycle +system.cpu.commit.count 1885344797 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908389129 # Number of memory references committed -system.cpu.commit.loads 631390507 # Number of loads committed +system.cpu.commit.refs 908385851 # Number of memory references committed +system.cpu.commit.loads 631388868 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291351870 # Number of branches committed +system.cpu.commit.branches 291350231 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653712175 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705619 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 72986484 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76978455 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4503298936 # The number of ROB reads -system.cpu.rob.rob_writes 6744049642 # The number of ROB writes -system.cpu.timesIdled 1345030 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52211656 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1885341976 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885341976 # Number of Instructions Simulated -system.cpu.cpi 0.821925 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.821925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.216656 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.216656 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12929172445 # number of integer regfile reads -system.cpu.int_regfile_writes 2454347411 # number of integer regfile writes -system.cpu.fp_regfile_reads 68793732 # number of floating regfile reads -system.cpu.fp_regfile_writes 50170083 # number of floating regfile writes -system.cpu.misc_regfile_reads 4128169598 # number of misc regfile reads -system.cpu.misc_regfile_writes 13779552 # number of misc regfile writes -system.cpu.icache.replacements 25756 # number of replacements -system.cpu.icache.tagsinuse 1635.277334 # Cycle average of tags in use -system.cpu.icache.total_refs 410544180 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 27432 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14965.885827 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4271814959 # The number of ROB reads +system.cpu.rob.rob_writes 6432618886 # The number of ROB writes +system.cpu.timesIdled 1340911 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51345526 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1885333781 # Number of Instructions Simulated +system.cpu.committedInsts_total 1885333781 # Number of Instructions Simulated +system.cpu.cpi 0.765461 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.765461 # CPI: Total CPI of All Threads +system.cpu.ipc 1.306403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.306403 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12650608214 # number of integer regfile reads +system.cpu.int_regfile_writes 2377451435 # number of integer regfile writes +system.cpu.fp_regfile_reads 68801235 # number of floating regfile reads +system.cpu.fp_regfile_writes 50191358 # number of floating regfile writes +system.cpu.misc_regfile_reads 4051722338 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776274 # number of misc regfile writes +system.cpu.icache.replacements 27265 # number of replacements +system.cpu.icache.tagsinuse 1631.022811 # Cycle average of tags in use +system.cpu.icache.total_refs 396319184 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 28937 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13695.931990 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1635.277334 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.798475 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 410544181 # number of ReadReq hits -system.cpu.icache.demand_hits 410544181 # number of demand (read+write) hits -system.cpu.icache.overall_hits 410544181 # number of overall hits -system.cpu.icache.ReadReq_misses 28230 # number of ReadReq misses -system.cpu.icache.demand_misses 28230 # number of demand (read+write) misses -system.cpu.icache.overall_misses 28230 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 268370000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 268370000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 268370000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 410572411 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 410572411 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 410572411 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000069 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000069 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000069 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9506.553312 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9506.553312 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9506.553312 # average overall miss latency +system.cpu.icache.occ_blocks::0 1631.022811 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.796398 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 396319190 # number of ReadReq hits +system.cpu.icache.demand_hits 396319190 # number of demand (read+write) hits +system.cpu.icache.overall_hits 396319190 # number of overall hits +system.cpu.icache.ReadReq_misses 34147 # number of ReadReq misses +system.cpu.icache.demand_misses 34147 # number of demand (read+write) misses +system.cpu.icache.overall_misses 34147 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 302756000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 302756000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 302756000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 396353337 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 396353337 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 396353337 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000086 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000086 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000086 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 8866.254722 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 8866.254722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 8866.254722 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,67 +354,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 792 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 792 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 792 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 27438 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 27438 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 27438 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 858 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 858 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 858 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 33289 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 33289 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 33289 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 164813000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 164813000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 164813000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 180196000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 180196000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 180196000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000067 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000067 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000067 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6006.742474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6006.742474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6006.742474 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5413.079396 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5413.079396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5413.079396 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1531422 # number of replacements -system.cpu.dcache.tagsinuse 4094.889747 # Cycle average of tags in use -system.cpu.dcache.total_refs 1060675603 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1535518 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 690.760775 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1531918 # number of replacements +system.cpu.dcache.tagsinuse 4094.807844 # Cycle average of tags in use +system.cpu.dcache.total_refs 1037036260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1536014 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 675.147661 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 306953000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.889747 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999729 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 784517362 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 276127149 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 17768 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 13310 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 1060644511 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1060644511 # number of overall hits -system.cpu.dcache.ReadReq_misses 1932656 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 808529 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 4094.807844 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999709 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 760874912 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 276118613 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 15353 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 11671 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 1036993525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1036993525 # number of overall hits +system.cpu.dcache.ReadReq_misses 1940591 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 817065 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2741185 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2741185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 69641234000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 28315172500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2757656 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2757656 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 69372468500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28482649500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 97956406500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 97956406500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 786450018 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 97855118000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 97855118000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 762815503 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 17771 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 13310 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1063385696 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1063385696 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002457 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002920 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000169 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.002578 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002578 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 36033.952240 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35020.602229 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 15356 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 11671 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 1039751181 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1039751181 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002544 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.002950 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000195 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.002652 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002652 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35748.114105 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34859.710672 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35735.058560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35735.058560 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35484.889341 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35484.889341 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,74 +423,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106530 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 469858 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 735802 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 106488 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 477280 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 740009 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1205660 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1205660 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1462798 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 72727 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1535525 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1535525 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1217289 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1217289 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1463311 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 77056 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1540367 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1540367 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 50071553500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2361380000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52432933500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52432933500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 50023449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2483285500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52506735000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52506735000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001860 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001444 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001444 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34229.984933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32469.096759 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34146.584067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34146.584067 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001918 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.001481 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001481 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.111367 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32227.023204 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34087.159099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34087.159099 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1479883 # number of replacements -system.cpu.l2cache.tagsinuse 31974.412351 # Cycle average of tags in use -system.cpu.l2cache.total_refs 83096 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512603 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.054936 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480007 # number of replacements +system.cpu.l2cache.tagsinuse 31971.458810 # Cycle average of tags in use +system.cpu.l2cache.total_refs 84947 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512726 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.056155 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 29007.598549 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2966.813802 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.885242 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.090540 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 75017 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106530 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 6638 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 81655 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 81655 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1415213 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 66083 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1481296 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1481296 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48605841000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2279788500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50885629500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50885629500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1490230 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106530 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72721 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1562951 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1562951 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.949661 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908720 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.947756 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.947756 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34345.247676 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.865064 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34352.100796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34352.100796 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 29004.872731 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2966.586079 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.885158 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.090533 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 76859 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 106488 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 6622 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 83481 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 83481 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1415390 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4348 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 1481472 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1481472 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48557740000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2252374000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50810114000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50810114000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1492249 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 106488 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 4352 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 72704 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1564953 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1564953 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.948495 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.999081 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.908918 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.946656 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.946656 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34306.968397 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34084.531340 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34297.046451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34297.046451 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,31 +500,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 24 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 24 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1415189 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66083 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1481272 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1481272 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 26 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 26 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1415364 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4348 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1481446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1481446 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44022928500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048636000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 46071564500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 46071564500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 43973597000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 134788000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048603500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 46022200500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 46022200500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949645 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908720 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.947741 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.947741 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.455259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948477 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999081 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908918 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.946639 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.946639 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31068.754751 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.953347 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.703960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.703960 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.930662 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.729362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.729362 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 7b47004d6..3ed32454b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 50848dbff..f4cba8212 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 19:00:26 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 14:49:49 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 22743377000 because target called exit() +Exiting @ tick 21280925000 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f7387c5fb..3555b3a9e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022743 # Number of seconds simulated -sim_ticks 22743377000 # Number of ticks simulated +sim_seconds 0.021281 # Number of seconds simulated +sim_ticks 21280925000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91653 # Simulator instruction rate (inst/s) -host_tick_rate 26189824 # Simulator tick rate (ticks/s) -host_mem_usage 255808 # Number of bytes of host memory used -host_seconds 868.41 # Real time elapsed on the host +host_inst_rate 145761 # Simulator instruction rate (inst/s) +host_tick_rate 38973060 # Simulator tick rate (ticks/s) +host_mem_usage 261392 # Number of bytes of host memory used +host_seconds 546.04 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 21751129 # DTB read hits -system.cpu.dtb.read_misses 175370 # DTB read misses -system.cpu.dtb.read_acv 31 # DTB read access violations -system.cpu.dtb.read_accesses 21926499 # DTB read accesses -system.cpu.dtb.write_hits 15297508 # DTB write hits -system.cpu.dtb.write_misses 26341 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15323849 # DTB write accesses -system.cpu.dtb.data_hits 37048637 # DTB hits -system.cpu.dtb.data_misses 201711 # DTB misses -system.cpu.dtb.data_acv 37 # DTB access violations -system.cpu.dtb.data_accesses 37250348 # DTB accesses -system.cpu.itb.fetch_hits 14100005 # ITB hits -system.cpu.itb.fetch_misses 36420 # ITB misses +system.cpu.dtb.read_hits 22306086 # DTB read hits +system.cpu.dtb.read_misses 214886 # DTB read misses +system.cpu.dtb.read_acv 39 # DTB read access violations +system.cpu.dtb.read_accesses 22520972 # DTB read accesses +system.cpu.dtb.write_hits 15626167 # DTB write hits +system.cpu.dtb.write_misses 39215 # DTB write misses +system.cpu.dtb.write_acv 8 # DTB write access violations +system.cpu.dtb.write_accesses 15665382 # DTB write accesses +system.cpu.dtb.data_hits 37932253 # DTB hits +system.cpu.dtb.data_misses 254101 # DTB misses +system.cpu.dtb.data_acv 47 # DTB access violations +system.cpu.dtb.data_accesses 38186354 # DTB accesses +system.cpu.itb.fetch_hits 13891710 # ITB hits +system.cpu.itb.fetch_misses 28310 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14136425 # ITB accesses +system.cpu.itb.fetch_accesses 13920020 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 45486755 # number of cpu cycles simulated +system.cpu.numCycles 42561853 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16901328 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10975275 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 456849 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14797141 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8724675 # Number of BTB hits +system.cpu.BPredUnit.lookups 16631874 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10794462 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 464307 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 14557589 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8568490 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 2018610 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 35075 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15142621 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 107619262 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16901328 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10743285 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20909720 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2286025 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6121858 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 13576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 358341 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14100005 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 211722 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44264196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.431294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.090704 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1988710 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 35321 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14916531 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105870429 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16631874 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10557200 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20627655 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2038131 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4875496 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5851 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 284921 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 13891710 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 223928 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42166283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.510784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.107272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23354476 52.76% 52.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2087705 4.72% 57.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1683152 3.80% 61.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2128946 4.81% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3922871 8.86% 74.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1978801 4.47% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 718343 1.62% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1236348 2.79% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7153554 16.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21538628 51.08% 51.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2127742 5.05% 56.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1681102 3.99% 60.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1999349 4.74% 64.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3923245 9.30% 74.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1939114 4.60% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 766205 1.82% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1130528 2.68% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7060370 16.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44264196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.371566 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.365947 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16625814 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5350938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19481362 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1184271 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1621811 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3792639 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98494 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 105768441 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 262977 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1621811 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17249190 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1859026 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 92496 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19962312 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3479361 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104444741 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62263 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3183210 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62854370 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 126007838 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 125513406 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 494432 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42166283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.390769 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.487449 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15993014 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4441023 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19696798 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 677140 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1358308 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3731142 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 99597 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104002025 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 279031 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1358308 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16480266 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2358783 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84134 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19842827 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2041965 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102626564 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 182 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2800 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1928739 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61750639 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123717887 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123241434 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 476453 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10307489 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5394 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5392 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7022840 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23585547 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16625780 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13013966 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10091747 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 92564607 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5349 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 87311286 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89819 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12800874 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8559564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 766 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44264196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.972504 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.848460 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9203758 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5461 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5458 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4160134 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23154536 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16249616 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1221790 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 569270 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90755871 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5414 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88285827 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 101429 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10871074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4987897 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 831 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42166283 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.093754 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.072730 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12024331 27.16% 27.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9739894 22.00% 49.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7505625 16.96% 66.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5587744 12.62% 78.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4605636 10.40% 89.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2526104 5.71% 94.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1401834 3.17% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 651382 1.47% 99.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 221646 0.50% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13277522 31.49% 31.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7349165 17.43% 48.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5870534 13.92% 62.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4909942 11.64% 74.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4829345 11.45% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2472819 5.86% 91.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1859151 4.41% 96.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1153053 2.73% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 444752 1.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44264196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42166283 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 145655 11.21% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 556077 42.81% 54.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 597272 45.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 104351 5.76% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 742075 40.96% 46.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 965203 53.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49414746 56.60% 56.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43477 0.05% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 125010 0.14% 56.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 125425 0.14% 56.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38600 0.04% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22113935 25.33% 82.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15449954 17.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49336133 55.88% 55.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44096 0.05% 55.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 126791 0.14% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 127304 0.14% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38913 0.04% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22760648 25.78% 82.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15851801 17.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 87311286 # Type of FU issued -system.cpu.iq.rate 1.919488 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1299004 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014878 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 219655218 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104890132 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85660866 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 620373 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 492550 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 303658 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 88299901 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 310389 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1470541 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88285827 # Type of FU issued +system.cpu.iq.rate 2.074295 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1811630 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020520 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 220029766 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101198436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86307444 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 621230 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 457830 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 302539 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89786725 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 310732 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1421646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3308909 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2159 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11951 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2012403 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2877898 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4388 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 24438 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1636239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1474 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1319 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 40 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1621811 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 650255 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 46881 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 102207113 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 299211 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23585547 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16625780 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5349 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10530 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7811 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11951 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 297237 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 113949 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 411186 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 86536224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 21928950 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 775062 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1358308 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1393023 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 60290 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100252216 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 329475 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23154536 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16249616 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5414 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42581 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 713 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 24438 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 304612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 116704 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 421316 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87314896 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22523751 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 970931 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9637157 # number of nop insts executed -system.cpu.iew.exec_refs 37253187 # number of memory reference insts executed -system.cpu.iew.exec_branches 15011802 # Number of branches executed -system.cpu.iew.exec_stores 15324237 # Number of stores executed -system.cpu.iew.exec_rate 1.902449 # Inst execution rate -system.cpu.iew.wb_sent 86279934 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85964524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 34688342 # num instructions producing a value -system.cpu.iew.wb_consumers 46291790 # num instructions consuming a value +system.cpu.iew.exec_nop 9490931 # number of nop insts executed +system.cpu.iew.exec_refs 38189606 # number of memory reference insts executed +system.cpu.iew.exec_branches 15067894 # Number of branches executed +system.cpu.iew.exec_stores 15665855 # Number of stores executed +system.cpu.iew.exec_rate 2.051482 # Inst execution rate +system.cpu.iew.wb_sent 87005186 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86609983 # cumulative count of insts written-back +system.cpu.iew.wb_producers 32995140 # num instructions producing a value +system.cpu.iew.wb_consumers 43003754 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.889880 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.749341 # average fanout of values written-back +system.cpu.iew.wb_rate 2.034920 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767262 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11023437 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8883927 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 360580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42642385 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.071663 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.676209 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 366786 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40807975 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.164789 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.804222 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17681432 41.46% 41.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8356070 19.60% 61.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3960782 9.29% 70.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2934126 6.88% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1908842 4.48% 81.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1271711 2.98% 84.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1063495 2.49% 87.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 841649 1.97% 89.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4624278 10.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17689673 43.35% 43.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7101779 17.40% 60.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3525291 8.64% 69.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2171268 5.32% 74.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2044082 5.01% 79.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1229518 3.01% 82.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1144487 2.80% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731349 1.79% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5170528 12.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42642385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40807975 # Number of insts commited each cycle system.cpu.commit.count 88340672 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4624278 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5170528 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 136064874 # The number of ROB reads -system.cpu.rob.rob_writes 200355381 # The number of ROB writes -system.cpu.timesIdled 41664 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1222559 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131544704 # The number of ROB reads +system.cpu.rob.rob_writes 195810643 # The number of ROB writes +system.cpu.timesIdled 15962 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 395570 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.571501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.571501 # CPI: Total CPI of All Threads -system.cpu.ipc 1.749779 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.749779 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 114385631 # number of integer regfile reads -system.cpu.int_regfile_writes 57104236 # number of integer regfile writes -system.cpu.fp_regfile_reads 255197 # number of floating regfile reads -system.cpu.fp_regfile_writes 247532 # number of floating regfile writes -system.cpu.misc_regfile_reads 38059 # number of misc regfile reads +system.cpu.cpi 0.534752 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.534752 # CPI: Total CPI of All Threads +system.cpu.ipc 1.870026 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.870026 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115501345 # number of integer regfile reads +system.cpu.int_regfile_writes 57352944 # number of integer regfile writes +system.cpu.fp_regfile_reads 252582 # number of floating regfile reads +system.cpu.fp_regfile_writes 251221 # number of floating regfile writes +system.cpu.misc_regfile_reads 38138 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 89406 # number of replacements -system.cpu.icache.tagsinuse 1932.641583 # Cycle average of tags in use -system.cpu.icache.total_refs 14004218 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 91454 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 153.128545 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18957437000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1932.641583 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.943673 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 14004218 # number of ReadReq hits -system.cpu.icache.demand_hits 14004218 # number of demand (read+write) hits -system.cpu.icache.overall_hits 14004218 # number of overall hits -system.cpu.icache.ReadReq_misses 95787 # number of ReadReq misses -system.cpu.icache.demand_misses 95787 # number of demand (read+write) misses -system.cpu.icache.overall_misses 95787 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 913804000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 913804000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 913804000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 14100005 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 14100005 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 14100005 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.006793 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.006793 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.006793 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9539.958449 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9539.958449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9539.958449 # average overall miss latency +system.cpu.icache.replacements 88299 # number of replacements +system.cpu.icache.tagsinuse 1927.175283 # Cycle average of tags in use +system.cpu.icache.total_refs 13796878 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 90347 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 152.709863 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17859322000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1927.175283 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.941004 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 13796878 # number of ReadReq hits +system.cpu.icache.demand_hits 13796878 # number of demand (read+write) hits +system.cpu.icache.overall_hits 13796878 # number of overall hits +system.cpu.icache.ReadReq_misses 94832 # number of ReadReq misses +system.cpu.icache.demand_misses 94832 # number of demand (read+write) misses +system.cpu.icache.overall_misses 94832 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 914342000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 914342000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 914342000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 13891710 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 13891710 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 13891710 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.006827 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.006827 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.006827 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 9641.703223 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 9641.703223 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9641.703223 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 4332 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 4332 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 4332 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 91455 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 91455 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 91455 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 4484 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 4484 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 4484 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 90348 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 90348 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 90348 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 543662500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 543662500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 543662500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 542867000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 542867000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 542867000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006486 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006486 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006486 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5944.590236 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5944.590236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5944.590236 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.006504 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.006504 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.006504 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6008.622216 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6008.622216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6008.622216 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201138 # number of replacements -system.cpu.dcache.tagsinuse 4077.454255 # Cycle average of tags in use -system.cpu.dcache.total_refs 33705391 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205234 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 164.229080 # Average number of references to valid blocks. +system.cpu.dcache.replacements 201353 # number of replacements +system.cpu.dcache.tagsinuse 4076.179768 # Cycle average of tags in use +system.cpu.dcache.total_refs 34205173 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205449 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.489849 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 157412000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4077.454255 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995472 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20126386 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13578957 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 48 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 33705343 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 33705343 # number of overall hits -system.cpu.dcache.ReadReq_misses 152658 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1034420 # number of WriteReq misses -system.cpu.dcache.demand_misses 1187078 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1187078 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4522200000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 33957528000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 38479728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 38479728000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20279044 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4076.179768 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995161 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 20626522 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13578601 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 50 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 34205123 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 34205123 # number of overall hits +system.cpu.dcache.ReadReq_misses 256524 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1034776 # number of WriteReq misses +system.cpu.dcache.demand_misses 1291300 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1291300 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8257183000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 33901746500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 42158929500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 42158929500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 20883046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 48 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 34892421 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 34892421 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007528 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.070786 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.034021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.034021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 29623.079039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32827.601941 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32415.500919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32415.500919 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24500 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 50 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 35496423 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 35496423 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.012284 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.070810 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.036378 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.036378 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32188.734777 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 32762.401235 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32648.439170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32648.439170 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 65000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2722.222222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2954.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161549 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 90911 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 890933 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 981844 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 981844 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 61747 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143487 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 205234 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 205234 # number of overall MSHR misses +system.cpu.dcache.writebacks 161616 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 194474 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 891377 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1085851 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1085851 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 62050 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 143399 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 205449 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 205449 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1261220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4731766000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5992986000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5992986000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1277837500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4733841000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6011678500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6011678500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003045 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009819 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005882 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005882 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20425.607722 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32976.966554 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29200.746465 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29200.746465 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002971 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005788 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005788 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20593.674456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33011.673722 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29261.171872 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29261.171872 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148998 # number of replacements -system.cpu.l2cache.tagsinuse 18953.465492 # Cycle average of tags in use -system.cpu.l2cache.total_refs 137682 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 174354 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.789669 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 149117 # number of replacements +system.cpu.l2cache.tagsinuse 18922.306950 # Cycle average of tags in use +system.cpu.l2cache.total_refs 136795 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 174479 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.784020 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3229.937002 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15723.528490 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.098570 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.479844 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 109274 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161549 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12075 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 121349 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 121349 # number of overall hits -system.cpu.l2cache.ReadReq_misses 43926 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131414 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 175340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 175340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1500006000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4522435500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6022441500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6022441500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 153200 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161549 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 296689 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 296689 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.286723 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.915847 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.590989 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.590989 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34148.476984 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34413.650753 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34347.219687 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34347.219687 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 3199.290629 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15723.016321 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.097635 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.479828 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 108324 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 161616 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 12021 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 120345 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 120345 # number of overall hits +system.cpu.l2cache.ReadReq_misses 44045 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 131407 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 175452 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 175452 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1515912500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4525567500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 6041480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 6041480000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 152369 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 161616 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 143428 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 295797 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 295797 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.289068 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.916188 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.593150 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.593150 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34417.357248 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34439.318301 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34433.805257 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34433.805257 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120514 # number of writebacks +system.cpu.l2cache.writebacks 120521 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 43926 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131414 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 175340 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 175340 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 44045 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 131407 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 175452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 175452 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1363479000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4116799500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5480278500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5480278500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1367450000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118334500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5485784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5485784500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.286723 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915847 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.590989 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.590989 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.363338 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.947662 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31255.152846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31255.152846 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.289068 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.916188 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.593150 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.593150 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.656828 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31340.297701 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31266.582883 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31266.582883 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 6d7c0bcb0..39371a1d2 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 46c2d0591..207188f08 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 16 2011 09:57:35 -gem5 started Aug 16 2011 10:08:58 -gem5 executing on nadc-0270 +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 21:03:42 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 36358325000 because target called exit() +Exiting @ tick 31377609500 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 95c5d6049..67af91500 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.036358 # Number of seconds simulated -sim_ticks 36358325000 # Number of ticks simulated +sim_seconds 0.031378 # Number of seconds simulated +sim_ticks 31377609500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119827 # Simulator instruction rate (inst/s) -host_tick_rate 43292688 # Simulator tick rate (ticks/s) -host_mem_usage 272264 # Number of bytes of host memory used -host_seconds 839.83 # Real time elapsed on the host -sim_insts 100633775 # Number of instructions simulated +host_inst_rate 86505 # Simulator instruction rate (inst/s) +host_tick_rate 26972311 # Simulator tick rate (ticks/s) +host_mem_usage 272452 # Number of bytes of host memory used +host_seconds 1163.33 # Real time elapsed on the host +sim_insts 100633440 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 72716651 # number of cpu cycles simulated +system.cpu.numCycles 62755220 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18013375 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11772112 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 832376 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15327252 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9900840 # Number of BTB hits +system.cpu.BPredUnit.lookups 17750529 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11606544 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 829921 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15137991 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9794974 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1964037 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 178584 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13247418 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90436613 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18013375 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11864877 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 23481643 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3251985 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 32424598 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1373 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12458457 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221175 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 71500308 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.766045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.955660 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1897089 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 178911 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13034693 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 89118710 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17750529 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11692063 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 23121914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2980918 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 23222293 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1054 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12266935 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 235956 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 61445707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.021826 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.078498 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 48035418 67.18% 67.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2508903 3.51% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2594650 3.63% 74.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2541855 3.56% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1760239 2.46% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1724167 2.41% 82.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1024110 1.43% 84.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1345153 1.88% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9965813 13.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38339721 62.40% 62.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2446048 3.98% 66.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2617640 4.26% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2484251 4.04% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1726192 2.81% 77.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1710249 2.78% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014832 1.65% 81.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1300729 2.12% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9806045 15.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71500308 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247720 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.243685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15629487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 30668783 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20991644 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1963924 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2246470 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3557308 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100615 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123225405 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 322834 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2246470 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17904325 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3174295 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20084450 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20590055 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7500713 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 119940984 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 135288 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5895117 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 121539560 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 551911893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 551809859 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 102034 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99143709 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22395801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 778680 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 778694 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 18433689 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30390382 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 23021081 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 18365996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16439244 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 114579507 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 778229 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107939670 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 154653 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14553196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 40300795 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 77221 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 71500308 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.509639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.632123 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 61445707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.282853 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.420100 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14959115 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 21951327 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21472779 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1093721 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1968765 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3488107 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 121008055 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 332806 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1968765 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16904329 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2023707 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15518382 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20592468 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4438056 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117725717 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3874 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3096804 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 422 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 119617057 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541668803 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541574389 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94414 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99143173 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 20473879 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 769482 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 769728 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12274515 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29853222 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22441342 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2796873 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3745515 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112284917 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 766220 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107896322 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 310095 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12199571 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30868237 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 65279 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 61445707 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.755962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.898029 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25383976 35.50% 35.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17917807 25.06% 60.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 11054386 15.46% 76.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7575334 10.59% 86.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5467314 7.65% 94.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2200256 3.08% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1169231 1.64% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 554865 0.78% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 177139 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22301465 36.29% 36.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11812133 19.22% 55.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8597395 13.99% 69.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7417461 12.07% 81.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4807172 7.82% 89.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3508678 5.71% 95.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1667450 2.71% 97.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 811386 1.32% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 522567 0.85% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71500308 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 61445707 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 116974 6.43% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1491133 81.95% 88.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 211505 11.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 87227 3.33% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1494399 56.99% 60.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1040416 39.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57828785 53.58% 53.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 87098 0.08% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 50 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 3 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28711971 26.60% 80.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21311756 19.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57176503 52.99% 52.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 87495 0.08% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29053069 26.93% 80.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21579219 20.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107939670 # Type of FU issued -system.cpu.iq.rate 1.484387 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1819612 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016858 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 289353682 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129921210 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106049922 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 300 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109759169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1061783 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107896322 # Type of FU issued +system.cpu.iq.rate 1.719320 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2622042 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024301 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 280170245 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125277700 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105616251 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 243 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 88 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110518239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 125 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1858517 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3081882 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2255 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10977 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2463953 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2544801 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28033 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1884293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2246470 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1025437 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38382 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115436550 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 596020 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30390382 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 23021081 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 761032 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4943 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5670 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10977 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 689404 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 204972 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 894376 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106732644 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28388861 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1207019 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1968765 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 949271 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28405 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113127739 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 631806 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29853222 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22441342 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 749089 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1264 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28033 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 689722 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 200512 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 890234 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106504319 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28672397 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1392003 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 78814 # number of nop insts executed -system.cpu.iew.exec_refs 49502432 # number of memory reference insts executed -system.cpu.iew.exec_branches 14773493 # Number of branches executed -system.cpu.iew.exec_stores 21113571 # Number of stores executed -system.cpu.iew.exec_rate 1.467788 # Inst execution rate -system.cpu.iew.wb_sent 106273270 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106050012 # cumulative count of insts written-back -system.cpu.iew.wb_producers 55103842 # num instructions producing a value -system.cpu.iew.wb_consumers 106001150 # num instructions consuming a value +system.cpu.iew.exec_nop 76602 # number of nop insts executed +system.cpu.iew.exec_refs 49938031 # number of memory reference insts executed +system.cpu.iew.exec_branches 14639990 # Number of branches executed +system.cpu.iew.exec_stores 21265634 # Number of stores executed +system.cpu.iew.exec_rate 1.697139 # Inst execution rate +system.cpu.iew.wb_sent 105945343 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105616339 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52584494 # num instructions producing a value +system.cpu.iew.wb_consumers 101353649 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.458401 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.519842 # average fanout of values written-back +system.cpu.iew.wb_rate 1.682989 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.518822 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100639327 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 14717021 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 701008 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 796431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 69253839 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.453195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.128132 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100638992 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12404270 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 700941 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 795177 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 59476943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.692067 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.421797 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30742933 44.39% 44.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19764540 28.54% 72.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4768337 6.89% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4180096 6.04% 85.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3349632 4.84% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1422305 2.05% 92.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 712095 1.03% 93.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 496006 0.72% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3817895 5.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 26426974 44.43% 44.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14734590 24.77% 69.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4278530 7.19% 76.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3643335 6.13% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2295146 3.86% 86.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1888116 3.17% 89.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 696870 1.17% 90.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 492103 0.83% 91.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5021279 8.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 69253839 # Number of insts commited each cycle -system.cpu.commit.count 100639327 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 59476943 # Number of insts commited each cycle +system.cpu.commit.count 100638992 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865603 # Number of memory references committed -system.cpu.commit.loads 27308487 # Number of loads committed +system.cpu.commit.refs 47865469 # Number of memory references committed +system.cpu.commit.loads 27308420 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670006 # Number of branches committed +system.cpu.commit.branches 13669939 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91478299 # Number of committed integer instructions. +system.cpu.commit.int_insts 91478031 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3817895 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5021279 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180766993 # The number of ROB reads -system.cpu.rob.rob_writes 232965550 # The number of ROB writes -system.cpu.timesIdled 61914 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1216343 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100633775 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633775 # Number of Instructions Simulated -system.cpu.cpi 0.722587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.722587 # CPI: Total CPI of All Threads -system.cpu.ipc 1.383917 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.383917 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512803523 # number of integer regfile reads -system.cpu.int_regfile_writes 104642569 # number of integer regfile writes -system.cpu.fp_regfile_reads 286 # number of floating regfile reads -system.cpu.fp_regfile_writes 254 # number of floating regfile writes -system.cpu.misc_regfile_reads 148108878 # number of misc regfile reads -system.cpu.misc_regfile_writes 34596 # number of misc regfile writes -system.cpu.icache.replacements 27541 # number of replacements -system.cpu.icache.tagsinuse 1822.972635 # Cycle average of tags in use -system.cpu.icache.total_refs 12427797 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 29578 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 420.170295 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 167473627 # The number of ROB reads +system.cpu.rob.rob_writes 228061528 # The number of ROB writes +system.cpu.timesIdled 61721 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1309513 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100633440 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633440 # Number of Instructions Simulated +system.cpu.cpi 0.623602 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.623602 # CPI: Total CPI of All Threads +system.cpu.ipc 1.603587 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.603587 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512681755 # number of integer regfile reads +system.cpu.int_regfile_writes 104103098 # number of integer regfile writes +system.cpu.fp_regfile_reads 154 # number of floating regfile reads +system.cpu.fp_regfile_writes 120 # number of floating regfile writes +system.cpu.misc_regfile_reads 146929222 # number of misc regfile reads +system.cpu.misc_regfile_writes 34462 # number of misc regfile writes +system.cpu.icache.replacements 26055 # number of replacements +system.cpu.icache.tagsinuse 1807.169356 # Cycle average of tags in use +system.cpu.icache.total_refs 12237713 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 28088 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 435.691861 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1822.972635 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.890123 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12427797 # number of ReadReq hits -system.cpu.icache.demand_hits 12427797 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12427797 # number of overall hits -system.cpu.icache.ReadReq_misses 30660 # number of ReadReq misses -system.cpu.icache.demand_misses 30660 # number of demand (read+write) misses -system.cpu.icache.overall_misses 30660 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 366375500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 366375500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 366375500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12458457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12458457 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12458457 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002461 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002461 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 11949.624918 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 11949.624918 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 11949.624918 # average overall miss latency +system.cpu.icache.occ_blocks::0 1807.169356 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.882407 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12237715 # number of ReadReq hits +system.cpu.icache.demand_hits 12237715 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12237715 # number of overall hits +system.cpu.icache.ReadReq_misses 29220 # number of ReadReq misses +system.cpu.icache.demand_misses 29220 # number of demand (read+write) misses +system.cpu.icache.overall_misses 29220 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 359586000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 359586000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 359586000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12266935 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12266935 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12266935 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002382 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002382 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002382 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12306.160164 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12306.160164 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12306.160164 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,143 +354,145 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1075 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1075 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1075 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 29585 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 29585 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 29585 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1104 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1104 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1104 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 28116 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 28116 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 28116 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 250083000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 250083000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 250083000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 247135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 247135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 247135000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002375 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002375 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002375 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8453.033632 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8453.033632 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8453.033632 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.002292 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002292 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002292 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8789.834969 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157556 # number of replacements -system.cpu.dcache.tagsinuse 4075.680070 # Cycle average of tags in use -system.cpu.dcache.total_refs 45321004 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161652 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 280.361542 # Average number of references to valid blocks. +system.cpu.dcache.replacements 157895 # number of replacements +system.cpu.dcache.tagsinuse 4072.454592 # Cycle average of tags in use +system.cpu.dcache.total_refs 44804358 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 161991 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 276.585477 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 307509000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4075.680070 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995039 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26986530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18297810 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 19355 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17297 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 45284340 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 45284340 # number of overall hits -system.cpu.dcache.ReadReq_misses 104939 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1552091 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1657030 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1657030 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2337604500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 51739462000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 386500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 54077066500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 54077066500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 27091469 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4072.454592 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994252 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 26458104 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18310282 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 18655 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17230 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 44768386 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 44768386 # number of overall hits +system.cpu.dcache.ReadReq_misses 108049 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1539619 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 28 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1647668 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1647668 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2398708000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 52285313500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 392000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 54684021500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 54684021500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 26566153 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 19382 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17297 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46941370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46941370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.078191 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035300 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035300 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22275.841203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33335.327632 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14314.814815 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32634.935095 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32634.935095 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 18683 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17230 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46416054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46416054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001499 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035498 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035498 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22200.186952 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33959.904041 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33188.737962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33188.737962 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18444.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123342 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 50191 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1445181 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1495372 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1495372 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54748 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106910 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 161658 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 161658 # number of overall MSHR misses +system.cpu.dcache.writebacks 123449 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 52916 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1432732 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 28 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1485648 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1485648 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 55133 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106887 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 162020 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 162020 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1029521500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3652232000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4681753500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4681753500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1036639500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3662530000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4699169500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4699169500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003444 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003444 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18804.732593 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34161.743523 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 28960.852541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 28960.852541 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002075 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003491 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003491 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18802.522990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34265.439202 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114899 # number of replacements -system.cpu.l2cache.tagsinuse 18376.822812 # Cycle average of tags in use -system.cpu.l2cache.total_refs 73444 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133749 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.549118 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114951 # number of replacements +system.cpu.l2cache.tagsinuse 18297.678495 # Cycle average of tags in use +system.cpu.l2cache.total_refs 72351 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133808 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.540708 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2396.199422 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15980.623390 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.073126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487690 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 51683 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123342 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 55992 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 55992 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32640 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102597 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 135237 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 135237 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1115857000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3525923000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4641780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4641780000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 84323 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123342 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106906 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 191229 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 191229 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.387083 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.707199 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.707199 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34186.795343 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.726123 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34323.299097 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34323.299097 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2366.019129 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15931.659366 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072205 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486196 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 50475 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123449 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 9 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 4296 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 54771 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 54771 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32704 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 135302 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 135302 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1119458500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3525951000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4645409500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4645409500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 83179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123449 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106894 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 190073 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 190073 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.393176 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.678571 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959811 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.711842 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.711842 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34230.017735 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 1789.473684 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.664068 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34333.635127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34333.635127 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,32 +501,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88453 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32559 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102597 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 135156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 135156 # number of overall MSHR misses +system.cpu.l2cache.writebacks 88458 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 87 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32617 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 135215 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 135215 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1011231500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200947000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4212178500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4212178500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1013752000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197491000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4211243000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4211243000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.386122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.706776 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.706776 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.432384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392130 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.678571 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959811 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.711385 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.711385 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.479505 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31199.226098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.308976 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.308976 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31165.237139 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index d0874930c..c23f9d7a4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 634bd1ef5..f6c6ec79d 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 19:08:37 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 15:02:03 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 630794322500 because target called exit() +Exiting @ tick 620013549500 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 612ce5ecb..a98b75386 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.630794 # Number of seconds simulated -sim_ticks 630794322500 # Number of ticks simulated +sim_seconds 0.620014 # Number of seconds simulated +sim_ticks 620013549500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76362 # Simulator instruction rate (inst/s) -host_tick_rate 27746395 # Simulator tick rate (ticks/s) -host_mem_usage 246464 # Number of bytes of host memory used -host_seconds 22734.28 # Real time elapsed on the host +host_inst_rate 119897 # Simulator instruction rate (inst/s) +host_tick_rate 42820054 # Simulator tick rate (ticks/s) +host_mem_usage 252132 # Number of bytes of host memory used +host_seconds 14479.51 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 603175408 # DTB read hits -system.cpu.dtb.read_misses 10382155 # DTB read misses +system.cpu.dtb.read_hits 605264801 # DTB read hits +system.cpu.dtb.read_misses 10656374 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 613557563 # DTB read accesses -system.cpu.dtb.write_hits 207486280 # DTB write hits -system.cpu.dtb.write_misses 6703729 # DTB write misses +system.cpu.dtb.read_accesses 615921175 # DTB read accesses +system.cpu.dtb.write_hits 208028494 # DTB write hits +system.cpu.dtb.write_misses 6799304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214190009 # DTB write accesses -system.cpu.dtb.data_hits 810661688 # DTB hits -system.cpu.dtb.data_misses 17085884 # DTB misses +system.cpu.dtb.write_accesses 214827798 # DTB write accesses +system.cpu.dtb.data_hits 813293295 # DTB hits +system.cpu.dtb.data_misses 17455678 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 827747572 # DTB accesses -system.cpu.itb.fetch_hits 389142997 # ITB hits +system.cpu.dtb.data_accesses 830748973 # DTB accesses +system.cpu.itb.fetch_hits 388376966 # ITB hits system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 389143035 # ITB accesses +system.cpu.itb.fetch_accesses 388377004 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1261588646 # number of cpu cycles simulated +system.cpu.numCycles 1240027100 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 372091723 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 287344410 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19482025 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 339026759 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 332564866 # Number of BTB hits +system.cpu.BPredUnit.lookups 371321925 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 286983057 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19433409 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 338368339 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 331826895 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 24521483 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1913 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 401603290 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3128927097 # Number of instructions fetch has processed -system.cpu.fetch.Branches 372091723 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 357086349 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 613258490 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 135586269 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 127041969 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 24336199 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1812 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 400687979 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3119280790 # Number of instructions fetch has processed +system.cpu.fetch.Branches 371321925 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 356163094 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 611390068 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 134440863 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 114604724 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 389142997 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9519109 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1250962446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.501216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.011577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 388376966 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9643914 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1234576300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.526600 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.016057 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 637703956 50.98% 50.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53070188 4.24% 55.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 35635977 2.85% 58.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 54551976 4.36% 62.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 136343152 10.90% 73.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 75070366 6.00% 79.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 52403227 4.19% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 43683605 3.49% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 162499999 12.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 623186232 50.48% 50.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52867156 4.28% 54.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 35732021 2.89% 57.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 53999250 4.37% 62.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 136250417 11.04% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 74701815 6.05% 79.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 52334630 4.24% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 43604913 3.53% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 161899866 13.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1250962446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.294939 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.480148 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 431101199 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 113892603 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 582711633 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14200214 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 109056797 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 57497676 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3047130030 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2024 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 109056797 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 453766318 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66152638 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 4489 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 572459547 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49522657 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2962251585 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 509472 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 8488964 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 37728922 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2215831278 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3828352305 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3827339752 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1012553 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1234576300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299447 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.515494 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 429010583 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 102446210 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 582198456 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13029284 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 107891767 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 57297832 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 881 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3038448049 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1952 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 107891767 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 451268352 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 59486920 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3651 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 571427779 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 44497831 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2952461199 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 509967 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3056593 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 38427215 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2208688695 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3815339116 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3814332639 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1006477 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 839628315 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 266 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 263 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 102105357 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 670128900 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250448120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 97927277 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 62674140 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2669873432 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 219 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2466087969 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1699054 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 923450677 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 397988094 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 190 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1250962446 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.971353 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.922762 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 832485732 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 193 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 190 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 93322285 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 667580197 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 249072955 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 55659961 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 31733911 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2660179037 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 172 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2468673818 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1992617 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 912469366 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 383003969 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 143 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1234576300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.999612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.936572 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 403537577 32.26% 32.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 206908557 16.54% 48.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 196272095 15.69% 64.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 156883452 12.54% 77.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 140843033 11.26% 88.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74249795 5.94% 94.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 49611438 3.97% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17556861 1.40% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5099638 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 394722049 31.97% 31.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 200520183 16.24% 48.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 195096973 15.80% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152865023 12.38% 76.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 138702547 11.23% 87.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 76304962 6.18% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56923142 4.61% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14040598 1.14% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5400823 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1250962446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1234576300 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3929936 26.79% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9164613 62.47% 89.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1575877 10.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1834419 11.27% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11081610 68.08% 79.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3361740 20.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1614368204 65.46% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 252 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 149 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 19 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 631861651 25.62% 91.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 219857557 8.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1613757187 65.37% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 92 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 155 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 634184534 25.69% 91.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 220731537 8.94% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2466087969 # Type of FU issued -system.cpu.iq.rate 1.954748 # Inst issue rate -system.cpu.iq.fu_busy_cnt 14670426 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6197744460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3592745886 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2365749940 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1763404 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1020600 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 828073 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2479878842 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 879553 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54119833 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2468673818 # Type of FU issued +system.cpu.iq.rate 1.990822 # Inst issue rate +system.cpu.iq.fu_busy_cnt 16277769 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6188434736 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3572169427 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2366146276 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1759586 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1005347 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 824789 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2484075446 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 876141 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54414516 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 225533237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 274653 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 443666 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 89719618 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 222984534 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 276039 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 531067 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 88344453 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 53 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 70 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162806 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 109056797 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23925138 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1338311 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2811874535 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12833381 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 670128900 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250448120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 219 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 545828 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18223 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 443666 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 20334836 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2010249 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22345085 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2412233933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 613557757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53854036 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 107891767 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22183001 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1020429 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2801921331 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12930096 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 667580197 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 249072955 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 172 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 231741 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17901 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 531067 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 20319343 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2050255 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22369598 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2414335785 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 615921372 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 54338033 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142000884 # number of nop insts executed -system.cpu.iew.exec_refs 827747782 # number of memory reference insts executed -system.cpu.iew.exec_branches 295599123 # Number of branches executed -system.cpu.iew.exec_stores 214190025 # Number of stores executed -system.cpu.iew.exec_rate 1.912061 # Inst execution rate -system.cpu.iew.wb_sent 2392748648 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2366578013 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1358866108 # num instructions producing a value -system.cpu.iew.wb_consumers 1719778019 # num instructions consuming a value +system.cpu.iew.exec_nop 141742122 # number of nop insts executed +system.cpu.iew.exec_refs 830749189 # number of memory reference insts executed +system.cpu.iew.exec_branches 295817735 # Number of branches executed +system.cpu.iew.exec_stores 214827817 # Number of stores executed +system.cpu.iew.exec_rate 1.947002 # Inst execution rate +system.cpu.iew.wb_sent 2393878434 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2366971065 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1353323878 # num instructions producing a value +system.cpu.iew.wb_consumers 1710357727 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.875871 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790140 # average fanout of values written-back +system.cpu.iew.wb_rate 1.908806 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.791252 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 759617769 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 748592924 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19481102 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1141905649 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.593634 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.464996 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19432624 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1126684533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.615164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.477479 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 604531379 52.94% 52.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194846854 17.06% 70.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 88590760 7.76% 77.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56412510 4.94% 82.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 37294667 3.27% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28799723 2.52% 88.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22448338 1.97% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 21204433 1.86% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 87776985 7.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 590961452 52.45% 52.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 189557925 16.82% 69.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95769677 8.50% 77.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53357223 4.74% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 37491988 3.33% 85.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27218230 2.42% 88.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21816919 1.94% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22438390 1.99% 92.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88072729 7.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1141905649 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1126684533 # Number of insts commited each cycle system.cpu.commit.count 1819780126 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 605324165 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 87776985 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88072729 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3547747359 # The number of ROB reads -system.cpu.rob.rob_writes 5268048666 # The number of ROB writes -system.cpu.timesIdled 494946 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10626200 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3521205654 # The number of ROB reads +system.cpu.rob.rob_writes 5244829032 # The number of ROB writes +system.cpu.timesIdled 389205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5450800 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.726703 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.726703 # CPI: Total CPI of All Threads -system.cpu.ipc 1.376078 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.376078 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3245673408 # number of integer regfile reads -system.cpu.int_regfile_writes 1894558271 # number of integer regfile writes -system.cpu.fp_regfile_reads 13236 # number of floating regfile reads -system.cpu.fp_regfile_writes 507 # number of floating regfile writes +system.cpu.cpi 0.714283 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.714283 # CPI: Total CPI of All Threads +system.cpu.ipc 1.400005 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.400005 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3248506464 # number of integer regfile reads +system.cpu.int_regfile_writes 1894457648 # number of integer regfile writes +system.cpu.fp_regfile_reads 12410 # number of floating regfile reads +system.cpu.fp_regfile_writes 512 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 755.752117 # Cycle average of tags in use -system.cpu.icache.total_refs 389141650 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 412226.324153 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 749.102661 # Cycle average of tags in use +system.cpu.icache.total_refs 388375634 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 411851.149523 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 755.752117 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.369020 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 389141650 # number of ReadReq hits -system.cpu.icache.demand_hits 389141650 # number of demand (read+write) hits -system.cpu.icache.overall_hits 389141650 # number of overall hits -system.cpu.icache.ReadReq_misses 1347 # number of ReadReq misses -system.cpu.icache.demand_misses 1347 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47225000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47225000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47225000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 389142997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 389142997 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 389142997 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 749.102661 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.365773 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 388375634 # number of ReadReq hits +system.cpu.icache.demand_hits 388375634 # number of demand (read+write) hits +system.cpu.icache.overall_hits 388375634 # number of overall hits +system.cpu.icache.ReadReq_misses 1332 # number of ReadReq misses +system.cpu.icache.demand_misses 1332 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1332 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 46849500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 46849500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 46849500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 388376966 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 388376966 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 388376966 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35059.391240 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35059.391240 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35059.391240 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35172.297297 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35172.297297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35172.297297 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,169 +343,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 403 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 403 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 403 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 389 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 389 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 389 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33492000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33492000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33492000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33478000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33478000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33478000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35478.813559 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35478.813559 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35478.813559 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35501.590668 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35501.590668 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35501.590668 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9159626 # number of replacements -system.cpu.dcache.tagsinuse 4087.185824 # Cycle average of tags in use -system.cpu.dcache.total_refs 694644975 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9163722 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.803803 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5155515000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.185824 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997848 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 538784960 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 155860012 # number of WriteReq hits +system.cpu.dcache.replacements 9160008 # number of replacements +system.cpu.dcache.tagsinuse 4087.032311 # Cycle average of tags in use +system.cpu.dcache.total_refs 696282176 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9164104 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.979297 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5156765000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.032311 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997811 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 540448912 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 155833261 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 694644972 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 694644972 # number of overall hits -system.cpu.dcache.ReadReq_misses 10193496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4868490 # number of WriteReq misses +system.cpu.dcache.demand_hits 696282173 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 696282173 # number of overall hits +system.cpu.dcache.ReadReq_misses 10323793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 4895241 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15061986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15061986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 169402977500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 135886448359 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15219034 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15219034 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 172136393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 136959411379 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 305289425859 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 305289425859 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 548978456 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 309095804879 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 309095804879 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 550772705 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 709706958 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 709706958 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.018568 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.030290 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 711501207 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 711501207 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.018744 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.030457 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021223 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021223 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16618.731935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27911.415728 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.021390 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021390 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16673.754840 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27978.073271 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 20268.869315 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 20268.869315 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 119358733 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148382000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37827 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65115 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3155.384593 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32993.657375 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency 20309.817619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 20309.817619 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 119249756 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148365000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37808 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.087918 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32995.423200 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3077546 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2914965 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2983300 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5898265 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5898265 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7278531 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1885190 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 3077590 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3044730 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3010201 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6054931 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6054931 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7279063 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1885040 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9163721 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9163721 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 9164103 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9164103 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 80729480000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38630501513 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 80943069500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38634312034 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 119359981513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 119359981513 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 119577381534 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 119577381534 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013258 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011729 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013216 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011728 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.012912 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.012912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11091.452382 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20491.569292 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.012880 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.012880 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11119.984743 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20495.221340 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13025.274505 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13025.274505 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13048.454555 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13048.454555 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2693791 # number of replacements -system.cpu.l2cache.tagsinuse 26705.078667 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7632821 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2718423 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.807812 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 127919553500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15965.123035 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10739.955632 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.487217 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.327757 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5458638 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3077546 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1001691 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6460329 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6460329 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1820833 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 883504 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2704337 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2704337 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 62507649000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 30451140500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 92958789500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 92958789500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7279471 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3077546 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1885195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9164666 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9164666 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250133 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.468654 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295083 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295083 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34329.149900 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34466.330090 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34373.966521 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34373.966521 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 17593500 # number of cycles access was blocked +system.cpu.l2cache.replacements 2693796 # number of replacements +system.cpu.l2cache.tagsinuse 26682.483839 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7633391 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2718433 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.808011 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 127776884500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15920.049734 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10762.434105 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.485841 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.328443 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5459110 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3077590 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 1001562 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6460672 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6460672 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1820887 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 883488 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2704375 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2704375 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 62517574500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 30445882000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 92963456500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 92963456500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7279997 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3077590 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1885050 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9165047 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9165047 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250122 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.468681 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295075 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295075 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34333.582754 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.002300 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34375.209244 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34375.209244 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 17565000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1703 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1700 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10330.886671 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10332.352941 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1171811 # number of writebacks +system.cpu.l2cache.writebacks 1171832 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1820833 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 883504 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2704337 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2704337 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1820887 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 883488 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2704375 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2704375 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56722118000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 27628606500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 84350724500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 84350724500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56727891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 27629735500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 84357627000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 84357627000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250133 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468654 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295083 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295083 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.740989 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.625822 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31190.907235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31190.907235 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468681 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.295075 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.295075 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.987864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.470041 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31193.021308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31193.021308 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 9b272f457..a651bdb28 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 30a5002e0..83af142ca 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 03:24:30 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 18 2011 17:30:35 +gem5 started Aug 18 2011 17:40:43 +gem5 executing on nadc-0330 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 520816837000 because target called exit() +Exiting @ tick 506532922500 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index efe6a8ef1..135431d57 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.520817 # Number of seconds simulated -sim_ticks 520816837000 # Number of ticks simulated +sim_seconds 0.506533 # Number of seconds simulated +sim_ticks 506532922500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106291 # Simulator instruction rate (inst/s) -host_tick_rate 32127421 # Simulator tick rate (ticks/s) -host_mem_usage 257992 # Number of bytes of host memory used -host_seconds 16210.98 # Real time elapsed on the host -sim_insts 1723073899 # Number of instructions simulated +host_inst_rate 123802 # Simulator instruction rate (inst/s) +host_tick_rate 36394183 # Simulator tick rate (ticks/s) +host_mem_usage 263680 # Number of bytes of host memory used +host_seconds 13917.96 # Real time elapsed on the host +sim_insts 1723073849 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1041633675 # number of cpu cycles simulated +system.cpu.numCycles 1013065846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 316759816 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 259210728 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18340703 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 279172110 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 252354125 # Number of BTB hits +system.cpu.BPredUnit.lookups 315530681 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 258143608 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18340117 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 278231679 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 251492518 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 20423833 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3592 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 314505496 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2269650018 # Number of instructions fetch has processed -system.cpu.fetch.Branches 316759816 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 272777958 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 507209823 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 102718581 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 118023116 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 13 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 301735103 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6341301 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1020560450 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.475963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.020968 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 20187042 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3509 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 313870814 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2260978275 # Number of instructions fetch has processed +system.cpu.fetch.Branches 315530681 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 271679560 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 505214363 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 101212316 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 104532477 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 328 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 301063999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6471754 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1002877503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.508485 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.026652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 513350682 50.30% 50.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 37274170 3.65% 53.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 66826624 6.55% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71750061 7.03% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 48900197 4.79% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61148306 5.99% 78.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 56009489 5.49% 83.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19114722 1.87% 85.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146186199 14.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 497663194 49.62% 49.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 37228948 3.71% 53.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 66606984 6.64% 59.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71463437 7.13% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 48876391 4.87% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 60858176 6.07% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55641741 5.55% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19086125 1.90% 85.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 145452507 14.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1020560450 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.304099 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.178933 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 345277471 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100386253 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 476244724 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17831036 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 80820966 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 48621536 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 684 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2461002046 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 80820966 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 367852317 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46560982 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20161 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 470070702 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55235322 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2399093241 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19112 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7084037 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41612105 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2375633121 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 11077295262 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11077294016 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1246 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320031 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669313040 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 859 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 115610874 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 649413230 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 228367203 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 119305836 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 109745450 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2270974746 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 855 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2053846795 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4950214 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 542412841 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1352419496 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 388 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1020560450 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.012470 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.816171 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1002877503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.311461 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.231818 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 341996878 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89611613 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 478932686 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13077462 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 79258864 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 48434993 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 667 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2450495134 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2272 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 79258864 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 363548311 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45530514 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19331 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 469125778 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45394705 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2388695520 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19323 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2689291 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 36489292 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2366306887 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 11027767520 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11027765811 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1709 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 659986931 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 807 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 800 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 96182774 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 645482909 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 225885161 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 74160075 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 61434686 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2258262830 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 791 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2062701357 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3805579 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 528742156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1247770653 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 334 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1002877503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.056783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.854473 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 295638482 28.97% 28.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 162908535 15.96% 44.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 186570916 18.28% 63.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 146485651 14.35% 77.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124092307 12.16% 89.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60745284 5.95% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 32474390 3.18% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9761593 0.96% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1883292 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 290604713 28.98% 28.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 157949600 15.75% 44.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 174074952 17.36% 62.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 138718897 13.83% 75.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 127592193 12.72% 88.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 68569400 6.84% 95.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 32608818 3.25% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10494958 1.05% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2263972 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1020560450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1002877503 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1886665 8.33% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 129 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20021118 88.41% 96.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 736661 3.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2048519 7.53% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 180 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19993289 73.47% 81.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5169269 19.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1258507909 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1049624 0.05% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 601998559 29.31% 90.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192290687 9.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1260792748 61.12% 61.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1057290 0.05% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 606172338 29.39% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194678965 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2053846795 # Type of FU issued -system.cpu.iq.rate 1.971755 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22644573 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011025 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5155848613 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2816902201 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1979021508 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 87 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2076491261 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 107 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 49405456 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2062701357 # Type of FU issued +system.cpu.iq.rate 2.036098 # Inst issue rate +system.cpu.iq.fu_busy_cnt 27211257 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013192 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5159296764 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2790611549 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1986898801 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 289 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 125 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2089912468 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 146 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50578054 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 163486436 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 194823 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3514757 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 53520135 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 159556137 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 214192 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3609503 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51038115 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451218 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 451763 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 80820966 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 21846614 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1532145 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2271045706 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6454862 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 649413230 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 228367203 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 463327 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 64846 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3514757 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18903388 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1825622 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20729010 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2013025353 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 580460904 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 40821435 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 79258864 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 21822492 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1097447 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2258327486 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7242198 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 645482909 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 225885161 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 728 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 222856 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63033 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3609503 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18937238 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1831687 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 20768925 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2019710082 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 582582512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42991275 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 70105 # number of nop insts executed -system.cpu.iew.exec_refs 769390557 # number of memory reference insts executed -system.cpu.iew.exec_branches 240046376 # Number of branches executed -system.cpu.iew.exec_stores 188929653 # Number of stores executed -system.cpu.iew.exec_rate 1.932566 # Inst execution rate -system.cpu.iew.wb_sent 1991598100 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1979021595 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1304894020 # num instructions producing a value -system.cpu.iew.wb_consumers 2076228305 # num instructions consuming a value +system.cpu.iew.exec_nop 63865 # number of nop insts executed +system.cpu.iew.exec_refs 773812500 # number of memory reference insts executed +system.cpu.iew.exec_branches 240248597 # Number of branches executed +system.cpu.iew.exec_stores 191229988 # Number of stores executed +system.cpu.iew.exec_rate 1.993661 # Inst execution rate +system.cpu.iew.wb_sent 1997612417 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1986898926 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1306276482 # num instructions producing a value +system.cpu.iew.wb_consumers 2072612086 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.899921 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628493 # average fanout of values written-back +system.cpu.iew.wb_rate 1.961273 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.630256 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1723073917 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 548129621 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18348258 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 939739485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.833566 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.580985 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 535450016 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 457 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 18340062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 923618640 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.865569 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.641231 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 417784524 44.46% 44.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 209332361 22.28% 66.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 89117008 9.48% 76.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 41409082 4.41% 80.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23428101 2.49% 83.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30586895 3.25% 86.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22243111 2.37% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15532475 1.65% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90305928 9.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 417808285 45.24% 45.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 197293052 21.36% 66.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87052087 9.43% 76.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 38036803 4.12% 80.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20677754 2.24% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 32036200 3.47% 85.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19042329 2.06% 87.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12956798 1.40% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98715332 10.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 939739485 # Number of insts commited each cycle -system.cpu.commit.count 1723073917 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 923618640 # Number of insts commited each cycle +system.cpu.commit.count 1723073867 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773837 # Number of memory references committed -system.cpu.commit.loads 485926781 # Number of loads committed +system.cpu.commit.refs 660773817 # Number of memory references committed +system.cpu.commit.loads 485926771 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462375 # Number of branches committed +system.cpu.commit.branches 213462365 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941893 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90305928 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98715332 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3120636496 # The number of ROB reads -system.cpu.rob.rob_writes 4623496698 # The number of ROB writes -system.cpu.timesIdled 989897 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21073225 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1723073899 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073899 # Number of Instructions Simulated -system.cpu.cpi 0.604521 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.604521 # CPI: Total CPI of All Threads -system.cpu.ipc 1.654203 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.654203 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10072525015 # number of integer regfile reads -system.cpu.int_regfile_writes 1968285521 # number of integer regfile writes -system.cpu.fp_regfile_reads 75 # number of floating regfile reads +system.cpu.rob.rob_reads 3083426592 # The number of ROB reads +system.cpu.rob.rob_writes 4596573652 # The number of ROB writes +system.cpu.timesIdled 890932 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10188343 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1723073849 # Number of Instructions Simulated +system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated +system.cpu.cpi 0.587941 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.587941 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700851 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700851 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10108398592 # number of integer regfile reads +system.cpu.int_regfile_writes 1972581504 # number of integer regfile writes +system.cpu.fp_regfile_reads 113 # number of floating regfile reads system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.misc_regfile_reads 3013509835 # number of misc regfile reads -system.cpu.misc_regfile_writes 146 # number of misc regfile writes -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 614.807125 # Cycle average of tags in use -system.cpu.icache.total_refs 301734075 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 749 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 402849.232310 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 3008512623 # number of misc regfile reads +system.cpu.misc_regfile_writes 126 # number of misc regfile writes +system.cpu.icache.replacements 11 # number of replacements +system.cpu.icache.tagsinuse 611.156574 # Cycle average of tags in use +system.cpu.icache.total_refs 301062972 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 404111.371812 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 614.807125 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.300199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 301734075 # number of ReadReq hits -system.cpu.icache.demand_hits 301734075 # number of demand (read+write) hits -system.cpu.icache.overall_hits 301734075 # number of overall hits -system.cpu.icache.ReadReq_misses 1028 # number of ReadReq misses -system.cpu.icache.demand_misses 1028 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1028 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35478500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35478500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35478500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 301735103 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 301735103 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 301735103 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 611.156574 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.298416 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 301062972 # number of ReadReq hits +system.cpu.icache.demand_hits 301062972 # number of demand (read+write) hits +system.cpu.icache.overall_hits 301062972 # number of overall hits +system.cpu.icache.ReadReq_misses 1027 # number of ReadReq misses +system.cpu.icache.demand_misses 1027 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1027 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35502000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35502000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35502000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 301063999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 301063999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 301063999 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34512.159533 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34512.159533 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34512.159533 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34568.646543 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34568.646543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34568.646543 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,176 +354,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 277 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 277 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 277 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 751 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 751 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 751 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 282 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 745 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 745 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 745 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25803000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25803000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25803000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25601000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25601000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25601000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34358.189081 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34358.189081 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34358.189081 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34363.758389 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34363.758389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34363.758389 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9571252 # number of replacements -system.cpu.dcache.tagsinuse 4088.168167 # Cycle average of tags in use -system.cpu.dcache.total_refs 683613233 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9575348 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 71.393043 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3571196000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4088.168167 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998088 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 515943773 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167669303 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 81 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 72 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 683613076 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 683613076 # number of overall hits -system.cpu.dcache.ReadReq_misses 10432910 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4916744 # number of WriteReq misses +system.cpu.dcache.replacements 9572249 # number of replacements +system.cpu.dcache.tagsinuse 4087.950948 # Cycle average of tags in use +system.cpu.dcache.total_refs 684182956 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9576345 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 71.445103 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3569933000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.950948 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998035 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 516770094 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 167412740 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 684182834 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 684182834 # number of overall hits +system.cpu.dcache.ReadReq_misses 10495679 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 5173307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15349654 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15349654 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 181536100500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 122414115127 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15668986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15668986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 184475737500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 128174581168 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 303950215627 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 303950215627 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 526376683 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 312650318668 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 312650318668 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 527265773 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 84 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 72 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 698962730 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 698962730 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.019820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.028489 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.035714 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021961 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021961 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 17400.332266 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24897.394521 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 699851820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 699851820 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.019906 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.029975 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.022389 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.022389 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 17576.350944 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24776.140517 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19801.763325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19801.763325 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 267203110 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 176500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 90930 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2938.558342 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22062.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency 19953.449360 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19953.449360 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 267517156 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91155 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2934.750217 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17208.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3128377 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2750280 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3024025 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 3128719 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2812049 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3280592 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5774305 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5774305 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7682630 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892719 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9575349 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9575349 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 6092641 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6092641 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7683630 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1892715 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9576345 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9576345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 90548331000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 45239706866 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 135788037866 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 135788037866 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 91948284500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 45274333885 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 137222618385 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 137222618385 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014595 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014573 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.010967 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013699 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013699 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11786.111136 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23901.966888 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 14181.001430 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 14181.001430 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.013683 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.013683 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11966.776706 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23920.312295 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 14329.331116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 14329.331116 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2927724 # number of replacements -system.cpu.l2cache.tagsinuse 26806.292865 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7851539 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2955046 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.656994 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 103976307500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15984.419596 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10821.873269 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.487806 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.330257 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5655745 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3128377 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980223 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6635968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6635968 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2027633 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 912497 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2940130 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2940130 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69565462000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31656932500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 101222394500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 101222394500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7683378 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3128377 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892720 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9576098 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9576098 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263899 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.482109 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.307028 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.307028 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34308.704780 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34692.642825 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34427.863564 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34427.863564 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 56270500 # number of cycles access was blocked +system.cpu.l2cache.replacements 2927741 # number of replacements +system.cpu.l2cache.tagsinuse 26823.943722 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7852858 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2955065 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.657423 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 103629166500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 16019.902231 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10804.041491 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.488889 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.329713 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5656678 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3128719 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 980284 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6636962 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6636962 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2027695 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 912433 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2940128 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2940128 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 69610117500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 31648090500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 101258208000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 101258208000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7684373 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3128719 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1892717 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9577090 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9577090 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.263873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.306996 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.306996 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34329.678527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.385667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34440.067915 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34440.067915 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 56477000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 6598 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6600 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8528.417702 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8557.121212 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1217507 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2027621 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 912497 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2940118 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2940118 # number of overall MSHR misses +system.cpu.l2cache.writebacks 1217526 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2027684 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 912433 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2940117 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2940117 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 63172977500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28814369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 91987347000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 91987347000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 63223600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 92038661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 92038661500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263897 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482109 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.307027 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.307027 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.205967 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31577.495049 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31286.957530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31286.957530 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263871 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.306995 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.306995 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31180.203621 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31580.468374 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31304.421389 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31304.421389 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 9b349a51c..cbca14c5b 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index cae861e0e..43a475337 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 19:50:53 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 14:49:49 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 33574995000 because target called exit() +122 123 124 Exiting @ tick 30278595500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 9b4ccbc94..08d328376 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033575 # Number of seconds simulated -sim_ticks 33574995000 # Number of ticks simulated +sim_seconds 0.030279 # Number of seconds simulated +sim_ticks 30278595500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75399 # Simulator instruction rate (inst/s) -host_tick_rate 30072740 # Simulator tick rate (ticks/s) -host_mem_usage 250632 # Number of bytes of host memory used -host_seconds 1116.46 # Real time elapsed on the host +host_inst_rate 116969 # Simulator instruction rate (inst/s) +host_tick_rate 42072708 # Simulator tick rate (ticks/s) +host_mem_usage 256296 # Number of bytes of host memory used +host_seconds 719.67 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25910068 # DTB read hits -system.cpu.dtb.read_misses 487884 # DTB read misses +system.cpu.dtb.read_hits 25688278 # DTB read hits +system.cpu.dtb.read_misses 550762 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 26397952 # DTB read accesses -system.cpu.dtb.write_hits 7442430 # DTB write hits -system.cpu.dtb.write_misses 947 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7443377 # DTB write accesses -system.cpu.dtb.data_hits 33352498 # DTB hits -system.cpu.dtb.data_misses 488831 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 33841329 # DTB accesses -system.cpu.itb.fetch_hits 20391081 # ITB hits +system.cpu.dtb.read_accesses 26239040 # DTB read accesses +system.cpu.dtb.write_hits 7360758 # DTB write hits +system.cpu.dtb.write_misses 1044 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7361802 # DTB write accesses +system.cpu.dtb.data_hits 33049036 # DTB hits +system.cpu.dtb.data_misses 551806 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 33600842 # DTB accesses +system.cpu.itb.fetch_hits 19370237 # ITB hits system.cpu.itb.fetch_misses 82 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 20391163 # ITB accesses +system.cpu.itb.fetch_accesses 19370319 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 67149991 # number of cpu cycles simulated +system.cpu.numCycles 60557192 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20043424 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 14890335 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1886616 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 16546187 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 12995160 # Number of BTB hits +system.cpu.BPredUnit.lookups 18972162 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 14043194 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1908534 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15684343 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 12020738 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1876944 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2472 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 21676746 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 172437485 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20043424 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14872104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 31892042 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10307497 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5295116 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1817403 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2435 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 20660360 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 162109118 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18972162 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13838141 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 29871214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8831306 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3272537 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1817 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 20391081 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 650323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 67056836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.571512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.236226 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 19370237 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 684277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 60463700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.681098 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.259568 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 35164794 52.44% 52.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3176485 4.74% 57.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2538345 3.79% 60.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3535941 5.27% 66.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4282691 6.39% 72.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1574198 2.35% 74.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1997484 2.98% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1705355 2.54% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 13081543 19.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 30592486 50.60% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2950542 4.88% 55.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2105012 3.48% 58.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3386904 5.60% 64.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4238557 7.01% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1492876 2.47% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1782148 2.95% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1645056 2.72% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12270119 20.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 67056836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298487 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.567945 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23902898 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4218142 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 29787412 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 970752 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8177632 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3156419 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13804 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 166261756 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43031 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8177632 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25731687 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1160543 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 28902105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3078846 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 159343297 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 60463700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.313293 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.676959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22547787 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2537266 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 28115662 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 618580 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6644405 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2987075 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13654 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 155918946 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42842 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6644405 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24245198 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 523469 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6031 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 27028766 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2015831 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 148832808 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 846266 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1904805 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 117303281 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 206166674 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 193984489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 12182185 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 266593 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1498062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 109279851 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 192445710 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 181748286 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10697424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48875920 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 516 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8753950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33541628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10395963 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7223070 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2102878 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 134779237 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107642256 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 461690 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 49489496 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42823427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 67056836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.605239 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.754849 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 40852490 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 518 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 515 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6036784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30729381 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9521294 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2640558 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 881343 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 123679327 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 494 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105899114 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 512588 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 38384232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30395152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 105 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 60463700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.751449 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.825920 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24956395 37.22% 37.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14036514 20.93% 58.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10136000 15.12% 73.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7177120 10.70% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5400162 8.05% 92.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2788229 4.16% 96.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1798139 2.68% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 642461 0.96% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 121816 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21057299 34.83% 34.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11707934 19.36% 54.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9587960 15.86% 70.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6925941 11.45% 81.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5557420 9.19% 90.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2847009 4.71% 95.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1835835 3.04% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796714 1.32% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 147588 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 67056836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 60463700 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 201993 12.31% 12.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 250 0.02% 12.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6175 0.38% 12.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5518 0.34% 13.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 850319 51.81% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 486670 29.65% 94.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 90238 5.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186761 11.23% 11.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 209 0.01% 11.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6487 0.39% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3444 0.21% 11.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 845716 50.84% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 517920 31.13% 93.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 103033 6.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 65718321 61.05% 61.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491419 0.46% 61.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2837753 2.64% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 114927 0.11% 64.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2460943 2.29% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 308030 0.29% 66.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 776022 0.72% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27323056 25.38% 92.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7611460 7.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 64090689 60.52% 60.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 486042 0.46% 60.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2799885 2.64% 63.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 114989 0.11% 63.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2411237 2.28% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311681 0.29% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763573 0.72% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27425152 25.90% 92.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7495540 7.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107642256 # Type of FU issued -system.cpu.iq.rate 1.603012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1641163 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 268833280 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 171996090 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 95630473 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15610921 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12638151 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7243335 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 101046338 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8237074 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1306070 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105899114 # Type of FU issued +system.cpu.iq.rate 1.748745 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1663570 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015709 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 259207602 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 152594620 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93309235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15230484 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9878183 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7072078 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 99520074 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8042603 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1240194 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13545430 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9202 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 431066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3894860 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10733183 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14770 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 472388 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3020191 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10948 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10319 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8177632 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205335 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 131722 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 147421220 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 680146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33541628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10395963 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 498 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 98656 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 431066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1771181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 338775 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2109956 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105130467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26398523 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2511789 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6644405 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16385 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 135563884 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 881728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30729381 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9521294 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 494 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 173 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 472388 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1792269 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 350241 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2142510 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 103141866 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26239584 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2757248 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12641484 # number of nop insts executed -system.cpu.iew.exec_refs 33841971 # number of memory reference insts executed -system.cpu.iew.exec_branches 13292827 # Number of branches executed -system.cpu.iew.exec_stores 7443448 # Number of stores executed -system.cpu.iew.exec_rate 1.565607 # Inst execution rate -system.cpu.iew.wb_sent 103975635 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102873808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 69418102 # num instructions producing a value -system.cpu.iew.wb_consumers 96250402 # num instructions consuming a value +system.cpu.iew.exec_nop 11884063 # number of nop insts executed +system.cpu.iew.exec_refs 33601488 # number of memory reference insts executed +system.cpu.iew.exec_branches 12972684 # Number of branches executed +system.cpu.iew.exec_stores 7361904 # Number of stores executed +system.cpu.iew.exec_rate 1.703214 # Inst execution rate +system.cpu.iew.wb_sent 101639951 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 100381313 # cumulative count of insts written-back +system.cpu.iew.wb_producers 68069676 # num instructions producing a value +system.cpu.iew.wb_consumers 93955815 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.532000 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721224 # average fanout of values written-back +system.cpu.iew.wb_rate 1.657628 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724486 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 55519927 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43662883 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1873181 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 58879204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.560875 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.342568 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1895215 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 53819295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.707623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.466902 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 27960283 47.49% 47.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13480171 22.89% 70.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5538232 9.41% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2736120 4.65% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1795830 3.05% 87.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1555437 2.64% 90.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 775440 1.32% 91.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 776613 1.32% 92.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4261078 7.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24819499 46.12% 46.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11624197 21.60% 67.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5120039 9.51% 77.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2844700 5.29% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1712935 3.18% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1498439 2.78% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 822147 1.53% 90.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 790849 1.47% 91.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4586490 8.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 58879204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 53819295 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4261078 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4586490 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 202040068 # The number of ROB reads -system.cpu.rob.rob_writes 303073761 # The number of ROB writes -system.cpu.timesIdled 2271 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93155 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 184797703 # The number of ROB reads +system.cpu.rob.rob_writes 277819902 # The number of ROB writes +system.cpu.timesIdled 2285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93492 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.797698 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.797698 # CPI: Total CPI of All Threads -system.cpu.ipc 1.253607 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.253607 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 141776374 # number of integer regfile reads -system.cpu.int_regfile_writes 77917804 # number of integer regfile writes -system.cpu.fp_regfile_reads 6238511 # number of floating regfile reads -system.cpu.fp_regfile_writes 6227605 # number of floating regfile writes -system.cpu.misc_regfile_reads 722508 # number of misc regfile reads +system.cpu.cpi 0.719380 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.719380 # CPI: Total CPI of All Threads +system.cpu.ipc 1.390086 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.390086 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 139300854 # number of integer regfile reads +system.cpu.int_regfile_writes 75996636 # number of integer regfile writes +system.cpu.fp_regfile_reads 6185785 # number of floating regfile reads +system.cpu.fp_regfile_writes 6053506 # number of floating regfile writes +system.cpu.misc_regfile_reads 715599 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8679 # number of replacements -system.cpu.icache.tagsinuse 1593.583704 # Cycle average of tags in use -system.cpu.icache.total_refs 20379337 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10611 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1920.585901 # Average number of references to valid blocks. +system.cpu.icache.replacements 8657 # number of replacements +system.cpu.icache.tagsinuse 1596.063648 # Cycle average of tags in use +system.cpu.icache.total_refs 19358424 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1827.990935 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1593.583704 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.778117 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 20379337 # number of ReadReq hits -system.cpu.icache.demand_hits 20379337 # number of demand (read+write) hits -system.cpu.icache.overall_hits 20379337 # number of overall hits -system.cpu.icache.ReadReq_misses 11744 # number of ReadReq misses -system.cpu.icache.demand_misses 11744 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11744 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 187534500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 187534500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 187534500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 20391081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 20391081 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 20391081 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000576 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000576 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000576 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15968.537125 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15968.537125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15968.537125 # average overall miss latency +system.cpu.icache.occ_blocks::0 1596.063648 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.779328 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 19358424 # number of ReadReq hits +system.cpu.icache.demand_hits 19358424 # number of demand (read+write) hits +system.cpu.icache.overall_hits 19358424 # number of overall hits +system.cpu.icache.ReadReq_misses 11813 # number of ReadReq misses +system.cpu.icache.demand_misses 11813 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11813 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 188211000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 188211000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 188211000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 19370237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 19370237 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 19370237 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000610 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000610 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000610 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15932.531956 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15932.531956 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15932.531956 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1133 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1133 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1133 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10611 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10611 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10611 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1223 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1223 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1223 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124781500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124781500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124781500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124783500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124783500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124783500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000520 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000520 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000520 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11759.636227 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11759.636227 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11759.636227 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000547 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000547 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000547 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11783.144476 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1459.306327 # Cycle average of tags in use -system.cpu.dcache.total_refs 31085202 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13864.942908 # Average number of references to valid blocks. +system.cpu.dcache.replacements 156 # number of replacements +system.cpu.dcache.tagsinuse 1459.699326 # Cycle average of tags in use +system.cpu.dcache.total_refs 30929897 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2239 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13814.156766 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1459.306327 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356276 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24592075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493081 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 46 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 31085156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 31085156 # number of overall hits -system.cpu.dcache.ReadReq_misses 927 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8022 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1459.699326 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.356372 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24436799 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 42 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30929855 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30929855 # number of overall hits +system.cpu.dcache.ReadReq_misses 922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8047 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8949 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8949 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28002000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 288506000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 8969 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8969 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 27935000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 289776500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 316508000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 316508000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 24593002 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 317711500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 317711500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 24437721 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 47 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 31094105 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 31094105 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30938824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30938824 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001234 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.021277 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000288 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000288 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30207.119741 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35964.348043 # average WriteReq miss latency +system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.023256 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000290 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000290 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 30298.264642 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 36010.500808 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35367.974075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35367.974075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35423.291337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35423.291337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,73 +410,73 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 418 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6708 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6708 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks 106 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6315 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6731 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6731 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2241 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2241 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 2238 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2238 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 16310000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61605000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77836000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77836000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77915000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77915000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.021277 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.023256 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32043.222004 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35523.094688 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32233.201581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35568.706697 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34732.708612 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34732.708612 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2396.251917 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7647 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2399.023561 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7622 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3552 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.152872 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.145833 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2378.668231 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.583686 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072591 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2381.411279 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.612282 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072675 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7636 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 7611 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7661 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7661 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3484 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1708 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5192 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5192 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 119676500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59253000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 178929500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 178929500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 11120 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12853 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12853 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.313309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985574 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.403952 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.403952 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34350.315729 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34691.451991 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34462.538521 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34462.538521 # average overall miss latency +system.cpu.l2cache.demand_hits 7636 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7636 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3486 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5193 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5193 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119743000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59251500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 178994500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 178994500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11097 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12829 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12829 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.314139 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985566 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.404786 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.404786 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34349.684452 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34710.896309 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34468.419026 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34468.419026 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3484 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1708 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5192 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5192 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3486 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5193 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5193 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108359500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53860000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162219500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162219500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108417500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53859000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162276500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162276500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313309 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.403952 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.403952 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.037887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31533.957845 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31244.125578 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31244.125578 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314139 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.404786 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.404786 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100.831899 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31551.845343 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 788c735d8..00b76845b 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index e55be2152..c549133d9 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 04:01:57 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 19:41:03 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2 @@ -23,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 109591303500 because target called exit() +122 123 124 Exiting @ tick 108225133500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 9acd1c20e..0b4a9f9c5 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.109591 # Number of seconds simulated -sim_ticks 109591303500 # Number of ticks simulated +sim_seconds 0.108225 # Number of seconds simulated +sim_ticks 108225133500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60659 # Simulator instruction rate (inst/s) -host_tick_rate 35235152 # Simulator tick rate (ticks/s) -host_mem_usage 261736 # Number of bytes of host memory used -host_seconds 3110.28 # Real time elapsed on the host -sim_insts 188667697 # Number of instructions simulated +host_inst_rate 75904 # Simulator instruction rate (inst/s) +host_tick_rate 43540817 # Simulator tick rate (ticks/s) +host_mem_usage 267548 # Number of bytes of host memory used +host_seconds 2485.60 # Real time elapsed on the host +sim_insts 188667477 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 219182608 # number of cpu cycles simulated +system.cpu.numCycles 216450268 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103745786 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 81976338 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9943224 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 85671159 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80219991 # Number of BTB hits +system.cpu.BPredUnit.lookups 103300495 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 81633853 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9933179 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 85260221 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79838053 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4756853 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 113204 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 46114245 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429912188 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103745786 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84976844 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 111330567 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35270728 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36699969 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 813 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4770425 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 112925 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 45859797 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427202269 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103300495 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84608478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 110661906 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 34687559 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35479219 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 41935754 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2246100 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 219124425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.128247 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.665143 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 41734734 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2307922 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 216391705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.142578 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.666710 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108000297 49.29% 49.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5031394 2.30% 51.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33002073 15.06% 66.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18529573 8.46% 75.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9301462 4.24% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12648515 5.77% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8577033 3.91% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4456570 2.03% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19577508 8.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 105933481 48.95% 48.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4813111 2.22% 51.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32934004 15.22% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18446280 8.52% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9282990 4.29% 79.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12615981 5.83% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8571229 3.96% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4380123 2.02% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19414506 8.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 219124425 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.473330 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.961434 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 55048245 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35099276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102750817 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1404892 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24821195 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14312217 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 170214 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 436500086 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 694588 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 24821195 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 64323611 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 816730 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29228849 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 94788839 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5145201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 401098755 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 70910 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2783871 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 682579390 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1716423376 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1698124875 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18298501 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298062048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 384517342 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2790601 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2741243 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 25505966 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 51358732 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 18498661 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9149940 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5397480 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344257456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2323720 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266454796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 912087 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 155278627 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 378105702 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 688088 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 219124425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.215998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.473523 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 216391705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.477248 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.973674 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 54721006 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 34041868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102087484 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1309075 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24232272 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14250687 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 167114 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 433129762 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 697150 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 24232272 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63872072 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 611164 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28890421 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 94161740 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4624036 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 397542070 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 22398 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2387180 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 678079214 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1699552910 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1681277450 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 18275460 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298061696 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 380017513 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2786987 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2738977 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 24570466 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 49895918 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 17636120 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4759553 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2845254 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 339889742 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2325465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 265876001 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1090686 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 151055977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362148819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 689877 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 216391705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.228679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485743 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 102187705 46.63% 46.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 39549888 18.05% 64.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 35231696 16.08% 80.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 23077585 10.53% 91.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11566082 5.28% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4775373 2.18% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2189017 1.00% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 443166 0.20% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 103913 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 100636897 46.51% 46.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 38680237 17.88% 64.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34682486 16.03% 80.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22976662 10.62% 91.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11626624 5.37% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4959669 2.29% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2310222 1.07% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 416631 0.19% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 102277 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 219124425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 216391705 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 343002 18.52% 18.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6054 0.33% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 31 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 2 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 95 0.01% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1162999 62.81% 81.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 339535 18.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 400224 18.78% 18.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5529 0.26% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 59 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 41 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1248313 58.57% 77.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 477105 22.39% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 207547424 77.89% 77.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 926133 0.35% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 6207 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.01% 78.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166254 0.06% 78.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 259347 0.10% 78.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76101 0.03% 78.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 470014 0.18% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207509 0.08% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71627 0.03% 78.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 324 0.00% 78.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 42377903 15.90% 94.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14312934 5.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 206820187 77.79% 77.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 928873 0.35% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 5969 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33098 0.01% 78.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166620 0.06% 78.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 261178 0.10% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76402 0.03% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 472124 0.18% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207762 0.08% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71816 0.03% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 326 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 42647461 16.04% 94.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14184185 5.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266454796 # Type of FU issued -system.cpu.iq.rate 1.215675 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1851718 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 751012737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 499908383 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 246985878 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3785085 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2315100 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1843098 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266401517 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1904997 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1061099 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 265876001 # Type of FU issued +system.cpu.iq.rate 1.228347 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2131272 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008016 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 747569642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 491340043 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 245818526 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3796023 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2315934 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1850284 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266096231 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1911042 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1286575 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21507010 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7624 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 380760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5851790 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 20044239 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9909 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 389239 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4989293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 22 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 21 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24821195 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25209 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3025 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 346635263 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3972949 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 51358732 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 18498661 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2299792 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 339 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2453 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 380760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10016813 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1701165 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11717978 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 253656328 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 40286910 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12798468 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24232272 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29384 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2101 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 342268798 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4011941 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 49895918 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 17636120 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2301609 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 367 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1495 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 389239 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10042133 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1698405 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11740538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 252918304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 40460736 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12957697 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 54087 # number of nop insts executed -system.cpu.iew.exec_refs 54182001 # number of memory reference insts executed -system.cpu.iew.exec_branches 53130827 # Number of branches executed -system.cpu.iew.exec_stores 13895091 # Number of stores executed -system.cpu.iew.exec_rate 1.157283 # Inst execution rate -system.cpu.iew.wb_sent 250510965 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 248828976 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151533747 # num instructions producing a value -system.cpu.iew.wb_consumers 253038401 # num instructions consuming a value +system.cpu.iew.exec_nop 53591 # number of nop insts executed +system.cpu.iew.exec_refs 54201060 # number of memory reference insts executed +system.cpu.iew.exec_branches 52956495 # Number of branches executed +system.cpu.iew.exec_stores 13740324 # Number of stores executed +system.cpu.iew.exec_rate 1.168482 # Inst execution rate +system.cpu.iew.wb_sent 249352337 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 247668810 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150626342 # num instructions producing a value +system.cpu.iew.wb_consumers 251613909 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.135259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598857 # average fanout of values written-back +system.cpu.iew.wb_rate 1.144230 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598641 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188682085 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 157943841 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9804994 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 194303231 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.971070 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.635692 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188681865 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 153577683 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1635588 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9794361 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 192159434 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.981903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.655341 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109217628 56.21% 56.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 42594648 21.92% 78.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19958113 10.27% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8663175 4.46% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5049927 2.60% 95.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2103639 1.08% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1719455 0.88% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 826115 0.43% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4170531 2.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108154489 56.28% 56.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41572533 21.63% 77.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19548903 10.17% 88.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8803666 4.58% 92.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5118368 2.66% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2098797 1.09% 96.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1631204 0.85% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1005945 0.52% 97.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4225529 2.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 194303231 # Number of insts commited each cycle -system.cpu.commit.count 188682085 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 192159434 # Number of insts commited each cycle +system.cpu.commit.count 188681865 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498593 # Number of memory references committed -system.cpu.commit.loads 29851722 # Number of loads committed +system.cpu.commit.refs 42498505 # Number of memory references committed +system.cpu.commit.loads 29851678 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283920 # Number of branches committed +system.cpu.commit.branches 40283876 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115173 # Number of committed integer instructions. +system.cpu.commit.int_insts 150114997 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4170531 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4225529 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 536753425 # The number of ROB reads -system.cpu.rob.rob_writes 718144719 # The number of ROB writes -system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58183 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667697 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667697 # Number of Instructions Simulated -system.cpu.cpi 1.161739 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.161739 # CPI: Total CPI of All Threads -system.cpu.ipc 0.860779 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.860779 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1134129060 # number of integer regfile reads -system.cpu.int_regfile_writes 413088145 # number of integer regfile writes -system.cpu.fp_regfile_reads 2922495 # number of floating regfile reads -system.cpu.fp_regfile_writes 2493955 # number of floating regfile writes -system.cpu.misc_regfile_reads 519944359 # number of misc regfile reads -system.cpu.misc_regfile_writes 824510 # number of misc regfile writes -system.cpu.icache.replacements 1926 # number of replacements -system.cpu.icache.tagsinuse 1331.949680 # Cycle average of tags in use -system.cpu.icache.total_refs 41931510 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3631 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11548.198843 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 530188252 # The number of ROB reads +system.cpu.rob.rob_writes 708816282 # The number of ROB writes +system.cpu.timesIdled 1726 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58563 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667477 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667477 # Number of Instructions Simulated +system.cpu.cpi 1.147258 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.147258 # CPI: Total CPI of All Threads +system.cpu.ipc 0.871644 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.871644 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1130629656 # number of integer regfile reads +system.cpu.int_regfile_writes 411782000 # number of integer regfile writes +system.cpu.fp_regfile_reads 2929902 # number of floating regfile reads +system.cpu.fp_regfile_writes 2506543 # number of floating regfile writes +system.cpu.misc_regfile_reads 516287293 # number of misc regfile reads +system.cpu.misc_regfile_writes 824422 # number of misc regfile writes +system.cpu.icache.replacements 1945 # number of replacements +system.cpu.icache.tagsinuse 1331.549144 # Cycle average of tags in use +system.cpu.icache.total_refs 41730466 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3654 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11420.488779 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1331.949680 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.650366 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 41931510 # number of ReadReq hits -system.cpu.icache.demand_hits 41931510 # number of demand (read+write) hits -system.cpu.icache.overall_hits 41931510 # number of overall hits -system.cpu.icache.ReadReq_misses 4244 # number of ReadReq misses -system.cpu.icache.demand_misses 4244 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101763500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101763500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101763500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 41935754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 41935754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 41935754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000101 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23978.204524 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23978.204524 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23978.204524 # average overall miss latency +system.cpu.icache.occ_blocks::0 1331.549144 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.650170 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 41730466 # number of ReadReq hits +system.cpu.icache.demand_hits 41730466 # number of demand (read+write) hits +system.cpu.icache.overall_hits 41730466 # number of overall hits +system.cpu.icache.ReadReq_misses 4268 # number of ReadReq misses +system.cpu.icache.demand_misses 4268 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4268 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 101918000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 101918000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 101918000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 41734734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 41734734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 41734734 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23879.568885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23879.568885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23879.568885 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,139 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 613 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 613 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 613 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3631 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3631 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3631 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 614 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 614 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 614 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3654 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3654 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3654 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74668500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74668500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74668500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74785000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74785000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74785000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20564.169650 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20564.169650 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20564.169650 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000088 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20466.611932 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 54 # number of replacements -system.cpu.dcache.tagsinuse 1407.375528 # Cycle average of tags in use -system.cpu.dcache.total_refs 50844385 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1848 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27513.195346 # Average number of references to valid blocks. +system.cpu.dcache.replacements 53 # number of replacements +system.cpu.dcache.tagsinuse 1408.919446 # Cycle average of tags in use +system.cpu.dcache.total_refs 50759192 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1852 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27407.771058 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1407.375528 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343598 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 38435222 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356746 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27773 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24644 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 50791968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 50791968 # number of overall hits -system.cpu.dcache.ReadReq_misses 1795 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7541 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1408.919446 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343974 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 38350065 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27780 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24600 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 50706812 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 50706812 # number of overall hits +system.cpu.dcache.ReadReq_misses 1815 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9336 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9336 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59271500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236699500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 9355 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9355 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59756000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 236779500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 295971000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 295971000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 38437017 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 296535500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 296535500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 38351880 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27775 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 50801304 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 50801304 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 27782 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24600 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 50716167 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 50716167 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.000184 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000184 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33020.334262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31388.343721 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 32923.415978 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31403.116711 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31702.120823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31702.120823 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 31698.075895 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31698.075895 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1035 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 1051 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6452 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7488 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7488 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 760 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits 7503 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7503 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 764 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1088 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1848 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1848 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1852 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62524000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62524000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24358000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62603500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62603500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31946.710526 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35151.194853 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33833.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33833.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31882.198953 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35152.113971 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1932.871986 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1702 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2683 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.634365 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1935.489256 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1725 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2688 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.641741 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1929.817883 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.054103 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058893 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1932.435208 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.054049 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058973 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1702 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 1725 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1711 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1711 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2689 # number of ReadReq misses +system.cpu.l2cache.demand_hits 1734 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1734 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2693 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1079 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3768 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3768 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 92183000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37080500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129263500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129263500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4391 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 3772 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3772 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92325500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37082000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129407500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129407500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1088 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5479 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5479 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.612389 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 5506 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5506 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.609552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.991728 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.687717 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.687717 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34281.517293 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.616311 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34305.599788 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34305.599788 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.685071 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.685071 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34283.512811 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34367.006487 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34307.396607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34307.396607 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,27 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2680 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1079 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3754 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 3759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3759 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83139500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83299500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 33503500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116643000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116643000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116803000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116803000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.609201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606609 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991728 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.685162 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.685162 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.186916 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.682710 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.682710 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.902985 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.509731 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.656899 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.656899 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 733a1cda5..5bb467c35 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index fbdea3a95..7a3f808a7 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:01:24 -gem5 started Jul 15 2011 23:50:22 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 17:25:41 +gem5 started Aug 17 2011 17:43:51 +gem5 executing on nadc-0388 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105044494000 because target called exit() +122 123 124 Exiting @ tick 99831779000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index b774063aa..21b77f826 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105044 # Number of seconds simulated -sim_ticks 105044494000 # Number of ticks simulated +sim_seconds 0.099832 # Number of seconds simulated +sim_ticks 99831779000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56697 # Simulator instruction rate (inst/s) -host_tick_rate 26904511 # Simulator tick rate (ticks/s) -host_mem_usage 262296 # Number of bytes of host memory used -host_seconds 3904.35 # Real time elapsed on the host +host_inst_rate 87193 # Simulator instruction rate (inst/s) +host_tick_rate 39323014 # Simulator tick rate (ticks/s) +host_mem_usage 268152 # Number of bytes of host memory used +host_seconds 2538.76 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 210088989 # number of cpu cycles simulated +system.cpu.numCycles 199663559 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25906091 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25906091 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2877681 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23697798 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20934390 # Number of BTB hits +system.cpu.BPredUnit.lookups 26033375 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 26033375 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2892272 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23801635 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 21124617 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30843739 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 261974302 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25906091 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20934390 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70794160 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26721651 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 84571192 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 411 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28839529 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 526028 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 210002245 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.077492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.256338 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31432261 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 264493397 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26033375 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 21124617 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 71518034 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27440776 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72430048 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 173 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1577 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 29258071 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 583239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 199575786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.208704 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313982 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 141083594 67.18% 67.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4096564 1.95% 69.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3267465 1.56% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4473347 2.13% 72.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4273378 2.03% 74.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4452036 2.12% 76.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5454314 2.60% 79.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3065570 1.46% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39835977 18.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129959453 65.12% 65.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4150455 2.08% 67.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3286315 1.65% 68.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4425223 2.22% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4327377 2.17% 73.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4568651 2.29% 75.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5572926 2.79% 78.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3068408 1.54% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 40216978 20.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 210002245 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123310 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.246968 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45814663 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73297000 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 55964774 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11133134 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23792674 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 424975722 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23792674 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54914820 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 20522213 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23840 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57109649 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53639049 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 413573068 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30245146 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20822120 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 438852783 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1070324075 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1058519342 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11804733 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 199575786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.324695 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45674333 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62083287 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 57427578 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10196895 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24193693 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 428380569 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24193693 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54435501 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16645801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21737 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 58104790 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46174264 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 415835044 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 22459451 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 21291992 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 441873091 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1077088979 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1065665407 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11423572 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 204489374 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1468 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1462 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108174037 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105166977 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38036544 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 93207180 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32406467 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 401191410 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1447 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 281389101 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 88945 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 179610706 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 379681728 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 210002245 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.339934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.371545 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 207509682 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1829 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1823 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 98204521 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105334480 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37821412 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 75455534 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24783352 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 400833570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1827 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 286380326 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 245766 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 179000562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 366769994 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 581 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 199575786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.434945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.451491 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69597365 33.14% 33.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 64957213 30.93% 64.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36846366 17.55% 81.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20444772 9.74% 91.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11872646 5.65% 97.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4318388 2.06% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1525465 0.73% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 350714 0.17% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 89316 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64436357 32.29% 32.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 57784347 28.95% 61.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35429830 17.75% 78.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21049464 10.55% 89.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13197205 6.61% 96.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5079102 2.54% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1923482 0.96% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 545287 0.27% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130712 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 210002245 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 199575786 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 107872 3.66% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2450287 83.09% 86.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 390701 13.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 94614 3.23% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2515029 85.77% 88.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 322713 11.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1204241 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187252248 66.55% 66.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1588066 0.56% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67629899 24.03% 91.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23714647 8.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1207901 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187612443 65.51% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1650340 0.58% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 71566969 24.99% 91.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 24342673 8.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281389101 # Type of FU issued -system.cpu.iq.rate 1.339381 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2948860 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770610110 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 574654249 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 273620025 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5208142 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 6216706 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2514026 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 280509716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2624004 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 16305906 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 286380326 # Type of FU issued +system.cpu.iq.rate 1.434314 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2932356 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010239 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770019302 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 574569480 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 277218966 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5495258 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 5820238 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2640122 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 285339093 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2765688 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17496370 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48517387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5787 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 69063 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17520828 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 48684890 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26476 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 567154 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17305696 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45289 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45677 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23792674 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 691646 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 425399 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 401192857 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 138630 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105166977 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38036544 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1447 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 309021 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40843 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 69063 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2486335 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578919 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3065254 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 278324671 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66381551 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3064430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24193693 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 457791 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 303468 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 400835397 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134633 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105334480 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37821412 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1827 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 212810 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14667 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 567154 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2502429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 590366 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3092795 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 282646911 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 70091222 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3733415 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89772300 # number of memory reference insts executed -system.cpu.iew.exec_branches 15687599 # Number of branches executed -system.cpu.iew.exec_stores 23390749 # Number of stores executed -system.cpu.iew.exec_rate 1.324794 # Inst execution rate -system.cpu.iew.wb_sent 277184129 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 276134051 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222355020 # num instructions producing a value -system.cpu.iew.wb_consumers 373725319 # num instructions consuming a value +system.cpu.iew.exec_refs 93958027 # number of memory reference insts executed +system.cpu.iew.exec_branches 15691329 # Number of branches executed +system.cpu.iew.exec_stores 23866805 # Number of stores executed +system.cpu.iew.exec_rate 1.415616 # Inst execution rate +system.cpu.iew.wb_sent 281113586 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 279859088 # cumulative count of insts written-back +system.cpu.iew.wb_producers 226653177 # num instructions producing a value +system.cpu.iew.wb_consumers 377782482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.314367 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.594969 # average fanout of values written-back +system.cpu.iew.wb_rate 1.401653 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.599957 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 179841994 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 179482154 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2877741 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 186209571 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.188784 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.542023 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2892451 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 175382093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.262176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.674972 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71071645 38.17% 38.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70044936 37.62% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18344188 9.85% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12667816 6.80% 92.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5471591 2.94% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2983054 1.60% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2040122 1.10% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1105861 0.59% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2480358 1.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66614816 37.98% 37.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 64778126 36.94% 74.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16236292 9.26% 84.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12183178 6.95% 91.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5701402 3.25% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3006065 1.71% 96.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2037233 1.16% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1096406 0.63% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3728575 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 186209571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 175382093 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2480358 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3728575 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 584934224 # The number of ROB reads -system.cpu.rob.rob_writes 826225881 # The number of ROB writes -system.cpu.timesIdled 1865 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 86744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 572498689 # The number of ROB reads +system.cpu.rob.rob_writes 825932723 # The number of ROB writes +system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 87773 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.949070 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.949070 # CPI: Total CPI of All Threads -system.cpu.ipc 1.053663 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.053663 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515807985 # number of integer regfile reads -system.cpu.int_regfile_writes 284258767 # number of integer regfile writes -system.cpu.fp_regfile_reads 3504419 # number of floating regfile reads -system.cpu.fp_regfile_writes 2170248 # number of floating regfile writes -system.cpu.misc_regfile_reads 144660799 # number of misc regfile reads +system.cpu.cpi 0.901973 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.901973 # CPI: Total CPI of All Threads +system.cpu.ipc 1.108680 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.108680 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 526429192 # number of integer regfile reads +system.cpu.int_regfile_writes 287807377 # number of integer regfile writes +system.cpu.fp_regfile_reads 3610412 # number of floating regfile reads +system.cpu.fp_regfile_writes 2295659 # number of floating regfile writes +system.cpu.misc_regfile_reads 148624711 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4219 # number of replacements -system.cpu.icache.tagsinuse 1625.397975 # Cycle average of tags in use -system.cpu.icache.total_refs 28832382 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6182 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4663.924620 # Average number of references to valid blocks. +system.cpu.icache.replacements 4242 # number of replacements +system.cpu.icache.tagsinuse 1597.360420 # Cycle average of tags in use +system.cpu.icache.total_refs 29250473 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6209 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4710.979707 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1625.397975 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.793651 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28832382 # number of ReadReq hits -system.cpu.icache.demand_hits 28832382 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28832382 # number of overall hits -system.cpu.icache.ReadReq_misses 7147 # number of ReadReq misses -system.cpu.icache.demand_misses 7147 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7147 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 169208500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 169208500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 169208500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28839529 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28839529 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28839529 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000248 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000248 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000248 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23675.458234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23675.458234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23675.458234 # average overall miss latency +system.cpu.icache.occ_blocks::0 1597.360420 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.779961 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 29250474 # number of ReadReq hits +system.cpu.icache.demand_hits 29250474 # number of demand (read+write) hits +system.cpu.icache.overall_hits 29250474 # number of overall hits +system.cpu.icache.ReadReq_misses 7597 # number of ReadReq misses +system.cpu.icache.demand_misses 7597 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7597 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 175067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 175067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 175067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 29258071 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 29258071 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 29258071 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23044.293800 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23044.293800 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23044.293800 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 961 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 961 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 961 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6186 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6186 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6186 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1135 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1135 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1135 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6462 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6462 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6462 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125111000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125815000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125815000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125815000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000214 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000214 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000214 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20224.862593 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20224.862593 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20224.862593 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19469.978335 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 49 # number of replacements -system.cpu.dcache.tagsinuse 1408.251063 # Cycle average of tags in use -system.cpu.dcache.total_refs 70379715 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1964 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 35834.885438 # Average number of references to valid blocks. +system.cpu.dcache.replacements 58 # number of replacements +system.cpu.dcache.tagsinuse 1414.389130 # Cycle average of tags in use +system.cpu.dcache.total_refs 72873832 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1985 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36712.257935 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1408.251063 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343811 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 49871091 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20508613 # number of WriteReq hits -system.cpu.dcache.demand_hits 70379704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 70379704 # number of overall hits -system.cpu.dcache.ReadReq_misses 713 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7117 # number of WriteReq misses -system.cpu.dcache.demand_misses 7830 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 7830 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 23577500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 188115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 211693000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 211693000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 49871804 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1414.389130 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.345310 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 52365835 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20507475 # number of WriteReq hits +system.cpu.dcache.demand_hits 72873310 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 72873310 # number of overall hits +system.cpu.dcache.ReadReq_misses 884 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8255 # number of WriteReq misses +system.cpu.dcache.demand_misses 9139 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9139 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 27524500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 227342500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 254867000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 254867000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 52366719 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 70387534 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 70387534 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33068.022440 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 26431.853309 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27036.143040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27036.143040 # average overall miss latency +system.cpu.dcache.demand_accesses 72882449 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 72882449 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31136.312217 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27539.975772 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27887.843309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27887.843309 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,72 +369,72 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 311 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 5551 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5862 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5862 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 402 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1968 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1968 # number of overall MSHR misses +system.cpu.dcache.writebacks 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 460 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6439 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6899 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6899 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1816 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13701000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 55004000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 68705000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 68705000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 63530000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77603500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77603500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34082.089552 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35123.882503 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34911.077236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34911.077236 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33192.216981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34983.480176 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2496.142499 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2832 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3755 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.754194 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2508.886918 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2866 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3770 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.760212 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2495.127708 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014791 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076145 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2832 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2838 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2838 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3751 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128522000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53234000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 181756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 181756000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6583 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 4 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8146 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8146 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.569801 # miss rate for ReadReq accesses +system.cpu.l2cache.occ_blocks::0 2507.064055 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.822864 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076510 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000056 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2865 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2873 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2873 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3766 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 253 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5322 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5322 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128966500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53203000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 182169500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 182169500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 253 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1564 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8195 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8195 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.567938 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.996161 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.651608 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.651608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34263.396428 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34190.109184 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34241.899020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34241.899020 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.994885 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.649420 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.649420 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34244.954859 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.159383 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34229.518978 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34229.518978 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3751 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5308 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3766 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 253 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5322 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5322 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116406500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48370500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 164777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 164777000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116813500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7843000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48344500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 165158000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 165158000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.569801 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567938 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.651608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.651608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31033.457745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.649420 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.649420 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.923526 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31066.473988 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.142427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.142427 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.730077 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |