diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-06 21:53:57 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-06 21:53:57 -0600 |
commit | c0618198908b592ff0c165b671cb5d8d785d83ca (patch) | |
tree | 96b98dbf6262a9f417c7d53ef59c09ff56018e2c /tests | |
parent | e8802fa127f5a446e708eb9f7ce8509e850bf699 (diff) | |
download | gem5-c0618198908b592ff0c165b671cb5d8d785d83ca.tar.xz |
ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
Diffstat (limited to 'tests')
-rw-r--r-- | tests/configs/memtest-ruby.py | 10 | ||||
-rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 3 | ||||
-rw-r--r-- | tests/configs/rubytest-ruby.py | 8 | ||||
-rw-r--r-- | tests/configs/simple-timing-ruby.py | 2 |
4 files changed, 7 insertions, 16 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 397e9f0c7..a252bc881 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -79,8 +79,8 @@ options.num_cpus = nb_cores # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), - physmem = SimpleMemory()) + physmem = SimpleMemory(null = True), + funcbus = NoncoherentBus()) Ruby.create_system(options, system) @@ -100,12 +100,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): # ruby_port.deadlock_threshold = 1000000 - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # connect reference memory to funcbus system.funcmem.port = system.funcbus.master diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 0753472bc..23a0bb3d0 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -74,5 +74,8 @@ for (i, cpu) in enumerate(system.cpu): cpu.interrupts.int_slave = system.piobus.master cpu.clock = '2GHz' + # Set access_phys_mem to True for ruby port + system.ruby._cpu_ruby_ports[i].access_phys_mem = True + root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index 4b5b3a19c..861205acc 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -77,7 +77,7 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer': tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, wakeup_frequency = 10, num_cpus = options.num_cpus) -system = System(tester = tester, physmem = SimpleMemory()) +system = System(tester = tester, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system) @@ -104,12 +104,6 @@ for ruby_port in system.ruby._cpu_ruby_ports: # ruby_port.using_ruby_tester = True - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 86869452a..41b4fdb1f 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -67,7 +67,7 @@ options.l3_assoc=2 options.num_cpus = 1 cpu = TimingSimpleCPU(cpu_id=0) -system = System(cpu = cpu, physmem = SimpleMemory()) +system = System(cpu = cpu, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system) |