diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-11-08 20:15:23 -0800 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-11-08 20:15:23 -0800 |
| commit | 14b51697500b71a05c67c8197c017cb6a39b57a7 (patch) | |
| tree | c32155000160acd3f350cb8a71d4c19787be9bc5 /tests | |
| parent | 708faa767763e65a2fded8aa33ac3c63cca9c84c (diff) | |
| download | gem5-14b51697500b71a05c67c8197c017cb6a39b57a7.tar.xz | |
tests: update statistics for change caused by vsyscall support in x86
Caused by a slight change in memory layout.
Diffstat (limited to 'tests')
15 files changed, 505 insertions, 520 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 033ea4c68..0c81e9129 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +79,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +113,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 7e3ef4fb7..8936a6094 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Nov 8 2009 16:16:58 +M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff +M5 started Nov 8 2009 16:32:22 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1814896735000 because target called exit() +Exiting @ tick 1814726932000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 574e2f381..60806dc72 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 989143 # Simulator instruction rate (inst/s) -host_mem_usage 205900 # Number of bytes of host memory used -host_seconds 1637.14 # Real time elapsed on the host -host_tick_rate 1108576660 # Simulator tick rate (ticks/s) +host_inst_rate 1181561 # Simulator instruction rate (inst/s) +host_mem_usage 194380 # Number of bytes of host memory used +host_seconds 1370.53 # Real time elapsed on the host +host_tick_rate 1324103876 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619366736 # Number of instructions simulated -sim_seconds 1.814897 # Number of seconds simulated -sim_ticks 1814896735000 # Number of ticks simulated +sim_seconds 1.814727 # Number of seconds simulated +sim_ticks 1814726932000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20939.027041 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17939.027041 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418844309 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4141928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 197809 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3548501000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000472 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197809 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency 20884.820230 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17884.820230 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 418844783 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4121306000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 197335 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3529301000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 197335 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187873910 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17480176000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001659 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 312146 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16543738000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001659 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 312146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 187876631 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17327800000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001644 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 309425 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16399525000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001644 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 309425 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1364.014744 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1372.614288 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42400.023531 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606718219 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21622104000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000840 # miss rate for demand accesses -system.cpu.dcache.demand_misses 509955 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 42325.964954 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606721414 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21449106000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000835 # miss rate for demand accesses +system.cpu.dcache.demand_misses 506760 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20092239000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000840 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 509955 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 19928826000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000835 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 506760 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42400.023531 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 42325.964954 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606718219 # number of overall hits -system.cpu.dcache.overall_miss_latency 21622104000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000840 # miss rate for overall accesses -system.cpu.dcache.overall_misses 509955 # number of overall misses +system.cpu.dcache.overall_hits 606721414 # number of overall hits +system.cpu.dcache.overall_miss_latency 21449106000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000835 # miss rate for overall accesses +system.cpu.dcache.overall_misses 506760 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20092239000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000840 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 509955 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 19928826000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000835 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 506760 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 440755 # number of replacements -system.cpu.dcache.sampled_refs 444851 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 437970 # number of replacements +system.cpu.dcache.sampled_refs 442066 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.900211 # Cycle average of tags in use -system.cpu.dcache.total_refs 606783323 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.901154 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786108 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 779430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 308934 # number of writebacks +system.cpu.dcache.writebacks 306212 # number of writebacks system.cpu.icache.ReadReq_accesses 1186516703 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -120,86 +120,86 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 660.162690 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.164909 # Cycle average of tags in use system.cpu.icache.total_refs 1186515981 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 247042 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 244731 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12846184000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 12726012000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247042 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9881680000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 244731 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9789240000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247042 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 198531 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 244731 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 198057 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 165128 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1736956000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.168251 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33403 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1336120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.168251 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33403 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 65104 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 164987 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1719640000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.166972 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33070 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1322800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166972 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33070 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 64694 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3385408000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3364088000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 65104 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2604160000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 64694 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587760000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 65104 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 308934 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 308934 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 64694 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 306212 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 306212 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.437895 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.429569 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 445573 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 442788 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 165128 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14583140000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.629403 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 280445 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 164987 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14445652000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.627391 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 277801 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11217800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.629403 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 280445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11112040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.627391 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 277801 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 445573 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 442788 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 165128 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14583140000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.629403 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 280445 # number of overall misses +system.cpu.l2cache.overall_hits 164987 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14445652000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.627391 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 277801 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11217800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.629403 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 280445 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11112040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.627391 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 277801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 82239 # number of replacements -system.cpu.l2cache.sampled_refs 97729 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 81543 # number of replacements +system.cpu.l2cache.sampled_refs 97060 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16489.401861 # Cycle average of tags in use -system.cpu.l2cache.total_refs 335982 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16545.401704 # Cycle average of tags in use +system.cpu.l2cache.total_refs 332874 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61724 # number of writebacks +system.cpu.l2cache.writebacks 61555 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3629793470 # number of cpu cycles simulated +system.cpu.numCycles 3629453864 # number of cpu cycles simulated system.cpu.num_insts 1619366736 # Number of instructions executed system.cpu.num_refs 607228174 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index 40547fe1c..c90ba3ccf 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +79,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +113,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -152,7 +149,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 2a93c45ae..035c663f2 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 17 2009 20:29:57 -M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch -M5 started Aug 17 2009 20:30:53 -M5 executing on tater -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +M5 compiled Nov 8 2009 16:16:58 +M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff +M5 started Nov 8 2009 16:34:05 +M5 executing on maize +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 381620562000 because target called exit() +Exiting @ tick 382091472000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index a882827d5..b582ff405 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 395133 # Simulator instruction rate (inst/s) -host_mem_usage 355296 # Number of bytes of host memory used -host_seconds 682.55 # Real time elapsed on the host -host_tick_rate 559113861 # Simulator tick rate (ticks/s) +host_inst_rate 839358 # Simulator instruction rate (inst/s) +host_mem_usage 328912 # Number of bytes of host memory used +host_seconds 321.31 # Real time elapsed on the host +host_tick_rate 1189158712 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269695959 # Number of instructions simulated -sim_seconds 0.381621 # Number of seconds simulated -sim_ticks 381620562000 # Number of ticks simulated +sim_seconds 0.382091 # Number of seconds simulated +sim_ticks 382091472000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency 15892.729148 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12892.729148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 88818985 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 31157028000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.021596 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1960458 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 25275654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.021596 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1960458 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 56000.038268 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.038268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31204566 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 13170313000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007480 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 235184 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 12464761000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 235184 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 58.134189 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency -system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 20188.783508 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17188.783508 # average overall mshr miss latency +system.cpu.dcache.demand_hits 120023551 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 44327341000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.017965 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2195642 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 37740415000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.017965 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2195642 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 20188.783508 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17188.783508 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 120039828 # number of overall hits -system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2179365 # number of overall misses +system.cpu.dcache.overall_hits 120023551 # number of overall hits +system.cpu.dcache.overall_miss_latency 44327341000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.017965 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2195642 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 37740415000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.017965 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2195642 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2049944 # number of replacements -system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2062715 # number of replacements +system.cpu.dcache.sampled_refs 2066811 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.426853 # Cycle average of tags in use -system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 127225673000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 229129 # number of writebacks +system.cpu.dcache.tagsinuse 4077.137530 # Cycle average of tags in use +system.cpu.dcache.total_refs 120152382 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 127457925000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 235136 # number of writebacks system.cpu.icache.ReadReq_accesses 217696172 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -120,86 +120,86 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 667.511289 # Cycle average of tags in use +system.cpu.icache.tagsinuse 667.480800 # Cycle average of tags in use system.cpu.icache.total_refs 217695364 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_accesses 106353 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.291482 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5530387000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 106353 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4254120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1950996 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 106353 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1961266 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 4627428000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 88989 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3559560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 88989 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 1872110 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 4636112000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.045458 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 89156 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3566240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045458 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 89156 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 128831 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51991.120150 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 6698068000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 128831 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5153240000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 128831 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 235136 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 235136 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 13.678118 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 13.775269 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2054848 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.160754 # average overall miss latency +system.cpu.l2cache.demand_accesses 2067619 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000.158560 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10027763000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.093847 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 192841 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1872110 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10166499000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.094558 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 195509 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 7713640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.093847 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 192841 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 7820360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.094558 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 195509 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 2054848 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.160754 # average overall miss latency +system.cpu.l2cache.overall_accesses 2067619 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000.158560 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1862007 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10027763000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.093847 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 192841 # number of overall misses +system.cpu.l2cache.overall_hits 1872110 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10166499000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.094558 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 195509 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 7713640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.093847 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 192841 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 7820360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.094558 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 195509 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 108886 # number of replacements -system.cpu.l2cache.sampled_refs 132828 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 109056 # number of replacements +system.cpu.l2cache.sampled_refs 132990 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18003.313178 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18001.651383 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1831973 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 70892 # number of writebacks +system.cpu.l2cache.writebacks 70891 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 763241124 # number of cpu cycles simulated +system.cpu.numCycles 764182944 # number of cpu cycles simulated system.cpu.num_insts 269695959 # Number of instructions executed system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 5f5b1b01c..a7ed66f8a 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +79,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +113,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index a5dbe2b41..a11db4e1e 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Nov 8 2009 16:16:58 +M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff +M5 started Nov 8 2009 16:39:28 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1722352562000 because target called exit() +Exiting @ tick 1722331568000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index c62dd0754..0e665b6ef 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,84 +1,84 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 924480 # Simulator instruction rate (inst/s) -host_mem_usage 209588 # Number of bytes of host memory used -host_seconds 1617.88 # Real time elapsed on the host -host_tick_rate 1064572030 # Simulator tick rate (ticks/s) +host_inst_rate 1459378 # Simulator instruction rate (inst/s) +host_mem_usage 198104 # Number of bytes of host memory used +host_seconds 1024.89 # Real time elapsed on the host +host_tick_rate 1680505604 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495700470 # Number of instructions simulated -sim_seconds 1.722353 # Number of seconds simulated -sim_ticks 1722352562000 # Number of ticks simulated +sim_seconds 1.722332 # Number of seconds simulated +sim_ticks 1722331568000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 382375369 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency 24153.691272 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21153.690114 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 382374810 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 41722410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1727372 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 36540292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1727372 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 147694052 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 55999.912307 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912307 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147694869 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 82058407500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009824 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1465331 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 77662414500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1465331 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 210.782575 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 210.745406 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency -system.cpu.dcache.demand_hits 530069421 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 38769.912986 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency +system.cpu.dcache.demand_hits 530069679 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 123780817500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005987 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3192703 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 114202706500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 3192703 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 38769.912986 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 530069421 # number of overall hits -system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3192961 # number of overall misses +system.cpu.dcache.overall_hits 530069679 # number of overall hits +system.cpu.dcache.overall_miss_latency 123780817500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005987 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3192703 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 114202706500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 3192703 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2513875 # number of replacements -system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2514317 # number of replacements +system.cpu.dcache.sampled_refs 2518413 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.831173 # Cycle average of tags in use -system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8217762000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1463913 # number of writebacks +system.cpu.dcache.tagsinuse 4086.814341 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743969 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8217895000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1463113 # number of writebacks system.cpu.icache.ReadReq_accesses 1068347073 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 48417.910448 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 45417.910448 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1068344259 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 136248000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 136836000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 127806000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 128394000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -90,29 +90,29 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1068347073 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 48417.910448 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 45417.910448 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 48626.865672 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency system.cpu.icache.demand_hits 1068344259 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 136248000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 136836000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 127806000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 128394000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 48417.910448 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 45417.910448 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1068344259 # number of overall hits -system.cpu.icache.overall_miss_latency 136248000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 136836000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.icache.overall_misses 2814 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 127806000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 128394000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -120,86 +120,86 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 887.487990 # Cycle average of tags in use +system.cpu.icache.tagsinuse 887.538461 # Cycle average of tags in use system.cpu.icache.total_refs 1068344259 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_accesses 791041 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 41134143500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 791041 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641640000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1729627 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 791041 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1730186 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21815196000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 419523 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16780920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 419523 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 1310266 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 21835840000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.242702 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 419920 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 16796800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 419920 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 674290 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.203458 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 35055800000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 674290 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26971600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 674290 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1463113 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1463113 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.428066 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.423900 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2520785 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.demand_accesses 2521227 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000.009497 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 62955423500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1210681 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1310266 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 62969983500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.480306 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1210961 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 48427240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1210681 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 48438440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.480306 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1210961 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 2520785 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency +system.cpu.l2cache.overall_accesses 2521227 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1310104 # number of overall hits -system.cpu.l2cache.overall_miss_latency 62955423500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1210681 # number of overall misses +system.cpu.l2cache.overall_hits 1310266 # number of overall hits +system.cpu.l2cache.overall_miss_latency 62969983500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.480306 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1210961 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 48427240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1210681 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 48438440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.480306 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1210961 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 663513 # number of replacements -system.cpu.l2cache.sampled_refs 679921 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 664073 # number of replacements +system.cpu.l2cache.sampled_refs 680479 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17216.037197 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 921771494000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 481430 # number of writebacks +system.cpu.l2cache.tagsinuse 17213.177564 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2329892 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 921652677000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 481653 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3444705124 # number of cpu cycles simulated +system.cpu.numCycles 3444663136 # number of cpu cycles simulated system.cpu.num_insts 1495700470 # Number of instructions executed system.cpu.num_refs 533262337 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index 2985d5b21..d5c949c6e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +79,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +113,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index ea6185a03..8e0139bb7 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:13:11 -M5 executing on tater +M5 compiled Nov 8 2009 16:16:58 +M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff +M5 started Nov 8 2009 16:30:56 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5988064038000 because target called exit() +Exiting @ tick 5988037845000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 129e4b866..ffd34c1e6 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1178978 # Simulator instruction rate (inst/s) -host_mem_usage 205796 # Number of bytes of host memory used -host_seconds 3946.92 # Real time elapsed on the host -host_tick_rate 1517149915 # Simulator tick rate (ticks/s) +host_inst_rate 1485872 # Simulator instruction rate (inst/s) +host_mem_usage 194272 # Number of bytes of host memory used +host_seconds 3131.72 # Real time elapsed on the host +host_tick_rate 1912063349 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653327894 # Number of instructions simulated -sim_seconds 5.988064 # Number of seconds simulated -sim_ticks 5988064038000 # Number of ticks simulated +sim_seconds 5.988038 # Number of seconds simulated +sim_ticks 5988037845000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency 25018.463901 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22018.463901 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1231962487 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 180689726000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.005828 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7222255 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 159022961000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005828 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7222255 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55999.840680 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.840680 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 436281288 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 125834330000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 2247048 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 119093186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2247048 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 183.121439 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 32370.287021 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1668243775 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 306524056000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005644 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9469303 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 278116147000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005644 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9469303 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 32370.287021 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1668242528 # number of overall hits -system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9470550 # number of overall misses +system.cpu.dcache.overall_hits 1668243775 # number of overall hits +system.cpu.dcache.overall_miss_latency 306524056000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005644 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9469303 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 278116147000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005644 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9469303 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9108982 # number of replacements -system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9107896 # number of replacements +system.cpu.dcache.sampled_refs 9111992 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.778553 # Cycle average of tags in use -system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58863931000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244013 # number of writebacks +system.cpu.dcache.tagsinuse 4084.774232 # Cycle average of tags in use +system.cpu.dcache.total_refs 1668601086 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 58863918000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2243955 # number of writebacks system.cpu.icache.ReadReq_accesses 4013232890 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -120,86 +120,86 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.573306 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.573148 # Cycle average of tags in use system.cpu.icache.total_refs 4013232215 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1889737 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 98266324000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1889737 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 75589480000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 1889737 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7222930 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 5327537 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 98560436000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.262413 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1895393 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 75815720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262413 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1895393 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 357311 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.899729 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 18561556000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 357311 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14292440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 357311 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2243955 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2243955 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.380966 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 9112667 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5327537 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 196826760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415370 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3785130 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 151405200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3785130 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 9112667 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5328546 # number of overall hits -system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3785207 # number of overall misses +system.cpu.l2cache.overall_hits 5327537 # number of overall hits +system.cpu.l2cache.overall_miss_latency 196826760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415370 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3785130 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 151405200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3785130 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2772128 # number of replacements -system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2771977 # number of replacements +system.cpu.l2cache.sampled_refs 2798150 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25742.940388 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4737814312000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1199171 # number of writebacks +system.cpu.l2cache.tagsinuse 25743.015890 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6662299 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4737770578000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1199166 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11976128076 # number of cpu cycles simulated +system.cpu.numCycles 11976075690 # number of cpu cycles simulated system.cpu.num_insts 4653327894 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index f70defe2b..6cbe3be3b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +79,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +113,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -152,7 +149,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index cfb8745b2..32ad08600 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 17 2009 20:29:57 -M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch -M5 started Aug 17 2009 20:42:16 -M5 executing on tater -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +M5 compiled Nov 8 2009 16:16:58 +M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff +M5 started Nov 8 2009 16:37:25 +M5 executing on maize +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +27,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250961789000 because target called exit() +122 123 124 Exiting @ tick 250962019000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index d0361bdaa..96e63da4b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,84 +1,84 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 489241 # Simulator instruction rate (inst/s) -host_mem_usage 228040 # Number of bytes of host memory used -host_seconds 448.51 # Real time elapsed on the host -host_tick_rate 559541126 # Simulator tick rate (ticks/s) +host_inst_rate 894535 # Simulator instruction rate (inst/s) +host_mem_usage 201656 # Number of bytes of host memory used +host_seconds 245.30 # Real time elapsed on the host +host_tick_rate 1023073835 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 219430973 # Number of instructions simulated sim_seconds 0.250962 # Number of seconds simulated -sim_ticks 250961789000 # Number of ticks simulated +sim_ticks 250962019000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56682001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 56681682 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 55228.395062 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52226.851852 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 56681677 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 17894000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 16921500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_hits 20514125 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 89824000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 1604 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 85012000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1604 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40758.097149 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40586.660358 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 77197730 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency -system.cpu.dcache.demand_hits 77195810 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 55870.331950 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52870.072614 # average overall mshr miss latency +system.cpu.dcache.demand_hits 77195802 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 107718000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1928 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 101933500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1928 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 77197730 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55870.331950 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52870.072614 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 77195810 # number of overall hits -system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles +system.cpu.dcache.overall_hits 77195802 # number of overall hits +system.cpu.dcache.overall_miss_latency 107718000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1920 # number of overall misses +system.cpu.dcache.overall_misses 1928 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 101933500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1928 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 27 # number of replacements -system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 40 # number of replacements +system.cpu.dcache.sampled_refs 1902 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.582472 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195836 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1361.446792 # Cycle average of tags in use +system.cpu.dcache.total_refs 77195828 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2 # number of writebacks +system.cpu.dcache.writebacks 7 # number of writebacks system.cpu.icache.ReadReq_accesses 173494375 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 39420.962931 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.252237 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 173489681 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 185042000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 170928500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -90,29 +90,29 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 173494375 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 39420.962931 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36414.252237 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency system.cpu.icache.demand_hits 173489681 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 185042000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 170928500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 173494375 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 39420.962931 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36414.252237 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 173489681 # number of overall hits -system.cpu.icache.overall_miss_latency 185042000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses system.cpu.icache.overall_misses 4694 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 170928500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -120,29 +120,29 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 2836 # number of replacements system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1455.283776 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.283940 # Cycle average of tags in use system.cpu.icache.total_refs 173489681 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 82056000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1578 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 63120000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5013 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52005.066498 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 1578 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5018 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52004.908170 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 164232000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.629962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_hits 1860 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 164231500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.629334 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3158 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 126320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629334 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3158 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency @@ -153,53 +153,53 @@ system.cpu.l2cache.UpgradeReq_misses 26 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits +system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.591895 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.593112 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 6588 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52003.380520 # average overall miss latency +system.cpu.l2cache.demand_accesses 6596 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52003.272804 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 246132000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.718427 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4733 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 1860 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 246287500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.718011 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4736 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 189320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.718427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4733 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 189440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.718011 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4736 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 6588 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52003.380520 # average overall miss latency +system.cpu.l2cache.overall_accesses 6596 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52003.272804 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1855 # number of overall hits -system.cpu.l2cache.overall_miss_latency 246132000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.718427 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4733 # number of overall misses +system.cpu.l2cache.overall_hits 1860 # number of overall hits +system.cpu.l2cache.overall_miss_latency 246287500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.718011 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4736 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 189320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.718427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4733 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 189440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.718011 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4736 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3134 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3136 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2033.146295 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2033.169065 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1860 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 501923578 # number of cpu cycles simulated +system.cpu.numCycles 501924038 # number of cpu cycles simulated system.cpu.num_insts 219430973 # Number of instructions executed system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls |