diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests')
74 files changed, 24603 insertions, 24635 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 14c60d4c9..05077073e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,244 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.867374 # Number of seconds simulated -sim_ticks 1867373908500 # Number of ticks simulated -final_tick 1867373908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.855236 # Number of seconds simulated +sim_ticks 1855236450500 # Number of ticks simulated +final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123272 # Simulator instruction rate (inst/s) -host_op_rate 123272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4349339718 # Simulator tick rate (ticks/s) -host_mem_usage 299108 # Number of bytes of host memory used -host_seconds 429.35 # Real time elapsed on the host -sim_insts 52926469 # Number of instructions simulated -sim_ops 52926469 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory +host_inst_rate 87142 # Simulator instruction rate (inst/s) +host_op_rate 87142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3050446700 # Simulator tick rate (ticks/s) +host_mem_usage 299400 # Number of bytes of host memory used +host_seconds 608.19 # Real time elapsed on the host +sim_insts 52998368 # Number of instructions simulated +sim_ops 52998368 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28501568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7518720 # Number of bytes written to this memory -system.physmem.bytes_written::total 7518720 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory +system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445337 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117480 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117480 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13323249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1420330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15262914 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4026360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4026360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4026360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 338398 # number of replacements -system.cpu.l2cache.tagsinuse 65348.140689 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2559915 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403567 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.343222 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997133 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1835554 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 841020 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 841020 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185546 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185546 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1007783 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1013317 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2021100 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1007783 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1013317 # number of overall hits -system.cpu.l2cache.overall_hits::total 2021100 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15155 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273854 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 289009 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 54 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 54 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15155 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389249 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404404 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15155 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389249 # number of overall misses -system.cpu.l2cache.overall_misses::total 404404 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 807128998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14259763500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15066892498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 376500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 376500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6225363497 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6225363497 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 807128998 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20485126997 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21292255995 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 807128998 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20485126997 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21292255995 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1022938 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1101625 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2124563 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 841020 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 841020 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1022938 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1402566 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2425504 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1022938 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1402566 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2425504 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248591 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136032 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.635294 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.635294 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383447 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383447 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014815 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277526 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166730 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014815 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277526 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166730 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6972.222222 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6972.222222 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75968 # number of writebacks -system.cpu.l2cache.writebacks::total 75968 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15154 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273854 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289008 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 54 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 54 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15154 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389249 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404403 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15154 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389249 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404403 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 621904998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10983272500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11605177498 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2245000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2245000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4831334497 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4831334497 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 621904998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15814606997 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16436511995 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 621904998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15814606997 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16436511995 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.309507 # Cycle average of tags in use +system.iocache.tagsinuse 1.255779 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1711308479000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.309507 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.081844 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.081844 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +57,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11464497806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11464497806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11485170804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11485170804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11485170804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11485170804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +81,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275907.244080 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275907.244080 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275258.737064 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275258.737064 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199587000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24660 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8093.552311 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +107,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9303643992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9303643992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9315319992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9315319992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9315319992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9315319992 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +123,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223903.638621 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223903.638621 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +146,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9950205 # DTB read hits -system.cpu.dtb.read_misses 43861 # DTB read misses -system.cpu.dtb.read_acv 493 # DTB read access violations -system.cpu.dtb.read_accesses 957335 # DTB read accesses -system.cpu.dtb.write_hits 6626699 # DTB write hits -system.cpu.dtb.write_misses 9966 # DTB write misses -system.cpu.dtb.write_acv 395 # DTB write access violations -system.cpu.dtb.write_accesses 340478 # DTB write accesses -system.cpu.dtb.data_hits 16576904 # DTB hits -system.cpu.dtb.data_misses 53827 # DTB misses -system.cpu.dtb.data_acv 888 # DTB access violations -system.cpu.dtb.data_accesses 1297813 # DTB accesses -system.cpu.itb.fetch_hits 1339762 # ITB hits -system.cpu.itb.fetch_misses 37185 # ITB misses -system.cpu.itb.fetch_acv 1122 # ITB acv -system.cpu.itb.fetch_accesses 1376947 # ITB accesses +system.cpu.dtb.read_hits 9942716 # DTB read hits +system.cpu.dtb.read_misses 44791 # DTB read misses +system.cpu.dtb.read_acv 565 # DTB read access violations +system.cpu.dtb.read_accesses 947396 # DTB read accesses +system.cpu.dtb.write_hits 6623666 # DTB write hits +system.cpu.dtb.write_misses 10259 # DTB write misses +system.cpu.dtb.write_acv 393 # DTB write access violations +system.cpu.dtb.write_accesses 338396 # DTB write accesses +system.cpu.dtb.data_hits 16566382 # DTB hits +system.cpu.dtb.data_misses 55050 # DTB misses +system.cpu.dtb.data_acv 958 # DTB access violations +system.cpu.dtb.data_accesses 1285792 # DTB accesses +system.cpu.itb.fetch_hits 1328947 # ITB hits +system.cpu.itb.fetch_misses 38142 # ITB misses +system.cpu.itb.fetch_acv 1080 # ITB acv +system.cpu.itb.fetch_accesses 1367089 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,277 +174,277 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 124800831 # number of cpu cycles simulated +system.cpu.numCycles 112948398 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14048431 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11726244 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 450741 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10120037 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5916610 # Number of BTB hits +system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 938783 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45408 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31451408 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71430724 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14048431 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6855393 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13459712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2155244 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43163669 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 276321 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 306226 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8835796 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303984 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 90109445 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.792711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.123252 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76649733 85.06% 85.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 882120 0.98% 86.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1758761 1.95% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 855148 0.95% 88.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2774809 3.08% 92.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 597111 0.66% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671452 0.75% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1010353 1.12% 94.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4909958 5.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90109445 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.112567 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.572358 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32486072 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 42966960 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12232972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1046401 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1377039 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 612715 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43176 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70146735 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 131924 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1377039 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33631618 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17301504 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21458473 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11517889 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4822920 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66414787 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7289 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750703 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1791896 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44375645 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80516952 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80027527 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 489425 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38131021 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6244616 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1698641 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251106 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12735763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10548926 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961519 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1298320 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 905557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58829539 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2094293 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57137234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 128634 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7593303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3942261 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1428853 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 90109445 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.634087 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.284474 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64286768 71.34% 71.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11995743 13.31% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5355125 5.94% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3438365 3.82% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2611846 2.90% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1326020 1.47% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 685055 0.76% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 355852 0.39% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 54671 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 90109445 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 75508 9.96% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 363265 47.93% 57.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 319103 42.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38991069 68.24% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61859 0.11% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25608 0.04% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10392240 18.19% 86.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6705676 11.74% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949855 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57137234 # Type of FU issued -system.cpu.iq.rate 0.457827 # Inst issue rate -system.cpu.iq.fu_busy_cnt 757876 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013264 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 204573341 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68190814 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55847999 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 697081 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339930 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327759 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57523312 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 364507 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597966 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued +system.cpu.iq.rate 0.505315 # Inst issue rate +system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1464590 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2710 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13959 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 585881 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18028 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 111488 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1377039 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12355921 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 868580 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64490760 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 689025 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10548926 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961519 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1842879 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 620807 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12564 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13959 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 241262 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 422502 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 663764 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56606739 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10022317 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 530494 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3566928 # number of nop insts executed -system.cpu.iew.exec_refs 16674247 # number of memory reference insts executed -system.cpu.iew.exec_branches 8979744 # Number of branches executed -system.cpu.iew.exec_stores 6651930 # Number of stores executed -system.cpu.iew.exec_rate 0.453577 # Inst execution rate -system.cpu.iew.wb_sent 56287349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56175758 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27690548 # num instructions producing a value -system.cpu.iew.wb_consumers 37534692 # num instructions consuming a value +system.cpu.iew.exec_nop 3555305 # number of nop insts executed +system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed +system.cpu.iew.exec_branches 8969939 # Number of branches executed +system.cpu.iew.exec_stores 6649129 # Number of stores executed +system.cpu.iew.exec_rate 0.500679 # Inst execution rate +system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27804186 # num instructions producing a value +system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.450123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737732 # average fanout of values written-back +system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8267625 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 665440 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 619184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 88732406 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.632394 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.547937 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67542246 76.12% 76.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8923750 10.06% 86.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4811841 5.42% 91.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2594320 2.92% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1447946 1.63% 96.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 597901 0.67% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 519027 0.58% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 475014 0.54% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1820361 2.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 88732406 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56113829 # Number of instructions committed -system.cpu.commit.committedOps 56113829 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56188905 # Number of instructions committed +system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15459974 # Number of memory references committed -system.cpu.commit.loads 9084336 # Number of loads committed -system.cpu.commit.membars 226495 # Number of memory barriers committed -system.cpu.commit.branches 8440914 # Number of branches committed +system.cpu.commit.refs 15476867 # Number of memory references committed +system.cpu.commit.loads 9095415 # Number of loads committed +system.cpu.commit.membars 226300 # Number of memory barriers committed +system.cpu.commit.branches 8447820 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51962143 # Number of committed integer instructions. -system.cpu.commit.function_calls 739769 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1820361 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52034961 # Number of committed integer instructions. +system.cpu.commit.function_calls 740468 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 151043798 # The number of ROB reads -system.cpu.rob.rob_writes 130140767 # The number of ROB writes -system.cpu.timesIdled 1385278 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34691386 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3609940555 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52926469 # Number of Instructions Simulated -system.cpu.committedOps 52926469 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52926469 # Number of Instructions Simulated -system.cpu.cpi 2.358004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.358004 # CPI: Total CPI of All Threads -system.cpu.ipc 0.424087 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424087 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74197467 # number of integer regfile reads -system.cpu.int_regfile_writes 40518410 # number of integer regfile writes -system.cpu.fp_regfile_reads 166390 # number of floating regfile reads -system.cpu.fp_regfile_writes 166940 # number of floating regfile writes -system.cpu.misc_regfile_reads 1995246 # number of misc regfile reads -system.cpu.misc_regfile_writes 947641 # number of misc regfile writes +system.cpu.rob.rob_reads 141682968 # The number of ROB reads +system.cpu.rob.rob_writes 129465441 # The number of ROB writes +system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52998368 # Number of Instructions Simulated +system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated +system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads +system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74144483 # number of integer regfile reads +system.cpu.int_regfile_writes 40484328 # number of integer regfile writes +system.cpu.fp_regfile_reads 165992 # number of floating regfile reads +system.cpu.fp_regfile_writes 167427 # number of floating regfile writes +system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads +system.cpu.misc_regfile_writes 946826 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -668,245 +476,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1022327 # number of replacements -system.cpu.icache.tagsinuse 509.956829 # Cycle average of tags in use -system.cpu.icache.total_refs 7752117 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1022838 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.579027 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23896694000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.956829 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996009 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996009 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7752118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7752118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7752118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7752118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7752118 # number of overall hits -system.cpu.icache.overall_hits::total 7752118 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1083676 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1083676 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1083676 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1083676 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1083676 # number of overall misses -system.cpu.icache.overall_misses::total 1083676 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17473525489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17473525489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17473525489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17473525489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17473525489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17473525489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8835794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8835794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8835794 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8835794 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8835794 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8835794 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16124.307901 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16124.307901 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16124.307901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16124.307901 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1701496 # number of cycles access was blocked +system.cpu.icache.replacements 1020348 # number of replacements +system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use +system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits +system.cpu.icache.overall_hits::total 7661721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses +system.cpu.icache.overall_misses::total 1079749 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9098.909091 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60589 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60589 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60589 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60589 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60589 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60589 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1023087 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1023087 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1023087 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1023087 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1023087 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1023087 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13469506496 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13469506496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13469506496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13469506496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13469506496 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13469506496 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115789 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115789 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115789 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13165.553365 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13165.553365 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13165.553365 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13165.553365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13165.553365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13165.553365 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # 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Average occupied blocks per requestor +system.cpu.dcache.replacements 1402622 # number of replacements +system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use +system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7252868 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7252868 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4173229 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4173229 # 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number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits +system.cpu.dcache.overall_hits::total 11479559 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses +system.cpu.dcache.overall_misses::total 3739889 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # 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miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 110012 # 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number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks +system.cpu.l2cache.writebacks::total 76030 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6432 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211195 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74695 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 137 0.08% 41.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.04% 42.06% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105693 57.94% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182415 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73328 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 137 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73331 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148686 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1826702082500 97.82% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 72077500 0.00% 97.83% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 572984500 0.03% 97.86% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40025844000 2.14% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1867372988500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981699 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693811 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815097 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -972,32 +960,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.18% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175272 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6795 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5118 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192141 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 191902 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393483 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29935560000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2782423500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1834654997000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3cd1cf5f9..a59fc99d0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.537930 # Number of seconds simulated -sim_ticks 2537929870500 # Number of ticks simulated -final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534231 # Number of seconds simulated +sim_ticks 2534231333000 # Number of ticks simulated +final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52642 # Simulator instruction rate (inst/s) -host_op_rate 67714 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2204296601 # Simulator tick rate (ticks/s) -host_mem_usage 387316 # Number of bytes of host memory used -host_seconds 1151.36 # Real time elapsed on the host -sim_insts 60609996 # Number of instructions simulated -sim_ops 77962726 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory +host_inst_rate 44913 # Simulator instruction rate (inst/s) +host_op_rate 57771 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1878262368 # Simulator tick rate (ticks/s) +host_mem_usage 387000 # Number of bytes of host memory used +host_seconds 1349.24 # Real time elapsed on the host +sim_insts 60598653 # Number of instructions simulated +sim_ops 77947265 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,273 +61,6 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 64349 # number of replacements -system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -336,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052897 # DTB read hits -system.cpu.checker.dtb.read_misses 7321 # DTB read misses -system.cpu.checker.dtb.write_hits 11296410 # DTB write hits -system.cpu.checker.dtb.write_misses 2195 # DTB write misses +system.cpu.checker.dtb.read_hits 15049411 # DTB read hits +system.cpu.checker.dtb.read_misses 7302 # DTB read misses +system.cpu.checker.dtb.write_hits 11294478 # DTB write hits +system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15060218 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298605 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056713 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296667 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26349307 # DTB hits -system.cpu.checker.dtb.misses 9516 # DTB misses -system.cpu.checker.dtb.accesses 26358823 # DTB accesses -system.cpu.checker.itb.inst_hits 61788771 # ITB inst hits +system.cpu.checker.dtb.hits 26343889 # DTB hits +system.cpu.checker.dtb.misses 9491 # DTB misses +system.cpu.checker.dtb.accesses 26353380 # DTB accesses +system.cpu.checker.itb.inst_hits 61777417 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -372,36 +105,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61793242 # ITB inst accesses -system.cpu.checker.itb.hits 61788771 # DTB hits +system.cpu.checker.itb.inst_accesses 61781888 # ITB inst accesses +system.cpu.checker.itb.hits 61777417 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61793242 # DTB accesses -system.cpu.checker.numCycles 78253308 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61781888 # DTB accesses +system.cpu.checker.numCycles 78237836 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51757171 # DTB read hits -system.cpu.dtb.read_misses 78755 # DTB read misses -system.cpu.dtb.write_hits 11824944 # DTB write hits -system.cpu.dtb.write_misses 17612 # DTB write misses +system.cpu.dtb.read_hits 51729232 # DTB read hits +system.cpu.dtb.read_misses 76957 # DTB read misses +system.cpu.dtb.write_hits 11808980 # DTB write hits +system.cpu.dtb.write_misses 17307 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7813 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7736 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51835926 # DTB read accesses -system.cpu.dtb.write_accesses 11842556 # DTB write accesses +system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806189 # DTB read accesses +system.cpu.dtb.write_accesses 11826287 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63582115 # DTB hits -system.cpu.dtb.misses 96367 # DTB misses -system.cpu.dtb.accesses 63678482 # DTB accesses -system.cpu.itb.inst_hits 13115769 # ITB inst hits -system.cpu.itb.inst_misses 12252 # ITB inst misses +system.cpu.dtb.hits 63538212 # DTB hits +system.cpu.dtb.misses 94264 # DTB misses +system.cpu.dtb.accesses 63632476 # DTB accesses +system.cpu.itb.inst_hits 13079160 # ITB inst hits +system.cpu.itb.inst_misses 12175 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -410,538 +143,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5204 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13128021 # ITB inst accesses -system.cpu.itb.hits 13115769 # DTB hits -system.cpu.itb.misses 12252 # DTB misses -system.cpu.itb.accesses 13128021 # DTB accesses -system.cpu.numCycles 487049956 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13091335 # ITB inst accesses +system.cpu.itb.hits 13079160 # DTB hits +system.cpu.itb.misses 12175 # DTB misses +system.cpu.itb.accesses 13091335 # DTB accesses +system.cpu.numCycles 475963827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits +system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued -system.cpu.iq.rate 0.259310 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued +system.cpu.iq.rate 0.265193 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226495 # number of nop insts executed -system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed -system.cpu.iew.exec_branches 11753944 # Number of branches executed -system.cpu.iew.exec_stores 12337385 # Number of stores executed -system.cpu.iew.exec_rate 0.252721 # Inst execution rate -system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47490892 # num instructions producing a value -system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value +system.cpu.iew.exec_nop 225525 # number of nop insts executed +system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed +system.cpu.iew.exec_branches 11734992 # Number of branches executed +system.cpu.iew.exec_stores 12321310 # Number of stores executed +system.cpu.iew.exec_rate 0.258373 # Inst execution rate +system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712496 # num instructions producing a value +system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60760377 # Number of instructions committed -system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749034 # Number of instructions committed +system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27521116 # Number of memory references committed -system.cpu.commit.loads 15720306 # Number of loads committed -system.cpu.commit.membars 413361 # Number of memory barriers committed -system.cpu.commit.branches 10025135 # Number of branches committed +system.cpu.commit.refs 27515291 # Number of memory references committed +system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.membars 413125 # Number of memory barriers committed +system.cpu.commit.branches 10023270 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. -system.cpu.commit.function_calls 996276 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.function_calls 996018 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256258159 # The number of ROB reads -system.cpu.rob.rob_writes 209428063 # The number of ROB writes -system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60609996 # Number of Instructions Simulated -system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated -system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 557221655 # number of integer regfile reads -system.cpu.int_regfile_writes 90065137 # number of integer regfile writes -system.cpu.fp_regfile_reads 8220 # number of floating regfile reads -system.cpu.fp_regfile_writes 2852 # number of floating regfile writes -system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads -system.cpu.misc_regfile_writes 913466 # number of misc regfile writes -system.cpu.icache.replacements 990831 # number of replacements -system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use -system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits -system.cpu.icache.overall_hits::total 12036161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses -system.cpu.icache.overall_misses::total 1075440 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked +system.cpu.rob.rob_reads 249559242 # The number of ROB reads +system.cpu.rob.rob_writes 208759201 # The number of ROB writes +system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598653 # Number of Instructions Simulated +system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated +system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556742715 # number of integer regfile reads +system.cpu.int_regfile_writes 89972067 # number of integer regfile writes +system.cpu.fp_regfile_reads 8371 # number of floating regfile reads +system.cpu.fp_regfile_writes 2922 # number of floating regfile writes +system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads +system.cpu.misc_regfile_writes 912914 # number of misc regfile writes +system.cpu.icache.replacements 989669 # number of replacements +system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use +system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits +system.cpu.icache.overall_hits::total 12001618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses +system.cpu.icache.overall_misses::total 1073577 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2357994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285730 # 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number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks +system.cpu.dcache.writebacks::total 609206 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506735998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793829994 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6302908992 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730274500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735566500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -963,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ebf3a5c17..2d955a00e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.537930 # Number of seconds simulated -sim_ticks 2537929870500 # Number of ticks simulated -final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534231 # Number of seconds simulated +sim_ticks 2534231333000 # Number of ticks simulated +final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62423 # Simulator instruction rate (inst/s) -host_op_rate 80294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2613828720 # Simulator tick rate (ticks/s) -host_mem_usage 387060 # Number of bytes of host memory used -host_seconds 970.96 # Real time elapsed on the host -sim_insts 60609996 # Number of instructions simulated -sim_ops 77962726 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory +host_inst_rate 58448 # Simulator instruction rate (inst/s) +host_op_rate 75181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2444289303 # Simulator tick rate (ticks/s) +host_mem_usage 386996 # Number of bytes of host memory used +host_seconds 1036.80 # Real time elapsed on the host +sim_insts 60598653 # Number of instructions simulated +sim_ops 77947265 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,273 +61,6 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 64349 # number of replacements -system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 502174 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1576793 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 84751 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12176 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits -system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10706 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133143 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12366 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143849 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156282 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12366 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143849 # number of overall misses -system.cpu.l2cache.overall_misses::total 156282 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8295680990 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1733075 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1733075 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.090176 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.090176 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59057 # number of writebacks -system.cpu.l2cache.writebacks::total 59057 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156212 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -336,27 +69,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51757171 # DTB read hits -system.cpu.dtb.read_misses 78755 # DTB read misses -system.cpu.dtb.write_hits 11824944 # DTB write hits -system.cpu.dtb.write_misses 17612 # DTB write misses +system.cpu.dtb.read_hits 51729232 # DTB read hits +system.cpu.dtb.read_misses 76957 # DTB read misses +system.cpu.dtb.write_hits 11808980 # DTB write hits +system.cpu.dtb.write_misses 17307 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4306 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4248 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51835926 # DTB read accesses -system.cpu.dtb.write_accesses 11842556 # DTB write accesses +system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806189 # DTB read accesses +system.cpu.dtb.write_accesses 11826287 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63582115 # DTB hits -system.cpu.dtb.misses 96367 # DTB misses -system.cpu.dtb.accesses 63678482 # DTB accesses -system.cpu.itb.inst_hits 13115769 # ITB inst hits -system.cpu.itb.inst_misses 12252 # ITB inst misses +system.cpu.dtb.hits 63538212 # DTB hits +system.cpu.dtb.misses 94264 # DTB misses +system.cpu.dtb.accesses 63632476 # DTB accesses +system.cpu.itb.inst_hits 13079160 # ITB inst hits +system.cpu.itb.inst_misses 12175 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -365,538 +98,538 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2604 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13128021 # ITB inst accesses -system.cpu.itb.hits 13115769 # DTB hits -system.cpu.itb.misses 12252 # DTB misses -system.cpu.itb.accesses 13128021 # DTB accesses -system.cpu.numCycles 487049956 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13091335 # ITB inst accesses +system.cpu.itb.hits 13079160 # DTB hits +system.cpu.itb.misses 12175 # DTB misses +system.cpu.itb.accesses 13091335 # DTB accesses +system.cpu.numCycles 475963827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits +system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued -system.cpu.iq.rate 0.259310 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued +system.cpu.iq.rate 0.265193 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226495 # number of nop insts executed -system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed -system.cpu.iew.exec_branches 11753944 # Number of branches executed -system.cpu.iew.exec_stores 12337385 # Number of stores executed -system.cpu.iew.exec_rate 0.252721 # Inst execution rate -system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47490892 # num instructions producing a value -system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value +system.cpu.iew.exec_nop 225525 # number of nop insts executed +system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed +system.cpu.iew.exec_branches 11734992 # Number of branches executed +system.cpu.iew.exec_stores 12321310 # Number of stores executed +system.cpu.iew.exec_rate 0.258373 # Inst execution rate +system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712496 # num instructions producing a value +system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60760377 # Number of instructions committed -system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749034 # Number of instructions committed +system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27521116 # Number of memory references committed -system.cpu.commit.loads 15720306 # Number of loads committed -system.cpu.commit.membars 413361 # Number of memory barriers committed -system.cpu.commit.branches 10025135 # Number of branches committed +system.cpu.commit.refs 27515291 # Number of memory references committed +system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.membars 413125 # Number of memory barriers committed +system.cpu.commit.branches 10023270 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. -system.cpu.commit.function_calls 996276 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.function_calls 996018 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256258159 # The number of ROB reads -system.cpu.rob.rob_writes 209428063 # The number of ROB writes -system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60609996 # Number of Instructions Simulated -system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated -system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 557221649 # number of integer regfile reads -system.cpu.int_regfile_writes 90065135 # number of integer regfile writes -system.cpu.fp_regfile_reads 8220 # number of floating regfile reads -system.cpu.fp_regfile_writes 2852 # number of floating regfile writes -system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads -system.cpu.misc_regfile_writes 913466 # number of misc regfile writes -system.cpu.icache.replacements 990831 # number of replacements -system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use -system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits -system.cpu.icache.overall_hits::total 12036161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses -system.cpu.icache.overall_misses::total 1075440 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked +system.cpu.rob.rob_reads 249559242 # The number of ROB reads +system.cpu.rob.rob_writes 208759201 # The number of ROB writes +system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598653 # Number of Instructions Simulated +system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated +system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556742712 # number of integer regfile reads +system.cpu.int_regfile_writes 89972066 # number of integer regfile writes +system.cpu.fp_regfile_reads 8371 # number of floating regfile reads +system.cpu.fp_regfile_writes 2922 # number of floating regfile writes +system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads +system.cpu.misc_regfile_writes 912914 # number of misc regfile writes +system.cpu.icache.replacements 989669 # number of replacements +system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use +system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits +system.cpu.icache.overall_hits::total 12001618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses +system.cpu.icache.overall_misses::total 1073577 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2357994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # 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Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21154214 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # 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number of replacements +system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use +system.cpu.dcache.total_refs 21796404 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645677 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.757442 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285730 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21223191 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21223191 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21223191 # number of overall hits +system.cpu.dcache.overall_hits::total 21223191 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 726725 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 726725 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962478 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962478 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13561 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3689203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3689203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3689203 # number of overall misses +system.cpu.dcache.overall_misses::total 3689203 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9436874000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9436874000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104178007737 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104178007737 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180640000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180640000 # 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miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12985.481441 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12985.481441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35165.833379 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35165.833379 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13320.551582 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13320.551582 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30796.592580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30796.592580 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12775922 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7850000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2526 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5057.768013 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27738.515901 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks -system.cpu.dcache.writebacks::total 609524 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks +system.cpu.dcache.writebacks::total 609206 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713436 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1355 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1355 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3052761 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3052761 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3052761 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3052761 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387400 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387400 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249042 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249042 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12206 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12206 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636442 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636442 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636442 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636442 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4757620458 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4757620458 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8541364957 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8541364957 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141415500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141415500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 332500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 332500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13298985415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13298985415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13298985415 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13298985415 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407548000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407548000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41944273253 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41944273253 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224351821253 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224351821253 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026423 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026423 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024295 # 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average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12280.899479 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.885493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34296.885493 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11585.736523 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11585.736523 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -904,6 +637,269 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 64397 # number of replacements +system.cpu.l2cache.tagsinuse 51351.941492 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1929097 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129792 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.862988 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2499029961500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36885.832563 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 46.221263 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8173.888273 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6245.999155 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.562833 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -918,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f421b5375..978d3ed52 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,327 +1,84 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.163939 # Number of seconds simulated -sim_ticks 5163939423500 # Number of ticks simulated -final_tick 5163939423500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125295 # Number of seconds simulated +sim_ticks 5125295451000 # Number of ticks simulated +final_tick 5125295451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202828 # Simulator instruction rate (inst/s) -host_op_rate 400952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2568035232 # Simulator tick rate (ticks/s) -host_mem_usage 368532 # Number of bytes of host memory used -host_seconds 2010.85 # Real time elapsed on the host -sim_insts 407858031 # Number of instructions simulated -sim_ops 806254969 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2460224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1069888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10576384 # Number of bytes read from this memory -system.physmem.bytes_read::total 14109824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1069888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1069888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9320448 # Number of bytes written to this memory -system.physmem.bytes_written::total 9320448 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38441 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165256 # Number of read requests responded to by this memory -system.physmem.num_reads::total 220466 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145632 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145632 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 207184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2048123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2732376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1804910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1804910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1804910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 109190 # number of replacements -system.cpu.l2cache.tagsinuse 64839.015299 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3984882 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.977685 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989365 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2515284 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1610495 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1610495 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 337 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 158131 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1505908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2673415 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 103321 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8437 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1055749 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1505908 # number of overall hits -system.cpu.l2cache.overall_hits::total 2673415 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35983 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3384 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3384 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130218 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130218 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16718 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166201 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 182971 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16718 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166201 # number of overall misses -system.cpu.l2cache.overall_misses::total 182971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2414500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 887508500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1921141998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2811377498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 38315000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 38315000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6787419499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6787419499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2414500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 887508500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8708561497 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9598796997 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2414500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 887508500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8708561497 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9598796997 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103367 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8443 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1072467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1383760 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2568037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1610495 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1610495 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3721 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3721 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103367 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8443 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1072467 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1672109 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2856386 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103367 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8443 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1072467 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1672109 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2856386 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000711 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015588 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026004 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.020542 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.909433 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.909433 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.451599 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.451599 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000711 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015588 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.099396 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.064057 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000711 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015588 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.099396 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.064057 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.130435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52083.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53087.002034 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53390.267571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53293.224992 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11322.399527 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11322.399527 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52123.512103 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52123.512103 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52460.756060 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52460.756060 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98965 # number of writebacks -system.cpu.l2cache.writebacks::total 98965 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1856000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683651500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1481312999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2167060499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 135806000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 135806000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5218894001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5218894001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1856000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683651500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6700207000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7385954500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1856000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683651500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6700207000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7385954500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47573 # number of replacements -system.iocache.tagsinuse 0.184801 # Cycle average of tags in use +host_inst_rate 133696 # Simulator instruction rate (inst/s) +host_op_rate 264282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1679641336 # Simulator tick rate (ticks/s) +host_mem_usage 368820 # Number of bytes of host memory used +host_seconds 3051.42 # Real time elapsed on the host +sim_insts 407963822 # Number of instructions simulated +sim_ops 806434654 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2463488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1076608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10836416 # Number of bytes read from this memory +system.physmem.bytes_read::total 14379776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1076608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1076608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9553280 # Number of bytes written to this memory +system.physmem.bytes_written::total 9553280 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169319 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224684 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149270 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2114301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2805648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1863947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1863947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1863947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 210058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2114301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4669595 # Total bandwidth to/from this memory (bytes/s) +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.091712 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996693675000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.184801 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.011550 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.011550 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.091712 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.005732 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.005732 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses -system.iocache.demand_misses::total 47628 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses -system.iocache.overall_misses::total 47628 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137681932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 137681932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9939428160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9939428160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10077110092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10077110092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10077110092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10077110092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138301932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 138301932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9924152160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9924152160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10062454092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10062454092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10062454092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10062454092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +87,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151632.083700 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 151632.083700 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212744.609589 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212744.609589 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211579.534979 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211579.534979 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72537008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151646.855263 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151646.855263 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212417.640411 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212417.640411 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211254.074824 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211254.074824 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 71289012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8981 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8825 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8076.718406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8078.075014 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 908 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47628 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47628 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47628 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47628 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90434000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90434000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7509668946 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7509668946 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7600102946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7600102946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90847000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90847000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7494384978 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7494384978 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7585231978 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7585231978 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,18 +129,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99596.916300 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 99596.916300 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160737.777098 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160737.777098 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99612.938596 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99612.938596 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160410.637372 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160410.637372 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -393,141 +150,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 465816448 # number of cpu cycles simulated +system.cpu.numCycles 448616710 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86514848 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86514848 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1196192 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82053392 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79452542 # Number of BTB hits +system.cpu.BPredUnit.lookups 86513922 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86513922 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1185612 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81821696 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79447101 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31181464 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427226624 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86514848 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79452542 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164016210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5124580 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 155814 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 72471814 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36433 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 65503 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9296745 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 539923 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4055 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 271815204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.102878 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406830 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27982708 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427301680 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86513922 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79447101 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164025545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5056665 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 120243 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63002299 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 57009 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9269960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 518545 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3708 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 259058563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.256074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417846 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108229721 39.82% 39.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1589699 0.58% 40.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71960202 26.47% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971866 0.36% 67.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1623537 0.60% 67.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2454126 0.90% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122252 0.41% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1424890 0.52% 69.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82438911 30.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95463641 36.85% 36.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1593246 0.62% 37.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71955070 27.78% 65.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 970468 0.37% 65.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1621274 0.63% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2451045 0.95% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1124441 0.43% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1422902 0.55% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82456476 31.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271815204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185727 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.917157 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34976255 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69906357 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159691682 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3353316 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3887594 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840157503 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1253 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3887594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37933620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43316590 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11886084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159761513 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15029803 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836332638 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33622 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7171271 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5982447 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16586 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998051723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816227596 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816227024 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 572 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964187470 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33864246 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 467105 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 474137 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 32047540 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336278 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10273791 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1251259 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 987046 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829985579 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1254715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824362930 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185325 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23972130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36446956 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 204607 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271815204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.032807 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.413784 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 259058563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192846 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952487 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31703593 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60473195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159750936 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3297057 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3833782 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840221922 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1208 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3833782 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34472569 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37379630 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10860587 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159949927 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12562068 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836350803 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21427 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5922094 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4820401 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7659 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998159477 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816297556 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816296596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 960 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964421570 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33737900 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28941579 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17313500 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10257423 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1154419 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 952791 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829902104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256068 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824407567 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167070 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23703242 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36101298 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203347 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 259058563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.182321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385461 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82518813 30.36% 30.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18405041 6.77% 37.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10590940 3.90% 41.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7611334 2.80% 43.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75787785 27.88% 71.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3621369 1.33% 73.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72414876 26.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 725602 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 139444 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72075437 27.82% 27.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15729256 6.07% 33.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10360511 4.00% 37.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7565386 2.92% 40.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75947592 29.32% 70.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3904357 1.51% 71.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72537575 28.00% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 784064 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 154385 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271815204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 259058563 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 330736 32.15% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548005 53.27% 85.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150045 14.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 356821 33.57% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553408 52.07% 85.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152587 14.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308450 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796558014 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 305253 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796599749 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -556,246 +313,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18020026 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9476440 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18032887 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9469678 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824362930 # Type of FU issued -system.cpu.iq.rate 1.769716 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1028786 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1921889039 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855222885 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819729616 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825083173 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1659720 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824407567 # Type of FU issued +system.cpu.iq.rate 1.837666 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1062816 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001289 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1909237330 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854871180 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819733271 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 242 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 64 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825165021 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3372872 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11865 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1866399 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3332196 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26785 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11385 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1841480 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917615 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932351 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11661 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3887594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28830241 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2469402 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831240294 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338803 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336278 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10273791 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725681 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1777576 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17730 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11865 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 713088 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 629130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1342218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822392031 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17604275 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1970898 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3833782 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26055488 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116129 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831158172 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342184 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17313500 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10257423 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725671 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616608 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15691 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11385 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 710592 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 622404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1332996 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822394271 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17607905 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2013295 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26833761 # number of memory reference insts executed -system.cpu.iew.exec_branches 83292230 # Number of branches executed -system.cpu.iew.exec_stores 9229486 # Number of stores executed -system.cpu.iew.exec_rate 1.765485 # Inst execution rate -system.cpu.iew.wb_sent 821862423 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819729668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639700217 # num instructions producing a value -system.cpu.iew.wb_consumers 1045258728 # num instructions consuming a value +system.cpu.iew.exec_refs 26830923 # number of memory reference insts executed +system.cpu.iew.exec_branches 83287562 # Number of branches executed +system.cpu.iew.exec_stores 9223018 # Number of stores executed +system.cpu.iew.exec_rate 1.833178 # Inst execution rate +system.cpu.iew.wb_sent 821886032 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819733335 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640537929 # num instructions producing a value +system.cpu.iew.wb_consumers 1046481965 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.759770 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612002 # average fanout of values written-back +system.cpu.iew.wb_rate 1.827247 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612087 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24883748 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050106 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1201289 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267943051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.009053 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862554 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24617298 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052719 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1189640 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255240182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.159513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.852385 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95668224 35.70% 35.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12347484 4.61% 40.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3939395 1.47% 41.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74898098 27.95% 69.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2419496 0.90% 70.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1554494 0.58% 71.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1057385 0.39% 71.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70928163 26.47% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5130312 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83212701 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11927297 4.67% 37.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4018442 1.57% 38.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74971615 29.37% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2476707 0.97% 69.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1494205 0.59% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000959 0.39% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70934027 27.79% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5204229 2.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267943051 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407858031 # Number of instructions committed -system.cpu.commit.committedOps 806254969 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255240182 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407963822 # Number of instructions committed +system.cpu.commit.committedOps 806434654 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22370795 # Number of memory references committed -system.cpu.commit.loads 13963403 # Number of loads committed -system.cpu.commit.membars 471705 # Number of memory barriers committed -system.cpu.commit.branches 82181312 # Number of branches committed +system.cpu.commit.refs 22397244 # Number of memory references committed +system.cpu.commit.loads 13981301 # Number of loads committed +system.cpu.commit.membars 473469 # Number of memory barriers committed +system.cpu.commit.branches 82197284 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735195017 # Number of committed integer instructions. +system.cpu.commit.int_insts 735369790 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5130312 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5204229 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1093872885 # The number of ROB reads -system.cpu.rob.rob_writes 1666184214 # The number of ROB writes -system.cpu.timesIdled 1421273 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194001244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9862059849 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407858031 # Number of Instructions Simulated -system.cpu.committedOps 806254969 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407858031 # Number of Instructions Simulated -system.cpu.cpi 1.142104 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.142104 # CPI: Total CPI of All Threads -system.cpu.ipc 0.875577 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.875577 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508209791 # number of integer regfile reads -system.cpu.int_regfile_writes 977816443 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 265196274 # number of misc regfile reads -system.cpu.misc_regfile_writes 402502 # number of misc regfile writes -system.cpu.icache.replacements 1071989 # number of replacements -system.cpu.icache.tagsinuse 510.817098 # Cycle average of tags in use -system.cpu.icache.total_refs 8149627 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072501 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.598713 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.817098 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997690 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997690 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8149627 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8149627 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8149627 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8149627 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8149627 # number of overall hits -system.cpu.icache.overall_hits::total 8149627 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1147113 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1147113 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1147113 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1147113 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1147113 # number of overall misses -system.cpu.icache.overall_misses::total 1147113 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18981109491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18981109491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18981109491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18981109491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18981109491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18981109491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9296740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9296740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9296740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9296740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9296740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9296740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123389 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123389 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123389 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123389 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123389 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123389 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16546.852395 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16546.852395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16546.852395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16546.852395 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3167993 # number of cycles access was blocked +system.cpu.rob.rob_reads 1081009655 # The number of ROB reads +system.cpu.rob.rob_writes 1665958243 # The number of ROB writes +system.cpu.timesIdled 1218536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189558147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9801971615 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407963822 # Number of Instructions Simulated +system.cpu.committedOps 806434654 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407963822 # Number of Instructions Simulated +system.cpu.cpi 1.099648 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.099648 # CPI: Total CPI of All Threads +system.cpu.ipc 0.909382 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.909382 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508373932 # number of integer regfile reads +system.cpu.int_regfile_writes 977906784 # number of integer regfile writes +system.cpu.fp_regfile_reads 64 # number of floating regfile reads +system.cpu.misc_regfile_reads 265175533 # number of misc regfile reads +system.cpu.misc_regfile_writes 402332 # number of misc regfile writes +system.cpu.icache.replacements 1068558 # number of replacements +system.cpu.icache.tagsinuse 510.894483 # Cycle average of tags in use +system.cpu.icache.total_refs 8130546 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1069070 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.605251 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.894483 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997841 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997841 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8130546 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8130546 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8130546 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8130546 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8130546 # number of overall hits +system.cpu.icache.overall_hits::total 8130546 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139410 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139410 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139410 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139410 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139410 # number of overall misses +system.cpu.icache.overall_misses::total 1139410 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15243937992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15243937992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15243937992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15243937992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15243937992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15243937992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9269956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9269956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9269956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9269956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9269956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9269956 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13378.799547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13378.799547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13378.799547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13378.799547 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2477494 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 401 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7900.231920 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9753.913386 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72595 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72595 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 72595 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 72595 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 72595 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 72595 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1074518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1074518 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1074518 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1074518 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1074518 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14814669993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14814669993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14814669993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14814669993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14814669993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14814669993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13787.270193 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13787.270193 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68152 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68152 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071258 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071258 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071258 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071258 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071258 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071258 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12539776496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12539776496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12539776496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12539776496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12539776496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12539776496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115562 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115562 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115562 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11705.654937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11705.654937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9931 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.048032 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 33329 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9947 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.350658 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5125253660500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.048032 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.378002 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.378002 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 33326 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 33326 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9803 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.028064 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28000 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9816 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.852486 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5098956249000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028064 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376754 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376754 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28010 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28010 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 33329 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 33329 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 33329 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 33329 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10825 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10825 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10825 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10825 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10825 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10825 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 178140000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 178140000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 178140000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 178140000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 178140000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 178140000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 44151 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 44151 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28013 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28013 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28013 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28013 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10692 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10692 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10692 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10692 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10692 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10692 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117857500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117857500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117857500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 117857500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117857500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 117857500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38702 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38702 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 44154 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 44154 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 44154 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 44154 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245181 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245181 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245165 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.245165 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245165 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.245165 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16456.351039 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16456.351039 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16456.351039 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38705 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38705 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38705 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38705 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.276265 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.276265 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.276243 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.276243 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.276243 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.276243 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11022.961092 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11022.961092 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11022.961092 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,78 +561,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10825 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10825 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10825 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10825 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10825 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10825 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 145034027 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 145034027 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 145034027 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 145034027 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 145034027 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 145034027 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245181 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245181 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245165 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245165 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13398.062540 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10692 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10692 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10692 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10692 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10692 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10692 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96471005 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96471005 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96471005 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96471005 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96471005 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96471005 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.276265 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.276265 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.276243 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.276243 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9022.727740 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109056 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.865602 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139886 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109072 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.282511 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108962066000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.865602 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866600 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.866600 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139886 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139886 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139886 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139886 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110096 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110096 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110096 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110096 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110096 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110096 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2001823500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2001823500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2001823500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2001823500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2001823500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2001823500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249982 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 249982 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249982 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 249982 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249982 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 249982 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.440416 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.440416 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.440416 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.440416 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.440416 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.440416 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18182.527067 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18182.527067 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109091 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 11.986906 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 138731 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109107 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.271513 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.986906 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749182 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.749182 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138731 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 138731 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138731 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 138731 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138731 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 138731 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110113 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110113 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110113 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110113 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110113 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110113 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1378090500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1378090500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1378090500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1378090500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1378090500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1378090500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248844 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 248844 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248844 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 248844 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248844 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 248844 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442498 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442498 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442498 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442498 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442498 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442498 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12515.238891 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12515.238891 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12515.238891 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -884,146 +641,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35215 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35215 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110096 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110096 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110096 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110096 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110096 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110096 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1668892003 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1668892003 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1668892003 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.440416 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.440416 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.440416 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15158.516231 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 32856 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 32856 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110113 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110113 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110113 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110113 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110113 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110113 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1157860508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1157860508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1157860508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442498 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442498 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442498 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.202637 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1672208 # number of replacements -system.cpu.dcache.tagsinuse 511.998155 # Cycle average of tags in use -system.cpu.dcache.total_refs 19212274 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1672720 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.485649 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998155 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11127928 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11127928 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8079547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8079547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19207475 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19207475 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19207475 # number of overall hits -system.cpu.dcache.overall_hits::total 19207475 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2271021 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2271021 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688158999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6872613000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7562833999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1782000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688158999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6872613000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7562833999 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185334000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185334000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304322500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304322500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489656500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489656500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915453 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915453 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.065591 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000429 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.065591 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40908.274819 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41477.165630 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41298.990909 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40126.674107 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40126.674107 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40055.554304 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40055.554304 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 56312634f..011acdd4e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274137 # Number of seconds simulated -sim_ticks 274137453500 # Number of ticks simulated -final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.271545 # Number of seconds simulated +sim_ticks 271544682500 # Number of ticks simulated +final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134061 # Simulator instruction rate (inst/s) -host_op_rate 134061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61063086 # Simulator tick rate (ticks/s) -host_mem_usage 219148 # Number of bytes of host memory used -host_seconds 4489.41 # Real time elapsed on the host +host_inst_rate 105483 # Simulator instruction rate (inst/s) +host_op_rate 105483 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47591638 # Simulator tick rate (ticks/s) +host_mem_usage 219440 # Number of bytes of host memory used +host_seconds 5705.72 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data 25316 # Nu system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114518787 # DTB read hits +system.cpu.dtb.read_hits 114517787 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114521418 # DTB read accesses -system.cpu.dtb.write_hits 39662426 # DTB write hits +system.cpu.dtb.read_accesses 114520418 # DTB read accesses +system.cpu.dtb.write_hits 39661840 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664728 # DTB write accesses -system.cpu.dtb.data_hits 154181213 # DTB hits +system.cpu.dtb.write_accesses 39664142 # DTB write accesses +system.cpu.dtb.data_hits 154179627 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154186146 # DTB accesses -system.cpu.itb.fetch_hits 25086764 # ITB hits +system.cpu.dtb.data_accesses 154184560 # DTB accesses +system.cpu.itb.fetch_hits 25070818 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25086786 # ITB accesses +system.cpu.itb.fetch_accesses 25070840 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548274908 # number of cpu cycles simulated +system.cpu.numCycles 543089366 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits +system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36895090 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49414915 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541552617 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005407463 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155050348 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255071199 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155051796 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2591546 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36349330 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538349706 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed. -system.cpu.activity 89.213788 # Percentage of cycles cpu is active +system.cpu.timesIdled 387700 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53984537 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489104829 # Number of cycles cpu stages are processed. +system.cpu.activity 90.059732 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.902356 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.902356 # CPI: Total CPI of All Threads +system.cpu.ipc 1.108210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.108210 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 204234221 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338855145 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.393994 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 232262845 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310826521 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.233034 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 201309957 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341779409 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.932444 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 431519146 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111570220 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.543621 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 196111910 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346977456 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.889569 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use -system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.073717 # Cycle average of tags in use +system.cpu.icache.total_refs 25069794 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29321.396491 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits -system.cpu.icache.overall_hits::total 25085741 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.073717 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355993 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355993 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25069794 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25069794 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25069794 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25069794 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25069794 # number of overall hits +system.cpu.icache.overall_hits::total 25069794 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses +system.cpu.icache.overall_misses::total 1022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56347500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56347500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56347500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56347500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56347500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56347500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25070816 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25070816 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25070816 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25070816 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25070816 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25070816 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55134.540117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55134.540117 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55134.540117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46510500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46510500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46510500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54398.245614 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54398.245614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.014631 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406162 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits -system.cpu.dcache.overall_hits::total 152406041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses -system.cpu.dcache.overall_misses::total 1559322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.668062 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 268976000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.014631 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999515 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999515 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285655 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285655 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406162 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406162 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406162 # number of overall hits +system.cpu.dcache.overall_hits::total 152406162 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165666 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559201 # number of overall misses +system.cpu.dcache.overall_misses::total 1559201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5490501500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5490501500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16777875500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16777875500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22268377000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22268377000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22268377000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22268377000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13951.748891 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13951.748891 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14393.381552 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14393.381552 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911503 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911503 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103806 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103806 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395605000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395605000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3804662000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3804662000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6200267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6200267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6200267000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6200267000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11904.692097 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11904.692097 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14969.377919 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14969.377919 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22852.343306 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21651.877416 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.990292 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 480.475597 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660763 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021972 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014663 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697398 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits @@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total 26157 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 215882000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 261384000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220308500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1220308500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45502000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1436190500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1481692500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45502000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1436190500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1481692500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083387 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54104.637337 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52398.543689 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52687.764564 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57572.584450 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57572.584450 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total 26157 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35251500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165390500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200642000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 961154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 961154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1126544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1161796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1126544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1161796000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41916.171225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.325243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40443.862125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index f78f2bef4..73ec0cee6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135471 # Number of seconds simulated -sim_ticks 135471331500 # Number of ticks simulated -final_tick 135471331500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133202 # Number of seconds simulated +sim_ticks 133202081500 # Number of ticks simulated +final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 255662 # Simulator instruction rate (inst/s) -host_op_rate 255662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61240707 # Simulator tick rate (ticks/s) -host_mem_usage 220172 # Number of bytes of host memory used -host_seconds 2212.11 # Real time elapsed on the host +host_inst_rate 189557 # Simulator instruction rate (inst/s) +host_op_rate 189557 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44645563 # Simulator tick rate (ticks/s) +host_mem_usage 220464 # Number of bytes of host memory used +host_seconds 2983.55 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory -system.physmem.bytes_read::total 1689280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58944 # Number of bytes written to this memory -system.physmem.bytes_written::total 58944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26395 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 921 # Number of write requests responded to by this memory -system.physmem.num_writes::total 921 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 456835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12012815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12469649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 456835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 456835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 435103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 435103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 435103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 456835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12012815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12904752 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627520 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58752 # Number of bytes written to this memory +system.physmem.bytes_written::total 58752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25430 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 918 # Number of write requests responded to by this memory +system.physmem.num_writes::total 918 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 460293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12218428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12678721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 460293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 460293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 441074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 441074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 441074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 460293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12218428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13119795 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123970603 # DTB read hits -system.cpu.dtb.read_misses 28720 # DTB read misses +system.cpu.dtb.read_hits 123824653 # DTB read hits +system.cpu.dtb.read_misses 18111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123999323 # DTB read accesses -system.cpu.dtb.write_hits 40821734 # DTB write hits -system.cpu.dtb.write_misses 42993 # DTB write misses +system.cpu.dtb.read_accesses 123842764 # DTB read accesses +system.cpu.dtb.write_hits 40832181 # DTB write hits +system.cpu.dtb.write_misses 27219 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40864727 # DTB write accesses -system.cpu.dtb.data_hits 164792337 # DTB hits -system.cpu.dtb.data_misses 71713 # DTB misses +system.cpu.dtb.write_accesses 40859400 # DTB write accesses +system.cpu.dtb.data_hits 164656834 # DTB hits +system.cpu.dtb.data_misses 45330 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164864050 # DTB accesses -system.cpu.itb.fetch_hits 66629589 # ITB hits +system.cpu.dtb.data_accesses 164702164 # DTB accesses +system.cpu.itb.fetch_hits 66456282 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66629628 # ITB accesses +system.cpu.itb.fetch_accesses 66456321 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 270942664 # number of cpu cycles simulated +system.cpu.numCycles 266404164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78540801 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72908130 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3045250 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42784442 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41679238 # Number of BTB hits +system.cpu.BPredUnit.lookups 78470433 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72835844 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3045377 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42694984 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41620121 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1625962 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68608304 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 712216936 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78540801 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43305200 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119376688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13084394 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72934666 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1626012 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68396808 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710651464 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78470433 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43246133 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119157795 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12900055 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 68967877 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66629589 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 948387 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 270906593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.629013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.455853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1025 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66456282 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 943162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 266369518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.667916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.466169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151529905 55.93% 55.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10364245 3.83% 59.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11839822 4.37% 64.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10610225 3.92% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6991463 2.58% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2667986 0.98% 71.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3540757 1.31% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3105472 1.15% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70256718 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 147211723 55.27% 55.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10361930 3.89% 59.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11839981 4.44% 63.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10604273 3.98% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6985851 2.62% 70.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2662888 1.00% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3489906 1.31% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3104255 1.17% 73.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70108711 26.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270906593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289880 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.628663 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86218522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56873885 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104030125 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13799230 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9984831 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3903379 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1089 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703205131 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9984831 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94485896 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12289062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104300720 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49844418 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 691143238 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5409 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37459217 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6250189 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527606706 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907468723 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907465803 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2920 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 266369518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.294554 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.667569 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85436450 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 53444664 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104479529 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13163939 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9844936 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3905187 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1152 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 701891597 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4998 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9844936 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93666462 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10915780 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 985 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104171147 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47770208 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690014062 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37142293 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4412591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527194579 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906673497 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906670681 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2816 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63751817 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 110700400 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129196942 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42484118 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14760258 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9703253 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626892028 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 99 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608695355 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 350153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60644934 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33797171 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270906593 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.246883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.833563 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63339690 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 89 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 106261883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128976533 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42417035 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14777590 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9627827 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626339991 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608311695 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 332491 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60098493 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33347060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 266369518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.283714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.821089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55377469 20.44% 20.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55325876 20.42% 40.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 54071762 19.96% 60.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36846414 13.60% 74.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30891550 11.40% 85.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23842623 8.80% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10560250 3.90% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3379294 1.25% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 611355 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 51762898 19.43% 19.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 53589578 20.12% 39.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53994858 20.27% 59.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 37661936 14.14% 73.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31638901 11.88% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23703533 8.90% 94.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10074612 3.78% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3319964 1.25% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 623238 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270906593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 266369518 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2755770 75.48% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 573872 15.72% 91.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 321392 8.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2702741 76.36% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 515259 14.56% 90.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 321532 9.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441149057 72.47% 72.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7297 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126283457 20.75% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41255500 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 440952184 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7450 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126098325 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41253693 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608695355 # Type of FU issued -system.cpu.iq.rate 2.246584 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3651064 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005998 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492294648 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687539732 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598944947 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3872 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2425 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1713 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612344476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1943 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12180058 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608311695 # Type of FU issued +system.cpu.iq.rate 2.283417 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3539537 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005819 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1486861080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686441117 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598748300 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3856 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2343 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 611849296 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1936 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12174453 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14682900 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33847 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5158 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3032797 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14462491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33569 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4944 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2965714 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6745 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162513 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6773 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 155 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9984831 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 591994 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80208 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 671175480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1733020 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129196942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42484118 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 99 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8476 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5158 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342632 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2208039 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3550671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602850413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123999444 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5844942 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9844936 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 227072 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16439 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670244681 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1692417 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128976533 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42417035 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6445 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4188 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4944 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342659 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2208068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3550727 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602499469 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123842867 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5812226 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44283353 # number of nop insts executed -system.cpu.iew.exec_refs 164880697 # number of memory reference insts executed -system.cpu.iew.exec_branches 67045865 # Number of branches executed -system.cpu.iew.exec_stores 40881253 # Number of stores executed -system.cpu.iew.exec_rate 2.225011 # Inst execution rate -system.cpu.iew.wb_sent 600209978 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598946660 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417271834 # num instructions producing a value -system.cpu.iew.wb_consumers 532298467 # num instructions consuming a value +system.cpu.iew.exec_nop 43904609 # number of nop insts executed +system.cpu.iew.exec_refs 164718956 # number of memory reference insts executed +system.cpu.iew.exec_branches 66994757 # Number of branches executed +system.cpu.iew.exec_stores 40876089 # Number of stores executed +system.cpu.iew.exec_rate 2.261599 # Inst execution rate +system.cpu.iew.wb_sent 599990050 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598749999 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417673921 # num instructions producing a value +system.cpu.iew.wb_consumers 531386701 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.210603 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783906 # average fanout of values written-back +system.cpu.iew.wb_rate 2.247525 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786007 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69202424 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68221188 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3044252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 260921762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.306657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.693748 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3044329 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 256524582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.346196 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.706570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 81870366 31.38% 31.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72918515 27.95% 59.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26232772 10.05% 69.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8204750 3.14% 72.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10788682 4.13% 76.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20849092 7.99% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6203888 2.38% 87.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3594438 1.38% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30259259 11.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77999684 30.41% 30.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72616675 28.31% 58.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26248532 10.23% 68.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7743107 3.02% 71.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10914414 4.25% 76.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20847110 8.13% 84.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6257952 2.44% 86.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3103879 1.21% 88.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30793229 12.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 260921762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 256524582 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30259259 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30793229 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 901657501 # The number of ROB reads -system.cpu.rob.rob_writes 1352126118 # The number of ROB writes -system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36071 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 895745115 # The number of ROB reads +system.cpu.rob.rob_writes 1350023504 # The number of ROB writes +system.cpu.timesIdled 796 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34646 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.479076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.479076 # CPI: Total CPI of All Threads -system.cpu.ipc 2.087351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.087351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848921354 # number of integer regfile reads -system.cpu.int_regfile_writes 492788777 # number of integer regfile writes -system.cpu.fp_regfile_reads 376 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cpi 0.471051 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.471051 # CPI: Total CPI of All Threads +system.cpu.ipc 2.122911 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.122911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848545483 # number of integer regfile reads +system.cpu.int_regfile_writes 492673182 # number of integer regfile writes +system.cpu.fp_regfile_reads 367 # number of floating regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 46 # number of replacements -system.cpu.icache.tagsinuse 834.348638 # Cycle average of tags in use -system.cpu.icache.total_refs 66628172 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67301.183838 # Average number of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.tagsinuse 827.655289 # Cycle average of tags in use +system.cpu.icache.total_refs 66454892 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67880.379980 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 834.348638 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.407397 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.407397 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66628172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66628172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66628172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66628172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66628172 # number of overall hits -system.cpu.icache.overall_hits::total 66628172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1417 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1417 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1417 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1417 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1417 # number of overall misses -system.cpu.icache.overall_misses::total 1417 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51973000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51973000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51973000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51973000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51973000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51973000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66629589 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66629589 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66629589 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66629589 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66629589 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66629589 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 827.655289 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404129 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404129 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66454892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66454892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66454892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66454892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66454892 # number of overall hits +system.cpu.icache.overall_hits::total 66454892 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1390 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1390 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1390 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1390 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1390 # number of overall misses +system.cpu.icache.overall_misses::total 1390 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48196500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48196500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48196500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48196500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48196500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48196500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66456282 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66456282 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66456282 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66456282 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66456282 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66456282 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36678.193366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36678.193366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36678.193366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36678.193366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34673.741007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34673.741007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34673.741007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34673.741007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 321.888467 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 135777000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.413189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999368 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999368 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111075212 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111075212 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38533998 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38533998 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 43 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 43 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149609210 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015541 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015541 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015541 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015541 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14222.446556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14222.446556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25574.823033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25574.823033 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22781.865118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22781.865118 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 260996 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 204500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 99 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2636.323232 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20450 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151094661 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151094661 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151094661 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151094661 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005089 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005089 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.023252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.023252 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009831 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009831 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009831 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5769.397917 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5769.397917 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8313.122423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8313.122423 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 483496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4740.156863 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444797 # number of writebacks -system.cpu.dcache.writebacks::total 444797 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367652 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 367652 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1516116 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1516116 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 444931 # number of writebacks +system.cpu.dcache.writebacks::total 444931 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 357852 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 357852 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 662813 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 662813 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1020665 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1020665 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1020665 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1020665 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210276 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210276 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254510 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464786 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464786 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464786 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464786 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578667000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 578667000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1370952996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1370952996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1949619996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1949619996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1949619996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1949619996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14607.039661 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2751.940307 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2751.940307 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5386.637052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5386.637052 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4194.661621 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 4194.661621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4194.661621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 4194.661621 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 950 # number of replacements -system.cpu.l2cache.tagsinuse 22952.523790 # Cycle average of tags in use -system.cpu.l2cache.total_refs 555154 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23388 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.736703 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 947 # number of replacements +system.cpu.l2cache.tagsinuse 22961.963492 # Cycle average of tags in use +system.cpu.l2cache.total_refs 555516 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23381 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 820.941483 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 615.048815 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.656921 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.025053 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.018770 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.700744 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 205984 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 206005 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 444931 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 444931 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 233372 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464786 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465765 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465765 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020411 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024851 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083054 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083054 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978550 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.054713 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056655 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978550 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.054713 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056655 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 100996 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10499.428571 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1246.864198 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 921 # number of writebacks -system.cpu.l2cache.writebacks::total 921 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4296 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5263 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26395 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26395 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 136100000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167740000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 754125496 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 754125496 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 890225496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 921865496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 890225496 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 921865496 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020447 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083029 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083029 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054729 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056690 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054729 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056690 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32719.751810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31680.633147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31871.556147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35686.423244 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35686.423244 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32719.751810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.654554 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34925.762303 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32719.751810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.654554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34925.762303 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 918 # number of writebacks +system.cpu.l2cache.writebacks::total 918 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4292 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5250 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21138 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26388 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31379500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167175000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913847496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 945226996 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31379500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913847496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 945226996 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083054 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083054 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056655 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056655 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 6b056dd7e..cd0e43aa8 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.764109 # Number of seconds simulated -sim_ticks 764109115000 # Number of ticks simulated -final_tick 764109115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762398 # Number of seconds simulated +sim_ticks 762397656000 # Number of ticks simulated +final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2465110 # Simulator instruction rate (inst/s) -host_op_rate 2465110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3129668646 # Simulator tick rate (ticks/s) -host_mem_usage 218984 # Number of bytes of host memory used -host_seconds 244.15 # Real time elapsed on the host +host_inst_rate 1514073 # Simulator instruction rate (inst/s) +host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1917939864 # Simulator tick rate (ticks/s) +host_mem_usage 219440 # Number of bytes of host memory used +host_seconds 397.51 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25315 # Nu system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory system.physmem.num_writes::total 883 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 65582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2120325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2185908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 65582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 65582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 73958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 73958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 73958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 65582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2120325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2259866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1528218230 # number of cpu cycles simulated +system.cpu.numCycles 1524795312 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1528218230 # Number of busy cycles +system.cpu.num_busy_cycles 1524795312 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.286058 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.286058 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328753 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328753 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44165000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55553.459119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55553.459119 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41780000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41780000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.128141 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 590218000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.128141 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2991812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2991812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4452609000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4452609000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7444421000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7444421000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7444421000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7444421000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16347.173333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16347.173333 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2388116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2388116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3690120000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3690120000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6078236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078236000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6078236000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.tagsinuse 22839.375690 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21645.673483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 668.235332 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 525.466875 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020393 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 3e2378b89..20eccd335 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164735 # Number of seconds simulated -sim_ticks 164735271500 # Number of ticks simulated -final_tick 164735271500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.163008 # Number of seconds simulated +sim_ticks 163008222000 # Number of ticks simulated +final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151833 # Simulator instruction rate (inst/s) -host_op_rate 160438 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43876980 # Simulator tick rate (ticks/s) -host_mem_usage 229232 # Number of bytes of host memory used -host_seconds 3754.48 # Real time elapsed on the host -sim_insts 570052715 # Number of instructions simulated -sim_ops 602360921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1771392 # Number of bytes read from this memory -system.physmem.bytes_read::total 1819904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 204096 # Number of bytes written to this memory -system.physmem.bytes_written::total 204096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27678 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28436 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3189 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3189 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 294485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10752961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11047446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 294485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 294485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1238933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1238933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1238933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 294485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10752961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12286379 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 104701 # Simulator instruction rate (inst/s) +host_op_rate 110635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29939476 # Simulator tick rate (ticks/s) +host_mem_usage 234836 # Number of bytes of host memory used +host_seconds 5444.59 # Real time elapsed on the host +sim_insts 570052710 # Number of instructions simulated +sim_ops 602360916 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1771648 # Number of bytes read from this memory +system.physmem.bytes_read::total 1819712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 204352 # Number of bytes written to this memory +system.physmem.bytes_written::total 204352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27682 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28433 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3193 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3193 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 294856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10868458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11163314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 294856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 294856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1253630 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1253630 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1253630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 294856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10868458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12416944 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329470544 # number of cpu cycles simulated +system.cpu.numCycles 326016445 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85543194 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80343428 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2410851 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47247808 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46879382 # Number of BTB hits +system.cpu.BPredUnit.lookups 85521826 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80321411 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2409005 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47176245 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46862526 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438508 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 957 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68858387 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669531966 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85543194 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48317890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130053558 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13436601 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119467619 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1438689 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 908 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68838729 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669384047 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85521826 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48301215 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130014225 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13401210 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 116068554 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 664 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67410579 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 785974 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329380053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195076 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67395150 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 787497 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 325897750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.188570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.203934 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199326735 60.52% 60.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20925869 6.35% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4976270 1.51% 68.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14401478 4.37% 72.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8915823 2.71% 75.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9447821 2.87% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4394131 1.33% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5797396 1.76% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61194530 18.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 195883756 60.11% 60.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20926266 6.42% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4973061 1.53% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14397687 4.42% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8914249 2.74% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9438407 2.90% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4391608 1.35% 79.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5795696 1.78% 81.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61177020 18.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329380053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259638 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032145 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93515183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96161670 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108196547 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20508331 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10998322 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4720780 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1591 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705885224 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5921 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10998322 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107743564 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14112964 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 43222 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114413091 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82068890 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697152675 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59727344 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20123270 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 641 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723862465 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241326776 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241326648 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 325897750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.262324 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053222 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92928440 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93325217 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108744555 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19925503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10974035 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4721193 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1619 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705690133 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6091 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10974035 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107218931 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12903831 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39750 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114312743 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80448460 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 696999769 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59211261 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 18958262 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 603 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723690859 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3240622549 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3240622421 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419181 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96443284 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2057 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2011 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169978483 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172921644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80622072 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21488970 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28010178 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681988292 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3275 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646797787 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1412727 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79459503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198007283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 345 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329380053 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.727918 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419173 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96271686 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2053 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2007 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169155311 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172874803 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80609628 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21505343 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28086060 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681842513 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3260 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646713779 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1407547 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79314162 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197591004 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 331 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 325897750 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.984407 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.742434 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69019799 20.95% 20.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85512996 25.96% 46.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75829369 23.02% 69.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 41034711 12.46% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28570777 8.67% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15062101 4.57% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5699719 1.73% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6474655 1.97% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2175926 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67307339 20.65% 20.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84522408 25.94% 46.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74985673 23.01% 69.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40267786 12.36% 81.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28844208 8.85% 90.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15117912 4.64% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5722755 1.76% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6923607 2.12% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2206062 0.68% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329380053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 325897750 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206481 5.38% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2616685 68.13% 73.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1017800 26.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205384 5.40% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2833511 74.46% 79.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 766298 20.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403890666 62.44% 62.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6567 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403852803 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6571 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,157 +239,157 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166105526 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76795025 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166065084 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76789318 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646797787 # Type of FU issued -system.cpu.iq.rate 1.963143 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3840966 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005938 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628229284 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761462946 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638497717 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646713779 # Type of FU issued +system.cpu.iq.rate 1.983685 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3805193 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005884 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624538012 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761171255 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638446114 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650638733 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650518952 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30397502 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30376789 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23968825 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 126112 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12134 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10400833 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23921985 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123764 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11533 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10388390 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12732 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35377 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12747 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17143 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10998322 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 671065 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80095 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 681994740 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 717531 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172921644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80622072 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1925 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21947 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12134 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1389665 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1520287 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2909952 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642597340 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163964037 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4200447 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10974035 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 319837 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41126 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 681848951 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 703596 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172874803 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80609628 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 10996 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4141 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11533 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1387510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1519308 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2906818 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642524921 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163926120 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4188858 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3173 # number of nop insts executed -system.cpu.iew.exec_refs 239958391 # number of memory reference insts executed -system.cpu.iew.exec_branches 74720339 # Number of branches executed -system.cpu.iew.exec_stores 75994354 # Number of stores executed -system.cpu.iew.exec_rate 1.950394 # Inst execution rate -system.cpu.iew.wb_sent 639963641 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638497733 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419111890 # num instructions producing a value -system.cpu.iew.wb_consumers 650388459 # num instructions consuming a value +system.cpu.iew.exec_nop 3178 # number of nop insts executed +system.cpu.iew.exec_refs 239918745 # number of memory reference insts executed +system.cpu.iew.exec_branches 74716876 # Number of branches executed +system.cpu.iew.exec_stores 75992625 # Number of stores executed +system.cpu.iew.exec_rate 1.970836 # Inst execution rate +system.cpu.iew.wb_sent 639915699 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638446130 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420790055 # num instructions producing a value +system.cpu.iew.wb_consumers 656091526 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937951 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644402 # average fanout of values written-back +system.cpu.iew.wb_rate 1.958325 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641359 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79643282 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2930 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2409350 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318381732 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.891946 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233867 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79497382 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2929 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2407463 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 314923716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.912720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.240103 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93812247 29.47% 29.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104551370 32.84% 62.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43266938 13.59% 75.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8778657 2.76% 78.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26036096 8.18% 86.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12762730 4.01% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7569326 2.38% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1269179 0.40% 93.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20335189 6.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91160511 28.95% 28.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103755163 32.95% 61.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42928794 13.63% 75.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8971951 2.85% 78.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25547635 8.11% 86.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13484569 4.28% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7640580 2.43% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1100606 0.35% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20333907 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318381732 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052766 # Number of instructions committed -system.cpu.commit.committedOps 602360972 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 314923716 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052761 # Number of instructions committed +system.cpu.commit.committedOps 602360967 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174058 # Number of memory references committed -system.cpu.commit.loads 148952819 # Number of loads committed +system.cpu.commit.refs 219174056 # Number of memory references committed +system.cpu.commit.loads 148952818 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70892750 # Number of branches committed +system.cpu.commit.branches 70892749 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523535 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523531 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20335189 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20333907 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980050185 # The number of ROB reads -system.cpu.rob.rob_writes 1375038514 # The number of ROB writes -system.cpu.timesIdled 6612 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90491 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052715 # Number of Instructions Simulated -system.cpu.committedOps 602360921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052715 # Number of Instructions Simulated -system.cpu.cpi 0.577965 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577965 # CPI: Total CPI of All Threads -system.cpu.ipc 1.730208 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.730208 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210034168 # number of integer regfile reads -system.cpu.int_regfile_writes 664124835 # number of integer regfile writes +system.cpu.rob.rob_reads 976447546 # The number of ROB reads +system.cpu.rob.rob_writes 1374722217 # The number of ROB writes +system.cpu.timesIdled 15150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 118695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052710 # Number of Instructions Simulated +system.cpu.committedOps 602360916 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052710 # Number of Instructions Simulated +system.cpu.cpi 0.571906 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.571906 # CPI: Total CPI of All Threads +system.cpu.ipc 1.748540 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.748540 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3209706655 # number of integer regfile reads +system.cpu.int_regfile_writes 664060053 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 904851739 # number of misc regfile reads -system.cpu.misc_regfile_writes 3108 # number of misc regfile writes -system.cpu.icache.replacements 59 # number of replacements -system.cpu.icache.tagsinuse 698.555131 # Cycle average of tags in use -system.cpu.icache.total_refs 67409471 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81412.404589 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 904689637 # number of misc regfile reads +system.cpu.misc_regfile_writes 3106 # number of misc regfile writes +system.cpu.icache.replacements 58 # number of replacements +system.cpu.icache.tagsinuse 694.540428 # Cycle average of tags in use +system.cpu.icache.total_refs 67394031 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 818 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82388.790954 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 698.555131 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.341091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.341091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67409471 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67409471 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67409471 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67409471 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67409471 # number of overall hits -system.cpu.icache.overall_hits::total 67409471 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses -system.cpu.icache.overall_misses::total 1108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38972000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38972000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38972000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38972000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38972000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38972000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67410579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67410579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67410579 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67410579 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67410579 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67410579 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35173.285199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35173.285199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35173.285199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35173.285199 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 694.540428 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.339131 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.339131 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67394031 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67394031 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67394031 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67394031 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67394031 # number of overall hits +system.cpu.icache.overall_hits::total 67394031 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1119 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1119 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1119 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1119 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1119 # number of overall misses +system.cpu.icache.overall_misses::total 1119 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37389000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37389000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37389000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37389000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37389000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37389000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67395150 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67395150 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67395150 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67395150 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67395150 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67395150 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33412.868633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33412.868633 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33412.868633 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33412.868633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33412.868633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33412.868633 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,309 +398,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 828 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 828 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 828 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 828 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 828 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29096500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29096500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29096500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29096500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29096500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29096500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 301 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 818 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 818 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 818 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 818 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 818 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28166000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28166000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28166000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28166000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28166000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28166000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35140.700483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35140.700483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35140.700483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35140.700483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35140.700483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35140.700483 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34432.762836 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34432.762836 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34432.762836 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34432.762836 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34432.762836 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34432.762836 # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66856753 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1705 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1705 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1553 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1553 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 198864103 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 198864103 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 198864103 # number of overall hits -system.cpu.dcache.overall_hits::total 198864103 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 301339 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 301339 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2560778 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2560778 # number of WriteReq misses +system.cpu.dcache.replacements 440381 # number of replacements +system.cpu.dcache.tagsinuse 4094.318957 # Cycle average of tags in use +system.cpu.dcache.total_refs 200223099 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444477 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 450.468976 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 101578000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.318957 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999590 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999590 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 132093235 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 132093235 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 68126614 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 68126614 # 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number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44140893629 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44140893629 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44140893629 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 132308689 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 132308689 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1507393 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1507393 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1507393 # number of overall misses +system.cpu.dcache.overall_misses::total 1507393 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1206496500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1206496500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11662167592 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11662167592 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 117000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12868664092 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12868664092 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12868664092 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12868664092 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132309711 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132309711 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1727 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1727 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1553 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1553 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201726220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201726220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201726220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201726220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002278 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036889 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.036889 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012739 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012739 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014188 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014188 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014188 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014188 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12251.183883 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12251.183883 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15795.642625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15795.642625 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10886.363636 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10886.363636 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15422.463033 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15422.463033 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30346130 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 47000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2896 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1720 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1720 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1552 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1552 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201727242 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201727242 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201727242 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201727242 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001636 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001636 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018596 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018596 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012791 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012791 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007472 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007472 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007472 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007472 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5573.349933 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5573.349933 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9034.018137 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9034.018137 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 5318.181818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 5318.181818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8537.033204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8537.033204 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28514592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3014 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10478.636050 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9460.714001 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 1000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 420958 # number of writebacks -system.cpu.dcache.writebacks::total 420958 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104059 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104059 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2313654 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2313654 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 421091 # number of writebacks +system.cpu.dcache.writebacks::total 421091 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 19124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 19124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1043792 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1043792 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2417713 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2417713 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2417713 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2417713 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247124 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247124 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444404 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444404 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444404 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444404 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1546585000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1546585000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753575629 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753575629 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4300160629 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4300160629 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4300160629 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4300160629 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1062916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1062916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1062916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1062916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197352 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197352 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247125 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247125 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444477 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444477 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444477 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444477 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 592577000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 592577000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1461825592 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1461825592 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2054402592 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2054402592 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2054402592 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2054402592 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001492 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002203 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002203 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7839.542782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7839.542782 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11142.485671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11142.485671 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9676.241953 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9676.241953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9676.241953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9676.241953 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3002.639953 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3002.639953 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5915.328647 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5915.328647 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4622.067266 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 4622.067266 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4622.067266 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 4622.067266 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 4252 # number of replacements -system.cpu.l2cache.tagsinuse 21908.074402 # Cycle average of tags in use -system.cpu.l2cache.total_refs 504991 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 25291 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 19.967222 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 4254 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36539.853882 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5494 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6245 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22188 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22188 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27682 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 28433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27682 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 28433 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197057000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 900047801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 900047801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24797500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072307301 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1097104801 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24797500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072307301 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1097104801 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089785 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089785 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063852 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063852 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40564.620561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40564.620561 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 7bce23d96..e1fc6c299 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.795271 # Number of seconds simulated -sim_ticks 795270546000 # Number of ticks simulated -final_tick 795270546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.793710 # Number of seconds simulated +sim_ticks 793709507000 # Number of ticks simulated +final_tick 793709507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1274959 # Simulator instruction rate (inst/s) -host_op_rate 1346403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1783406999 # Simulator tick rate (ticks/s) -host_mem_usage 227740 # Number of bytes of host memory used -host_seconds 445.93 # Real time elapsed on the host +host_inst_rate 1083083 # Simulator instruction rate (inst/s) +host_op_rate 1143775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1512037928 # Simulator tick rate (ticks/s) +host_mem_usage 233820 # Number of bytes of host memory used +host_seconds 524.93 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 27110 # Nu system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2181698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2230868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 244888 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 244888 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 244888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2181698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2475756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 49267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2185989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2235256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 245369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 245369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 245369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2185989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2480625 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1590541092 # number of cpu cycles simulated +system.cpu.numCycles 1587419014 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 568539335 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 219173606 # nu system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1590541092 # Number of busy cycles +system.cpu.num_busy_cycles 1587419014 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.715333 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.773227 # Cycle average of tags in use system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.715333 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.282088 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.282088 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 577.773227 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34792000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34792000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34792000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34792000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34792000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34792000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34021000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34021000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34021000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34021000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34021000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34021000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54108.864697 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54108.864697 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54108.864697 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54108.864697 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52909.797823 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52909.797823 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52909.797823 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32863000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32863000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32863000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32863000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32863000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32863000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51108.864697 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51108.864697 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.191707 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.242161 # Cycle average of tags in use system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 547974000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.191707 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999559 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999559 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 529482000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.242161 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2866972000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2866972000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4400884000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4400884000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7267856000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7267856000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7267856000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7267856000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2675478000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2675478000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4151654000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4151654000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6827132000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6827132000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6827132000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6827132000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.953302 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.953302 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17763.550059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17763.550059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16609.812507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16609.812507 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14095.113162 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14095.113162 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16757.568174 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16757.568174 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15602.590707 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15602.590707 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2297524000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2297524000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3657640000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3657640000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5955164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5955164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5955164000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5955164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295846000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295846000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5952004000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5952004000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5952004000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5952004000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.953302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.953302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14763.550059 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14763.550059 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12095.113162 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12095.113162 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 3963 # number of replacements -system.cpu.l2cache.tagsinuse 21579.150724 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 21582.814171 # Cycle average of tags in use system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20939.895204 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 130.071130 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 509.184390 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.639035 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.003969 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.658543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 20943.692003 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 130.073000 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 509.049168 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.639151 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.658655 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits @@ -323,16 +323,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 611 # system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses system.cpu.l2cache.overall_misses::total 27721 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257140000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 288912000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 289092000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1409720000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1441492000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1409900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1441672000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1409720000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1441492000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1409900000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1441672000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) @@ -358,16 +358,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.400404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52032.397408 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52006.493272 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52006.493272 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,16 +390,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197980000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222420000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1108840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084580000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1109020000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1108840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084580000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1109020000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses @@ -412,16 +412,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40036.400404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40032.397408 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index c0dac2931..b8b444d29 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.389171 # Number of seconds simulated -sim_ticks 389171400000 # Number of ticks simulated -final_tick 389171400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.386987 # Number of seconds simulated +sim_ticks 386986985000 # Number of ticks simulated +final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248197 # Simulator instruction rate (inst/s) -host_op_rate 248980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68935275 # Simulator tick rate (ticks/s) -host_mem_usage 223264 # Number of bytes of host memory used -host_seconds 5645.46 # Real time elapsed on the host +host_inst_rate 135169 # Simulator instruction rate (inst/s) +host_op_rate 135595 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37331500 # Simulator tick rate (ticks/s) +host_mem_usage 223688 # Number of bytes of host memory used +host_seconds 10366.23 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1679232 # Number of bytes read from this memory -system.physmem.bytes_read::total 1757760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory -system.physmem.bytes_written::total 163392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26238 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27465 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 201783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4314891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4516673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 419846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 419846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 419846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4314891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4936519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679104 # Number of bytes read from this memory +system.physmem.bytes_read::total 1757888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163264 # Number of bytes written to this memory +system.physmem.bytes_written::total 163264 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26236 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27467 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2551 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2551 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 203583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4338916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4542499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 421885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 421885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 421885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4338916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4964384 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778342801 # number of cpu cycles simulated +system.cpu.numCycles 773973971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98197174 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88413236 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3785239 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66015510 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65664831 # Number of BTB hits +system.cpu.BPredUnit.lookups 98196903 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88415122 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3785922 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66048945 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65663541 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1336 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 1365 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165881717 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648798034 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98197174 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65666167 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330411204 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21674066 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264316803 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 122 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2684 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162819499 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755607 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778298468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.124294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 165893347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648920679 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98196903 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65664906 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330423745 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21687705 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 259909474 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2700 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162828772 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 752135 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 773928223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.136454 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.151019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447887264 57.55% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28163510 3.62% 76.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18828809 2.42% 79.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11510131 1.48% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3871378 0.50% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 443504478 57.31% 57.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74374556 9.61% 66.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37974673 4.91% 71.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9085275 1.17% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28162152 3.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18827829 2.43% 79.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11514662 1.49% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3870211 0.50% 81.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146614387 18.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778298468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126162 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.118344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217730424 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214714897 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285147825 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43019384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17685938 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642518992 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17685938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241679770 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36912628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51960576 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303022356 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 127037200 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631180439 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 31545211 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73402475 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3147906 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360824399 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755700072 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721856567 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33843505 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 773928223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126874 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.130460 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 216918337 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 211126972 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285339114 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42844971 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17698829 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642655288 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17698829 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 240878845 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33665029 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51866735 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303087743 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126731042 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631322359 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 30917915 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73728979 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3098650 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360964482 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755920727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2722080159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33840568 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116053960 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2679524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2694715 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 273063750 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438707438 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180249753 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255184370 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82754827 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1516941659 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2635026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460769058 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54636 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113641063 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136677185 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778298468 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.427909 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116194043 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2680701 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2696386 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 272557720 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438727279 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180254007 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255223658 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82981799 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517066880 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2635302 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460886365 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45400 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113758577 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136602100 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 391631 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 773928223 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.887625 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.429425 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147064058 18.90% 18.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 186545303 23.97% 42.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210910021 27.10% 69.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70782478 9.09% 95.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7762489 1.00% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 144009666 18.61% 18.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 185251464 23.94% 42.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210317974 27.18% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131221648 16.96% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70752732 9.14% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20294392 2.62% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7875333 1.02% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4040989 0.52% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 164025 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778298468 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 773928223 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113664 7.00% 7.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 166579 10.26% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1139492 70.19% 87.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 203791 12.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90190 5.49% 5.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 99214 6.04% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1093274 66.56% 78.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 359776 21.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867086456 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867180921 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2642669 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2647347 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -193,84 +193,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419773044 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171266889 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419785067 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171273030 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460769058 # Type of FU issued -system.cpu.iq.rate 1.876768 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1623526 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001111 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3683829702 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624339460 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444358901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17685044 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9115270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8537907 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453371392 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9021192 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215484580 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460886365 # Type of FU issued +system.cpu.iq.rate 1.887514 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1642454 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001124 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3679668823 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624597420 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444476565 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17719984 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9099813 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8555773 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453469070 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9059749 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215381487 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36194595 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55177 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245195 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13401611 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36214436 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54352 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244694 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13405865 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3537 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56120 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3598 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17685938 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1543124 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 135108 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613772123 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4123534 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438707438 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180249753 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549312 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 88176 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3284 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245195 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2354964 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1564711 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3919675 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455222367 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417054039 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5546691 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17698829 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 443700 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14828 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613898358 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4123447 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438727279 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180254007 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2549639 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8198 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1497 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244694 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2356359 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1563564 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3919923 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455334067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417065579 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5552298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94195438 # number of nop insts executed -system.cpu.iew.exec_refs 587626307 # number of memory reference insts executed -system.cpu.iew.exec_branches 89109233 # Number of branches executed -system.cpu.iew.exec_stores 170572268 # Number of stores executed -system.cpu.iew.exec_rate 1.869642 # Inst execution rate -system.cpu.iew.wb_sent 1453822475 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452896808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154316776 # num instructions producing a value -system.cpu.iew.wb_consumers 1205166275 # num instructions consuming a value +system.cpu.iew.exec_nop 94196176 # number of nop insts executed +system.cpu.iew.exec_refs 587643036 # number of memory reference insts executed +system.cpu.iew.exec_branches 89109340 # Number of branches executed +system.cpu.iew.exec_stores 170577457 # Number of stores executed +system.cpu.iew.exec_rate 1.880340 # Inst execution rate +system.cpu.iew.wb_sent 1453944636 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1453032338 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154452527 # num instructions producing a value +system.cpu.iew.wb_consumers 1205669839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.866654 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back +system.cpu.iew.wb_rate 1.877366 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957520 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124161815 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124266701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3785239 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760613141 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.958319 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.503249 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3785922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756230005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.969670 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506799 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 241688690 31.78% 31.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276879555 36.40% 68.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43195229 5.68% 73.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54904670 7.22% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19686776 2.59% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13341139 1.75% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30448610 4.00% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10352976 1.36% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70115496 9.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 237695032 31.43% 31.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276589849 36.57% 68.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43049426 5.69% 73.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54802104 7.25% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19618852 2.59% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13377170 1.77% 85.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30585382 4.04% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10542801 1.39% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69969389 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760613141 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756230005 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -281,70 +281,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70115496 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69969389 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304117872 # The number of ROB reads -system.cpu.rob.rob_writes 3245080355 # The number of ROB writes -system.cpu.timesIdled 1467 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2299985729 # The number of ROB reads +system.cpu.rob.rob_writes 3245302839 # The number of ROB writes +system.cpu.timesIdled 3314 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 45748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.555487 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555487 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800221 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800221 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980525328 # number of integer regfile reads -system.cpu.int_regfile_writes 1276196147 # number of integer regfile writes -system.cpu.fp_regfile_reads 16956232 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491758 # number of floating regfile writes -system.cpu.misc_regfile_reads 593298094 # number of misc regfile reads +system.cpu.cpi 0.552369 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552369 # CPI: Total CPI of All Threads +system.cpu.ipc 1.810383 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.810383 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980648344 # number of integer regfile reads +system.cpu.int_regfile_writes 1276312589 # number of integer regfile writes +system.cpu.fp_regfile_reads 16966196 # number of floating regfile reads +system.cpu.fp_regfile_writes 10497856 # number of floating regfile writes +system.cpu.misc_regfile_reads 593314657 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 214 # number of replacements -system.cpu.icache.tagsinuse 1046.066234 # Cycle average of tags in use -system.cpu.icache.total_refs 162817587 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1362 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119543.015419 # Average number of references to valid blocks. +system.cpu.icache.replacements 209 # number of replacements +system.cpu.icache.tagsinuse 1046.532429 # Cycle average of tags in use +system.cpu.icache.total_refs 162826872 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1358 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119901.967599 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1046.066234 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510775 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510775 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162817587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162817587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162817587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162817587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162817587 # number of overall hits -system.cpu.icache.overall_hits::total 162817587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1912 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1912 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1912 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1912 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1912 # number of overall misses -system.cpu.icache.overall_misses::total 1912 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62928500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62928500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62928500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62928500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62928500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62928500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162819499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162819499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162819499 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162819499 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162819499 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162819499 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1046.532429 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.511002 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.511002 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162826872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162826872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162826872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162826872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162826872 # number of overall hits +system.cpu.icache.overall_hits::total 162826872 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1900 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1900 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1900 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1900 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1900 # number of overall misses +system.cpu.icache.overall_misses::total 1900 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60525500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60525500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60525500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60525500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60525500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60525500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162828772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162828772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162828772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162828772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162828772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162828772 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32912.395397 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 32912.395397 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 32912.395397 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 32912.395397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 32912.395397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 32912.395397 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31855.526316 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31855.526316 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31855.526316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31855.526316 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,248 +353,248 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 549 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 549 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 549 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 549 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 549 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1363 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1363 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1363 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1363 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1363 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1363 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44825000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 44825000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44825000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 44825000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44825000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 44825000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 541 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 541 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 541 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 541 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 541 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1359 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1359 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1359 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1359 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1359 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1359 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44484500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 44484500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44484500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 44484500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44484500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 44484500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32887.013940 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32887.013940 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34733.424358 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2551 # number of writebacks +system.cpu.l2cache.writebacks::total 2551 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1231 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4442 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5673 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21794 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21794 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27467 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26236 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27467 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39025000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138834500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177859500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 777128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 777128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39025000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915963000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 954988000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39025000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915963000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 954988000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022179 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083149 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083149 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056740 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059228 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056740 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059228 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31701.868400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31254.952724 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31351.930196 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35657.910434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35657.910434 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 3078a0fec..c111732e8 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.063178 # Number of seconds simulated -sim_ticks 2063177737000 # Number of ticks simulated -final_tick 2063177737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.061067 # Number of seconds simulated +sim_ticks 2061066683000 # Number of ticks simulated +final_tick 2061066683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1527975 # Simulator instruction rate (inst/s) -host_op_rate 1532517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2122729697 # Simulator tick rate (ticks/s) -host_mem_usage 231576 # Number of bytes of host memory used -host_seconds 971.95 # Real time elapsed on the host +host_inst_rate 1352034 # Simulator instruction rate (inst/s) +host_op_rate 1356054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1876383782 # Simulator tick rate (ticks/s) +host_mem_usage 222536 # Number of bytes of host memory used +host_seconds 1098.43 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26134 # Nu system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 31858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 810680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 842537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 31858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 31858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 31858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 31890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 843400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31890 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31890 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78344 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78344 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 921744 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4126355474 # number of cpu cycles simulated +system.cpu.numCycles 4122133366 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108088 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365766 # nu system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4126355474 # Number of busy cycles +system.cpu.num_busy_cycles 4122133366 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.409378 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.468708 # Cycle average of tags in use system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.409378 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 906.468708 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58777000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58777000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58777000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 57527000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 57527000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 57527000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 57527000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 57527000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 57527000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53095.754291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53095.754291 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53095.754291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53095.754291 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51966.576332 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51966.576332 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51966.576332 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51966.576332 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55456000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55456000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 55313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 55313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55313000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 55313000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50095.754291 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50095.754291 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49966.576332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49966.576332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.205181 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.236029 # Cycle average of tags in use system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 588931000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.205181 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 559332000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.236029 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses system.cpu.dcache.overall_misses::total 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888728000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2888728000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554574000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4554574000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294542000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4294542000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6989368000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6989368000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6989368000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6989368000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14929.907073 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14929.907073 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17535.937596 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17535.937596 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16423.371741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16423.371741 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.767141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.767141 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15421.783087 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214 system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2308270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2308270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775390000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6083660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6083660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6083660000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6083660000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11929.907073 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11929.907073 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14535.937596 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14535.937596 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22185.384813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22187.209427 # Cycle average of tags in use system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20828.536507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.441709 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.406597 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677044 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 20830.496331 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 857.499465 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.213631 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635696 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.026169 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015235 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677100 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits @@ -292,17 +292,17 @@ system.cpu.l2cache.demand_misses::total 27161 # nu system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses system.cpu.l2cache.overall_misses::total 27161 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53406000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 275652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 275654000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53406000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1412372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53404000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 1412374000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53406000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1412372000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1412374000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) @@ -327,17 +327,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.059783 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.947420 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.377287 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.073635 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.073635 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,17 +359,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27161 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41082000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212042000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41082000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1086440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41080000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1086442000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41082000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1086440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1086442000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.947420 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.377287 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 7a2ddd771..bad8d0f8e 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,171 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.609567 # Number of seconds simulated -sim_ticks 609566727000 # Number of ticks simulated -final_tick 609566727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.609798 # Number of seconds simulated +sim_ticks 609797568500 # Number of ticks simulated +final_tick 609797568500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62263 # Simulator instruction rate (inst/s) -host_op_rate 114724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43127912 # Simulator tick rate (ticks/s) -host_mem_usage 276908 # Number of bytes of host memory used -host_seconds 14133.93 # Real time elapsed on the host +host_inst_rate 67150 # Simulator instruction rate (inst/s) +host_op_rate 123728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46530668 # Simulator tick rate (ticks/s) +host_mem_usage 230840 # Number of bytes of host memory used +host_seconds 13105.28 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694464 # Number of bytes read from this memory -system.physmem.bytes_read::total 1752832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162880 # Number of bytes written to this memory -system.physmem.bytes_written::total 162880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 912 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26476 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2545 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2545 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2779784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2875538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 267206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 267206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 267206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2779784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3142744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 58112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694784 # Number of bytes read from this memory +system.physmem.bytes_read::total 1752896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162816 # Number of bytes written to this memory +system.physmem.bytes_written::total 162816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26481 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2544 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2544 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2779257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2874554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2779257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3141554 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1219133455 # number of cpu cycles simulated +system.cpu.numCycles 1219595138 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 154519843 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 154519843 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26678926 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77274626 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76985066 # Number of BTB hits +system.cpu.BPredUnit.lookups 153419281 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 153419281 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26709105 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 75190754 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 74807048 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180157368 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1482244654 # Number of instructions fetch has processed -system.cpu.fetch.Branches 154519843 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76985066 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400441074 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91643666 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 573697614 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 180231048 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1488409356 # Number of instructions fetch has processed +system.cpu.fetch.Branches 153419281 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 74807048 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 400557825 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92407802 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 573234633 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186403933 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9747583 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1219106465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.078734 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.272852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 185924931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9228337 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1219569114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.084484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.278873 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 825883799 67.75% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24475369 2.01% 69.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15188361 1.25% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18161843 1.49% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26717986 2.19% 74.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18155688 1.49% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28775832 2.36% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39425650 3.23% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 222321937 18.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 826230375 67.75% 67.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23815932 1.95% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15671088 1.28% 70.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17469051 1.43% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26718016 2.19% 74.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18180169 1.49% 76.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 27807273 2.28% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39426907 3.23% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224250303 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1219106465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126746 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215818 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289371714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497062295 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275168406 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92693923 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 64810127 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2355715170 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 64810127 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337830723 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122995154 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1813 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305493642 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387975006 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2259654010 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242278891 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120849469 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2627164074 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5766696541 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5766690921 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5620 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1219569114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125795 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.220413 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 289356881 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 496684656 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 275171365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92810894 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65545318 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2357736314 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 65545318 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 337721602 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 122595128 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1576 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 305744833 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387960657 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2261287899 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242284686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120945759 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2627574208 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5773835618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5773831438 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4180 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740268817 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 96 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 730471883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 541137404 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220343917 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 347951990 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144808328 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2010997367 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 534 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784139180 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 263264 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 389085977 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 810611327 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 484 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1219106465 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.463481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.418984 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 740678951 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 84 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 730447231 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 543232760 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220439884 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 349480208 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144920713 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2014741693 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 481 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1784164311 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 260366 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 392823529 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 821144040 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1219569114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.462946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418593 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 363767078 29.84% 29.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365542734 29.98% 59.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234442506 19.23% 79.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141155043 11.58% 90.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 61085427 5.01% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39802416 3.26% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10825326 0.89% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1946919 0.16% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 539016 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 363999611 29.85% 29.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 365670586 29.98% 59.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234855592 19.26% 79.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 140866108 11.55% 90.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60913141 4.99% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 40023537 3.28% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10789680 0.88% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1930984 0.16% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 519875 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1219106465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1219569114 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 465020 16.12% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2178971 75.55% 91.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 240132 8.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 467350 16.09% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2184649 75.23% 91.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 251796 8.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46815442 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065636060 59.73% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46816435 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065676196 59.73% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued @@ -194,84 +193,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478995198 26.85% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192692480 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478957046 26.84% 89.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192714634 10.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784139180 # Type of FU issued -system.cpu.iq.rate 1.463449 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2884123 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001617 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4790531580 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2400258808 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725049081 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 632 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1764 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740207554 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209593506 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1784164311 # Type of FU issued +system.cpu.iq.rate 1.462915 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2903795 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001628 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4791061390 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2407739950 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1725073479 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 507 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1436 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740251451 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 220 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209520869 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 122095283 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38780 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 181714 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32157860 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 124190639 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36910 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180735 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 32253827 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2258 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 452 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2057 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 64810127 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 288054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 51315 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2010997901 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63873969 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 541137404 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220343917 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 29041 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 466 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 181714 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2119314 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24709049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26828363 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766210973 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474185905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17928207 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65545318 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 120938 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15130 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2014742174 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63913352 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 543232760 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220439884 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7621 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180735 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2120344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24738064 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26858408 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766248435 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474148133 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17915876 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666011474 # number of memory reference insts executed -system.cpu.iew.exec_branches 110196607 # Number of branches executed -system.cpu.iew.exec_stores 191825569 # Number of stores executed -system.cpu.iew.exec_rate 1.448743 # Inst execution rate -system.cpu.iew.wb_sent 1726341541 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725049244 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267580159 # num instructions producing a value -system.cpu.iew.wb_consumers 1828717326 # num instructions consuming a value +system.cpu.iew.exec_refs 665987460 # number of memory reference insts executed +system.cpu.iew.exec_branches 110190116 # Number of branches executed +system.cpu.iew.exec_stores 191839327 # Number of stores executed +system.cpu.iew.exec_rate 1.448225 # Inst execution rate +system.cpu.iew.wb_sent 1726426595 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1725073583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267591282 # num instructions producing a value +system.cpu.iew.wb_consumers 1828482722 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.414980 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.693153 # average fanout of values written-back +system.cpu.iew.wb_rate 1.414464 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.693248 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 389506426 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 393250539 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26678961 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1154296338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.404747 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.831971 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26709142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1154023796 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.405078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832959 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 420857241 36.46% 36.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 413520492 35.82% 72.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87361055 7.57% 79.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122186130 10.59% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24494860 2.12% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23109073 2.00% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18457710 1.60% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12056348 1.04% 97.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32253429 2.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 421087806 36.49% 36.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 412894237 35.78% 72.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87424698 7.58% 79.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122293813 10.60% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24525346 2.13% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22502511 1.95% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19027826 1.65% 96.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12052514 1.04% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32215045 2.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1154296338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1154023796 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -282,68 +281,68 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32253429 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32215045 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3133043260 # The number of ROB reads -system.cpu.rob.rob_writes 4086848885 # The number of ROB writes -system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3136553215 # The number of ROB reads +system.cpu.rob.rob_writes 4095072141 # The number of ROB writes +system.cpu.timesIdled 539 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26024 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.385339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.385339 # CPI: Total CPI of All Threads -system.cpu.ipc 0.721845 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.721845 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541474948 # number of integer regfile reads -system.cpu.int_regfile_writes 1975063996 # number of integer regfile writes -system.cpu.fp_regfile_reads 163 # number of floating regfile reads -system.cpu.misc_regfile_reads 910391945 # number of misc regfile reads -system.cpu.icache.replacements 26 # number of replacements -system.cpu.icache.tagsinuse 823.006550 # Cycle average of tags in use -system.cpu.icache.total_refs 186402559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 924 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201734.371212 # Average number of references to valid blocks. +system.cpu.cpi 1.385864 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.385864 # CPI: Total CPI of All Threads +system.cpu.ipc 0.721572 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.721572 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3541346034 # number of integer regfile reads +system.cpu.int_regfile_writes 1975100349 # number of integer regfile writes +system.cpu.fp_regfile_reads 104 # number of floating regfile reads +system.cpu.misc_regfile_reads 910400266 # number of misc regfile reads +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 820.177123 # Cycle average of tags in use +system.cpu.icache.total_refs 185923597 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 202310.769314 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 823.006550 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.401859 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.401859 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186402560 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186402560 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186402560 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186402560 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186402560 # number of overall hits -system.cpu.icache.overall_hits::total 186402560 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1373 # number of overall misses -system.cpu.icache.overall_misses::total 1373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48027000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48027000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48027000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48027000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48027000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48027000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186403933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186403933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186403933 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186403933 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186403933 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186403933 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 820.177123 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.400477 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.400477 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 185923597 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 185923597 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 185923597 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 185923597 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 185923597 # number of overall hits +system.cpu.icache.overall_hits::total 185923597 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1334 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1334 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1334 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1334 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1334 # number of overall misses +system.cpu.icache.overall_misses::total 1334 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44859000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44859000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44859000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44859000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44859000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44859000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 185924931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 185924931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 185924931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 185924931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 185924931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 185924931 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34979.606701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34979.606701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34979.606701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34979.606701 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33627.436282 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33627.436282 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33627.436282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33627.436282 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,94 +351,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 446 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 446 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 446 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 446 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 446 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 446 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 927 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 927 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 927 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 927 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 927 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 927 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33886000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33886000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33886000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33886000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33886000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33886000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 415 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 415 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 415 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 415 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 415 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 415 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 919 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 919 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 919 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 919 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33142500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33142500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33142500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33142500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33142500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33142500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36554.476807 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36554.476807 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36554.476807 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36554.476807 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.476807 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.476807 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36063.656148 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36063.656148 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36063.656148 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36063.656148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36063.656148 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36063.656148 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445317 # number of replacements -system.cpu.dcache.tagsinuse 4093.312668 # Cycle average of tags in use -system.cpu.dcache.total_refs 452320188 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449413 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1006.468856 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 738501000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.312668 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999344 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999344 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264380337 # 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number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 454579 # number of overall misses -system.cpu.dcache.overall_misses::total 454579 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1325128000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1325128000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2053821500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2053821500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 3378949500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 3378949500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 3378949500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 3378949500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264588707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264588707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 445640 # number of replacements +system.cpu.dcache.tagsinuse 4093.409130 # Cycle average of tags in use +system.cpu.dcache.total_refs 452355828 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449736 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1005.825257 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 723009000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.409130 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999367 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999367 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264416053 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264416053 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939775 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939775 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452355828 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452355828 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452355828 # number of overall hits +system.cpu.dcache.overall_hits::total 452355828 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 208185 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 208185 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246282 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246282 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 454467 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 454467 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 454467 # number of overall misses +system.cpu.dcache.overall_misses::total 454467 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 988643000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 988643000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1714858500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1714858500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2703501500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2703501500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2703501500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2703501500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264624238 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264624238 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452774764 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452774764 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452774764 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452774764 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000788 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000788 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 452810295 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452810295 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452810295 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452810295 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000787 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000787 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001004 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.001004 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001004 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001004 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6359.495129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 6359.495129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8341.780763 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8341.780763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7433.140334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7433.140334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7433.140334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7433.140334 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4748.867594 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 4748.867594 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 6962.987551 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 6962.987551 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 5948.730051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 5948.730051 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,136 +447,132 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428431 # number of writebacks -system.cpu.dcache.writebacks::total 428431 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5144 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5144 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5161 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5161 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5161 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5161 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203226 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203226 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246192 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246192 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449418 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449418 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449418 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449418 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 609204500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 609204500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1249438500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1249438500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1858643000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1858643000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1858643000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1858643000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000768 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000768 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 428671 # number of writebacks +system.cpu.dcache.writebacks::total 428671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4720 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4720 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4729 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4729 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4729 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4729 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246273 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246273 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449738 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449738 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 561387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 561387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1222169500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1222169500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1783557000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1783557000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1783557000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1783557000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000769 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000993 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2997.670082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2997.670082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5075.057272 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5075.057272 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4135.666573 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4135.666573 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4135.666573 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4135.666573 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2759.135478 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2759.135478 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 4962.661355 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 4962.661355 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3965.768959 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3965.768959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3965.768959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3965.768959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2664 # number of replacements -system.cpu.l2cache.tagsinuse 22189.826884 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517514 # Total number of references to valid blocks. +system.cpu.l2cache.replacements 2661 # number of replacements +system.cpu.l2cache.tagsinuse 22190.588854 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517940 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24220 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.367217 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 21.384806 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20789.410931 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 824274500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 853560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022373 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026715 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060776 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060776 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32252.753304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31121.594903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31309.706960 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31128.140818 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31128.140818 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 045a8ad7b..e35ba34dd 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.801980 # Number of seconds simulated -sim_ticks 1801979679000 # Number of ticks simulated -final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.800193 # Number of seconds simulated +sim_ticks 1800193072000 # Number of ticks simulated +final_tick 1800193072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 528145 # Simulator instruction rate (inst/s) -host_op_rate 973136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1081454463 # Simulator tick rate (ticks/s) -host_mem_usage 274856 # Number of bytes of host memory used -host_seconds 1666.26 # Real time elapsed on the host +host_inst_rate 480678 # Simulator instruction rate (inst/s) +host_op_rate 885676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 983283018 # Simulator tick rate (ticks/s) +host_mem_usage 228792 # Number of bytes of host memory used +host_seconds 1830.80 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26287 # Nu system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 933622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25643 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25643 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 89146 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 89146 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 89146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 934549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 89235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 89235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 89235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 934549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1049452 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3603959358 # number of cpu cycles simulated +system.cpu.numCycles 3600386144 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025278 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228178 # nu system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3603959358 # Number of busy cycles +system.cpu.num_busy_cycles 3600386144 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.169550 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.197374 # Cycle average of tags in use system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.169550 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 660.197374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.icache.overall_misses::total 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40521000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40521000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40521000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39710000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39710000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39710000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39710000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39710000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39710000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56123.268698 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56123.268698 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56123.268698 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56123.268698 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722 system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38355000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38355000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38355000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38355000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38355000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38355000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53123.268698 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53123.268698 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.884130 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.905905 # Cycle average of tags in use system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 788810000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.884130 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 771462000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.905905 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses system.cpu.dcache.overall_misses::total 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2948308000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2948308000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4362877000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4362877000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7311185000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4104707000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4104707000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6851259000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6851259000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6851259000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6851259000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.305251 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.305251 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17827.890423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17827.890423 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16539.346406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16539.346406 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16772.938273 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16772.938273 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15498.902834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15498.902834 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048 system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2356330000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2356330000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3628711000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3628711000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5985041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5985041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5985041000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5985041000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615263000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615263000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967163000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5967163000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967163000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5967163000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11941.305251 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11941.305251 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14827.890423 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14827.890423 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14772.938273 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14772.938273 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2581 # number of replacements -system.cpu.l2cache.tagsinuse 22161.850174 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22163.399604 # Cycle average of tags in use system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21018.400685 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 596.832055 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.617434 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.676326 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21020.012941 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 596.858262 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.528401 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641480 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018215 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.676373 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits @@ -272,14 +272,14 @@ system.cpu.l2cache.overall_misses::total 27009 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1142440000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1142440000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143021000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1143021000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1366924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1404468000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1367505000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1405049000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1366924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1404468000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1367505000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1405049000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) @@ -307,14 +307,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.061000 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.445152 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.445152 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52021.511348 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52021.511348 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -339,14 +339,14 @@ system.cpu.l2cache.overall_mshr_misses::total 27009 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 878800000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 878800000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879381000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879381000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1051480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1080360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052061000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1080941000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1051480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1080360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052061000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1080941000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses @@ -361,14 +361,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40026.445152 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40026.445152 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 1a08f1a5c..b0555a54b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.028506 # Number of seconds simulated -sim_ticks 28505597000 # Number of ticks simulated -final_tick 28505597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025432 # Number of seconds simulated +sim_ticks 25432499000 # Number of ticks simulated +final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145688 # Simulator instruction rate (inst/s) -host_op_rate 146734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45838175 # Simulator tick rate (ticks/s) -host_mem_usage 362080 # Number of bytes of host memory used -host_seconds 621.87 # Real time elapsed on the host -sim_insts 90599368 # Number of instructions simulated -sim_ops 91249921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 993216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 712 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15519 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1598563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33244278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34842842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1598563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1598563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1598563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33244278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34842842 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 141358 # Simulator instruction rate (inst/s) +host_op_rate 142373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39681246 # Simulator tick rate (ticks/s) +host_mem_usage 367916 # Number of bytes of host memory used +host_seconds 640.92 # Real time elapsed on the host +sim_insts 90599358 # Number of instructions simulated +sim_ops 91249911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory +system.physmem.bytes_read::total 992960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1786690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37256268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39042958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1786690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1786690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1786690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37256268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 39042958 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,320 +70,318 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 57011195 # number of cpu cycles simulated +system.cpu.numCycles 50864999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27014403 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22277078 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 889929 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11548760 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11430884 # Number of BTB hits +system.cpu.BPredUnit.lookups 26815832 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22064400 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 887268 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11482840 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11353380 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 73122 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 372 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14508892 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129672886 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27014403 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11504006 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24367767 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4991272 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14021743 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 72941 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 493 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14339573 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128641990 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26815832 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11426321 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24202315 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4802086 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8372764 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14122126 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 347107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 56945823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.293943 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.179113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14019260 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 376949 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 50826068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549806 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252225 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 32616008 57.28% 57.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3437208 6.04% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033940 3.57% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1577922 2.77% 69.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1684600 2.96% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3016320 5.30% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1478308 2.60% 80.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1110359 1.95% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9991158 17.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 26661639 52.46% 52.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3429294 6.75% 59.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2034587 4.00% 63.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1568872 3.09% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1675049 3.30% 69.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2962794 5.83% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1484032 2.92% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1105241 2.17% 80.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9904560 19.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 56945823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.473844 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.274516 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17727827 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11442534 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22314035 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1422886 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4038541 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4486849 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8989 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127753929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42812 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4038541 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19463622 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5507295 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 178125 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21532560 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6225680 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124585344 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 540744 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4833961 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11275 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145162652 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 542774349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 542766580 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37733154 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6541 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6539 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14204519 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29836795 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5560829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2097523 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1243222 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119152184 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10385 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105702713 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27697349 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68611569 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 56945823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.856198 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.856170 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 50826068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.527196 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.529087 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16897392 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6458273 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22716084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 851770 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3902549 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4473858 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8976 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126855886 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42929 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3902549 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18614164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1601921 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 162955 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21830794 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4713685 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123685119 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 281691 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3991082 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 144136379 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 538783715 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 538776344 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7371 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36706897 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6468 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 10859255 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29577544 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5541374 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2075747 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1267218 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118433426 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105554764 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 73541 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26995758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 66330940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 50826068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.076784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.959181 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17311609 30.40% 30.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13029602 22.88% 53.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8527913 14.98% 68.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6948954 12.20% 80.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5271164 9.26% 89.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2793517 4.91% 94.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2152448 3.78% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 481434 0.85% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 429182 0.75% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13833219 27.22% 27.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10749724 21.15% 48.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7931783 15.61% 63.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6457025 12.70% 76.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4857915 9.56% 86.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3493885 6.87% 93.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2371067 4.67% 97.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 608688 1.20% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 522762 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 56945823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 50826068 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 40477 6.05% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 349114 52.21% 58.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 279085 41.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 142420 18.36% 18.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 354766 45.74% 64.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 278332 35.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74715129 70.68% 70.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10969 0.01% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 226 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 287 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25832645 24.44% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5143450 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74645911 70.72% 70.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10962 0.01% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 239 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 298 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25762945 24.41% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5134404 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105702713 # Type of FU issued -system.cpu.iq.rate 1.854069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 668703 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006326 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 269098152 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146861999 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102960296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1111 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1652 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 475 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106370866 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 550 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 430808 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105554764 # Type of FU issued +system.cpu.iq.rate 2.075194 # Inst issue rate +system.cpu.iq.fu_busy_cnt 775545 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262783539 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 145440732 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102807034 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1143 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1553 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 495 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106329739 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 570 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 435536 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7260915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7599 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 814071 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7001666 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7849 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3639 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 794618 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 165011 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13641 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4038541 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 891747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 116973 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119175285 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342275 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29836795 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5560829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6480 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49074 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 478618 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 473981 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 952599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104642381 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25500898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1060332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3902549 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 96175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18780 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118456487 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 345131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29577544 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5541374 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6439 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4015 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3639 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 474441 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 478533 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 952974 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104393226 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25307547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1161538 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12716 # number of nop insts executed -system.cpu.iew.exec_refs 30579562 # number of memory reference insts executed -system.cpu.iew.exec_branches 21366362 # Number of branches executed -system.cpu.iew.exec_stores 5078664 # Number of stores executed -system.cpu.iew.exec_rate 1.835471 # Inst execution rate -system.cpu.iew.wb_sent 103249709 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102960771 # cumulative count of insts written-back -system.cpu.iew.wb_producers 61941288 # num instructions producing a value -system.cpu.iew.wb_consumers 102916553 # num instructions consuming a value +system.cpu.iew.exec_nop 12717 # number of nop insts executed +system.cpu.iew.exec_refs 30377969 # number of memory reference insts executed +system.cpu.iew.exec_branches 21353332 # Number of branches executed +system.cpu.iew.exec_stores 5070422 # Number of stores executed +system.cpu.iew.exec_rate 2.052359 # Inst execution rate +system.cpu.iew.wb_sent 103118433 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102807529 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62180383 # num instructions producing a value +system.cpu.iew.wb_consumers 104132992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.805975 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601859 # average fanout of values written-back +system.cpu.iew.wb_rate 2.021184 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.597125 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27915285 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 881077 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52907283 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.724952 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.476924 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 27194508 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 878429 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 46923520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.944921 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.520501 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22917585 43.32% 43.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13525297 25.56% 68.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4253401 8.04% 76.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3602316 6.81% 83.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1554565 2.94% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 724715 1.37% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 894547 1.69% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 264490 0.50% 90.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5170367 9.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16620645 35.42% 35.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13501207 28.77% 64.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4487454 9.56% 73.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3864489 8.24% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1521327 3.24% 85.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 782022 1.67% 86.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 855558 1.82% 88.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 262372 0.56% 89.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5028446 10.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52907283 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611977 # Number of instructions committed -system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 46923520 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611967 # Number of instructions committed +system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322638 # Number of memory references committed -system.cpu.commit.loads 22575880 # Number of loads committed +system.cpu.commit.refs 27322634 # Number of memory references committed +system.cpu.commit.loads 22575878 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734218 # Number of branches committed +system.cpu.commit.branches 18734216 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533330 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5170367 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5028446 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 166908997 # The number of ROB reads -system.cpu.rob.rob_writes 242415249 # The number of ROB writes -system.cpu.timesIdled 17140 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65372 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599368 # Number of Instructions Simulated -system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated -system.cpu.cpi 0.629267 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.629267 # CPI: Total CPI of All Threads -system.cpu.ipc 1.589150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.589150 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497539806 # number of integer regfile reads -system.cpu.int_regfile_writes 120848373 # number of integer regfile writes -system.cpu.fp_regfile_reads 239 # number of floating regfile reads -system.cpu.fp_regfile_writes 624 # number of floating regfile writes -system.cpu.misc_regfile_reads 183493284 # number of misc regfile reads -system.cpu.misc_regfile_writes 11612 # number of misc regfile writes +system.cpu.rob.rob_reads 160346368 # The number of ROB reads +system.cpu.rob.rob_writes 240838970 # The number of ROB writes +system.cpu.timesIdled 1282 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38931 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599358 # Number of Instructions Simulated +system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated +system.cpu.cpi 0.561428 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561428 # CPI: Total CPI of All Threads +system.cpu.ipc 1.781173 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.781173 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496237676 # number of integer regfile reads +system.cpu.int_regfile_writes 120715642 # number of integer regfile writes +system.cpu.fp_regfile_reads 235 # number of floating regfile reads +system.cpu.fp_regfile_writes 643 # number of floating regfile writes +system.cpu.misc_regfile_reads 182128613 # number of misc regfile reads +system.cpu.misc_regfile_writes 11608 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 636.231301 # Cycle average of tags in use -system.cpu.icache.total_refs 14121140 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 635.871073 # Cycle average of tags in use +system.cpu.icache.total_refs 14018279 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 738 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19134.336043 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18994.957995 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 636.231301 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.310660 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.310660 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14121140 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14121140 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14121140 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14121140 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14121140 # number of overall hits -system.cpu.icache.overall_hits::total 14121140 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 986 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 986 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 986 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 986 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 986 # number of overall misses -system.cpu.icache.overall_misses::total 986 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35670500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35670500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35670500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35670500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35670500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35670500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14122126 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14122126 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14122126 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14122126 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14122126 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14122126 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.871073 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310484 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310484 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14018279 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14018279 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14018279 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14018279 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14018279 # number of overall hits +system.cpu.icache.overall_hits::total 14018279 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 981 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 981 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 981 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 981 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 981 # number of overall misses +system.cpu.icache.overall_misses::total 981 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34205000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34205000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34205000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34205000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34205000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34205000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14019260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14019260 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14019260 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14019260 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14019260 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14019260 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36176.977688 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36176.977688 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36176.977688 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36176.977688 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34867.482161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34867.482161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34867.482161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34867.482161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34867.482161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,246 +390,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 738 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 738 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 738 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 738 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26658000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26658000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26658000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26658000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26658000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26658000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36121.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36121.951220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26308000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26308000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35647.696477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35647.696477 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35647.696477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35647.696477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943542 # number of replacements -system.cpu.dcache.tagsinuse 3691.655008 # Cycle average of tags in use -system.cpu.dcache.total_refs 28378395 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947638 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.946451 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8118725000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3691.655008 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.901283 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.901283 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23798260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23798260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4568472 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4568472 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5862 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5862 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28366732 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28366732 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28366732 # number of overall hits -system.cpu.dcache.overall_hits::total 28366732 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1060889 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1060889 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 166509 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 166509 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1227398 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1227398 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1227398 # number of overall misses -system.cpu.dcache.overall_misses::total 1227398 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21973475500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21973475500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6211010261 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6211010261 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 161000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 161000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28184485761 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28184485761 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28184485761 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28184485761 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24859149 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24859149 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 943636 # number of replacements +system.cpu.dcache.tagsinuse 3643.742201 # Cycle average of tags in use +system.cpu.dcache.total_refs 28404607 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947732 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.971138 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8103531000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3643.742201 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.889585 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.889585 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23813813 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23813813 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4579150 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4579150 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5845 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5845 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28392963 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28392963 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28392963 # number of overall hits +system.cpu.dcache.overall_hits::total 28392963 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 995922 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 995922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 155831 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 155831 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1151753 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1151753 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1151753 # number of overall misses +system.cpu.dcache.overall_misses::total 1151753 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4102006500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4102006500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4011864060 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4011864060 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 120000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8113870560 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8113870560 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8113870560 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8113870560 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24809735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24809735 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5870 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5870 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29594130 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29594130 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29594130 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29594130 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042676 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.042676 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.035166 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001363 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001363 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20712.322873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20712.322873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37301.348642 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37301.348642 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22962.792640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22962.792640 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78891432 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5852 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5852 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29544716 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29544716 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29544716 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29544716 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040142 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040142 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032911 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001196 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001196 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038983 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038983 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038983 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038983 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4118.802979 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 4118.802979 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25744.967689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25744.967689 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17142.857143 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9153 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8619.188463 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1374.477220 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942894 # number of writebacks -system.cpu.dcache.writebacks::total 942894 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148366 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 148366 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131394 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131394 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 279760 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 279760 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 279760 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279760 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912523 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 912523 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35115 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 35115 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16758552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16758552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1752488893 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1752488893 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18511040893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18511040893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18511040893 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18511040893 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036708 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036708 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007416 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007416 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18365.073538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18365.073538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49907.130656 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412223 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.449438 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33818.014706 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32965.955285 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.078431 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.078431 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 977 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15515 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9078500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32316500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 451969500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 451969500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23238000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 461048000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484286000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23238000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 461048000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484286000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001069 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419931 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016358 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32729.577465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34001.872659 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33077.277380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31088.836154 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31088.836154 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32729.577465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31214.050918 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 3cd60c7e5..9850fa37f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148268 # Number of seconds simulated -sim_ticks 148267705000 # Number of ticks simulated -final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.147136 # Number of seconds simulated +sim_ticks 147135976000 # Number of ticks simulated +final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1153616 # Simulator instruction rate (inst/s) -host_op_rate 1161887 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1888384270 # Simulator tick rate (ticks/s) -host_mem_usage 360564 # Number of bytes of host memory used -host_seconds 78.52 # Real time elapsed on the host +host_inst_rate 1039833 # Simulator instruction rate (inst/s) +host_op_rate 1047288 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1689137215 # Simulator tick rate (ticks/s) +host_mem_usage 366884 # Number of bytes of host memory used +host_seconds 87.11 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 36992 # Nu system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 249495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6372042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6621536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 249495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 249495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 249495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6372042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6621536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 251414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6421054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6672467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 251414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 296535410 # number of cpu cycles simulated +system.cpu.numCycles 294271952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 27318810 # nu system.cpu.num_load_insts 22573966 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 296535410 # Number of busy cycles +system.cpu.num_busy_cycles 294271952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.369252 # Cycle average of tags in use +system.cpu.icache.tagsinuse 510.071144 # Cycle average of tags in use system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.369252 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.249204 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.249204 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.249058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32709000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32709000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32709000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32709000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32709000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32709000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32063000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32063000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32063000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32063000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32063000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32063000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54606.010017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54606.010017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54606.010017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54606.010017 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53527.545910 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30912000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30912000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51606.010017 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51606.010017 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3568.972050 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54491057000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3568.972050 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.871331 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.871331 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses system.cpu.dcache.overall_misses::total 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12648933000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12648933000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1288595000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1288595000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13937528000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13937528000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13937528000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13937528000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14051.419202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14051.419202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27646.913686 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27646.913686 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14720.698607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14720.698607 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798 system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9948366000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9948366000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148768000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148768000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11097134000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11097134000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11097134000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11097134000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11051.419202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11051.419202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24646.913686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24646.913686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9602.986186 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8914.312589 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 495.421771 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 193.251826 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.272043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.015119 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.293060 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.291909 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 44702e46f..e3f69f56e 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.362482 # Number of seconds simulated -sim_ticks 362481563000 # Number of ticks simulated -final_tick 362481563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361489 # Number of seconds simulated +sim_ticks 361488530000 # Number of ticks simulated +final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1415125 # Simulator instruction rate (inst/s) -host_op_rate 1415183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2103788292 # Simulator tick rate (ticks/s) -host_mem_usage 363728 # Number of bytes of host memory used -host_seconds 172.30 # Real time elapsed on the host +host_inst_rate 1171246 # Simulator instruction rate (inst/s) +host_op_rate 1171295 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1736457304 # Simulator tick rate (ticks/s) +host_mem_usage 354676 # Number of bytes of host memory used +host_seconds 208.18 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 724963126 # number of cpu cycles simulated +system.cpu.numCycles 722977060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 724963126 # Number of busy cycles +system.cpu.num_busy_cycles 722977060 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 25 # number of replacements -system.cpu.icache.tagsinuse 725.564713 # Cycle average of tags in use +system.cpu.icache.tagsinuse 725.412977 # Cycle average of tags in use system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 725.564713 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55933.106576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55933.106576 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46687000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46687000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements -system.cpu.dcache.tagsinuse 3563.804941 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134384267000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3563.804941 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12510586000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12510586000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14664.344320 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14664.344320 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9832015000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9832015000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1127418000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1127418000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 89000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 89000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10959433000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10959433000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10959433000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10959433000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -237,30 +237,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 9744.633464 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8861.505031 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 738.799835 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 144.328599 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.297383 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.296955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 516126aba..cad348d1e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,174 +1,174 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064346 # Number of seconds simulated -sim_ticks 64346040000 # Number of ticks simulated -final_tick 64346040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061487 # Number of seconds simulated +sim_ticks 61487437500 # Number of ticks simulated +final_tick 61487437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132449 # Simulator instruction rate (inst/s) -host_op_rate 233222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53944275 # Simulator tick rate (ticks/s) -host_mem_usage 365660 # Number of bytes of host memory used -host_seconds 1192.82 # Real time elapsed on the host +host_inst_rate 86290 # Simulator instruction rate (inst/s) +host_op_rate 151942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33582980 # Simulator tick rate (ticks/s) +host_mem_usage 365956 # Number of bytes of host memory used +host_seconds 1830.91 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1893376 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1893056 # Number of bytes read from this memory +system.physmem.bytes_read::total 1961408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20416 # Number of bytes written to this memory -system.physmem.bytes_written::total 20416 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory +system.physmem.bytes_written::total 20288 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29584 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory -system.physmem.num_writes::total 319 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 29424903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 317284 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 29424903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30804444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 29579 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30647 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory +system.physmem.num_writes::total 317 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1111642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30787687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31899329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1111642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1111642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 329954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 329954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 329954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1111642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30787687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32229283 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 128692081 # number of cpu cycles simulated +system.cpu.numCycles 122974876 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 35576702 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1085312 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25399500 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25270525 # Number of BTB hits +system.cpu.BPredUnit.lookups 35563581 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 35563581 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1083908 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25421016 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25287599 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27884150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 193525000 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35576702 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25270525 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 58636506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7358089 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35916291 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27160167 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 295674 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128658357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.644591 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27814300 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 193613700 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35563581 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25287599 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 58598336 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7345607 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 30298263 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 223 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 27172491 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 322176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 122946211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.768410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.402032 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 72765830 56.56% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2056683 1.60% 58.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3006413 2.34% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4027268 3.13% 63.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8003806 6.22% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5026752 3.91% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2893556 2.25% 76.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1437345 1.12% 77.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29440704 22.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67085101 54.56% 54.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2067083 1.68% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2985500 2.43% 58.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3997651 3.25% 61.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7978379 6.49% 68.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5028202 4.09% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2861375 2.33% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1431598 1.16% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29511322 24.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128658357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.276448 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.503783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39452105 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 27727798 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46961382 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8295915 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6221157 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336436945 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 6221157 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44164076 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5970160 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9070 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50268632 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22025262 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 331751360 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 262 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6842 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20121054 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 216 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 334012838 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 880453680 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 880451759 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1921 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 122946211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289194 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.574417 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38912587 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 22600530 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 48050125 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7147919 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6235050 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336030812 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 6235050 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43304200 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3170225 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8978 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 50645325 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19582433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 332156996 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3311 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 17907327 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 182 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 334503257 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 881229115 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 881227036 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2079 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 54800094 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 485 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 50437110 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104594760 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36334761 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 41480583 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6245732 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 323452648 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 55290513 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 484 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44388140 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104937995 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36474446 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 41500364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5836392 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 323873529 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307818254 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198387 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 45033296 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65280307 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 307729409 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 216713 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 45479887 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 66424397 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128658357 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.392524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.788521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 122946211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.502960 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.799833 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25721748 19.99% 19.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18649480 14.50% 34.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 23014823 17.89% 52.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 27362657 21.27% 73.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 17010472 13.22% 86.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9600725 7.46% 94.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6243189 4.85% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 895594 0.70% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 159669 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21631935 17.59% 17.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17051158 13.87% 31.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24526773 19.95% 51.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 23966381 19.49% 70.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19143829 15.57% 86.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9189049 7.47% 93.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5012385 4.08% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2266917 1.84% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 157784 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128658357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 122946211 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35279 1.70% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1868126 90.18% 91.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 168108 8.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 50945 1.97% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1871750 72.23% 74.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 668572 25.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 29245 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174946374 56.83% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33168 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174887442 56.83% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 52 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued @@ -194,84 +194,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99043059 32.18% 89.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33799538 10.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98817076 32.11% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33991671 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307818254 # Type of FU issued -system.cpu.iq.rate 2.391897 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2071513 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006730 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 746564211 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 368519272 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304587112 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 554 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 943 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 186 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 309860246 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 276 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52574701 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307729409 # Type of FU issued +system.cpu.iq.rate 2.502376 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2591267 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008421 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 741212334 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 369384855 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304533759 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 675 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 209 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 310287186 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 322 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52324197 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13815376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 44181 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33341 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4895010 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14158611 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 53020 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 31592 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5034695 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 36659 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3174 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6221157 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 782061 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 89817 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 323454406 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 362446 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104594760 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36334761 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 480 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 611 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 22270 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33341 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 595275 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 582931 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1178206 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305708901 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98426933 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2109353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6235050 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 247932 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19449 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 323875287 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 344865 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104937995 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36474446 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 247 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31592 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 595265 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 583416 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1178681 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305536893 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98199399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2192516 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131805652 # number of memory reference insts executed -system.cpu.iew.exec_branches 31122940 # Number of branches executed -system.cpu.iew.exec_stores 33378719 # Number of stores executed -system.cpu.iew.exec_rate 2.375507 # Inst execution rate -system.cpu.iew.wb_sent 305078305 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304587298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 225979119 # num instructions producing a value -system.cpu.iew.wb_consumers 311384301 # num instructions consuming a value +system.cpu.iew.exec_refs 131640830 # number of memory reference insts executed +system.cpu.iew.exec_branches 31219911 # Number of branches executed +system.cpu.iew.exec_stores 33441431 # Number of stores executed +system.cpu.iew.exec_rate 2.484547 # Inst execution rate +system.cpu.iew.wb_sent 304949933 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304533968 # cumulative count of insts written-back +system.cpu.iew.wb_producers 225863686 # num instructions producing a value +system.cpu.iew.wb_consumers 311805704 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.366791 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.725724 # average fanout of values written-back +system.cpu.iew.wb_rate 2.476392 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724373 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 45269554 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 45684582 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1085338 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122437200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.272124 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.827291 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1083935 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 116711161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.383598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.781080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 46942462 38.34% 38.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 21185475 17.30% 55.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15973782 13.05% 68.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12948459 10.58% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1961875 1.60% 80.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1887285 1.54% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1388960 1.13% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 594855 0.49% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 19554047 15.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38716768 33.17% 33.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22386952 19.18% 52.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17053265 14.61% 66.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13105313 11.23% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048873 1.76% 79.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3220721 2.76% 82.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1361336 1.17% 83.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 627536 0.54% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18190397 15.59% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122437200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 116711161 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -282,69 +282,69 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 19554047 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18190397 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 426345169 # The number of ROB reads -system.cpu.rob.rob_writes 653150724 # The number of ROB writes -system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33724 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 422397808 # The number of ROB reads +system.cpu.rob.rob_writes 653994696 # The number of ROB writes +system.cpu.timesIdled 646 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28665 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.814566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.814566 # CPI: Total CPI of All Threads -system.cpu.ipc 1.227648 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.227648 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 598601369 # number of integer regfile reads -system.cpu.int_regfile_writes 305356910 # number of integer regfile writes -system.cpu.fp_regfile_reads 165 # number of floating regfile reads -system.cpu.fp_regfile_writes 88 # number of floating regfile writes -system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads -system.cpu.icache.replacements 92 # number of replacements -system.cpu.icache.tagsinuse 843.498155 # Cycle average of tags in use -system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. +system.cpu.cpi 0.778378 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.778378 # CPI: Total CPI of All Threads +system.cpu.ipc 1.284722 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.284722 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 598611638 # number of integer regfile reads +system.cpu.int_regfile_writes 305159096 # number of integer regfile writes +system.cpu.fp_regfile_reads 198 # number of floating regfile reads +system.cpu.fp_regfile_writes 109 # number of floating regfile writes +system.cpu.misc_regfile_reads 195504004 # number of misc regfile reads +system.cpu.icache.replacements 86 # number of replacements +system.cpu.icache.tagsinuse 846.025687 # Cycle average of tags in use +system.cpu.icache.total_refs 27171094 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1075 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25275.436279 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 843.498155 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27158782 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27158782 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27158782 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27158782 # number of overall hits -system.cpu.icache.overall_hits::total 27158782 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses -system.cpu.icache.overall_misses::total 1385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51455500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51455500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51455500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51455500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51455500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51455500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27160167 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27160167 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27160167 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 846.025687 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.413098 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.413098 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 27171094 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27171094 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27171094 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27171094 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27171094 # number of overall hits +system.cpu.icache.overall_hits::total 27171094 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1397 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1397 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1397 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1397 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1397 # number of overall misses +system.cpu.icache.overall_misses::total 1397 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49824500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49824500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49824500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49824500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49824500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49824500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27172491 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27172491 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27172491 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27172491 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27172491 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27172491 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37151.985560 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37151.985560 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37151.985560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37151.985560 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35665.354331 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35665.354331 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35665.354331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35665.354331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35665.354331 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,94 +353,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 307 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 307 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 307 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 307 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39438000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39438000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39438000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39438000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39438000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39438000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 320 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 320 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 320 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 320 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39164500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39164500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39164500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39164500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39164500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39164500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36584.415584 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36584.415584 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36364.438254 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36364.438254 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36364.438254 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36364.438254 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072148 # number of replacements -system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use -system.cpu.dcache.total_refs 74824983 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076244 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36.038627 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21783897000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.029897 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994148 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994148 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 43467724 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 43467724 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31357249 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31357249 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 74824973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 74824973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 74824973 # number of overall hits -system.cpu.dcache.overall_hits::total 74824973 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2321557 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2321557 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82502 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82502 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2404059 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2404059 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45789281 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2071944 # number of replacements +system.cpu.dcache.tagsinuse 4071.467534 # Cycle average of tags in use +system.cpu.dcache.total_refs 74936342 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076040 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 36.095808 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21468323000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4071.467534 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994011 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994011 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 43578741 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 43578741 # 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number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77229032 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77229032 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77229032 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77229032 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050701 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050701 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.031129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.031129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8353.697109 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8353.697109 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19053.332040 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19053.332040 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8720.884970 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8720.884970 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8720.884970 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 77275046 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77275046 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77275046 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77275046 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002613 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.030265 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.030265 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.030265 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.030265 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4039.213553 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 4039.213553 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15712.999026 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15712.999026 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 4449.318514 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 4449.318514 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 4449.318514 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,140 +449,138 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2064775 # number of writebacks -system.cpu.dcache.writebacks::total 2064775 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 327358 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 327358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 327811 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 327811 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 327811 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 327811 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994199 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82049 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82049 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076248 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076248 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076248 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076248 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8452133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8452133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1314555500 # 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number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 262670 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 262670 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 262670 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 262670 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1993983 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1993983 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82061 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82061 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076044 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076044 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076044 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076044 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4061724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4061724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125939500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125939500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5187664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5187664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5187664000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5187664000 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 38066500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1010362500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1048429000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1075 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1993904 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1994979 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2064785 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2064785 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82155 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82155 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076246 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077322 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076246 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077322 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000830 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352943 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352943 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014249 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014756 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35468.164794 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35535.326087 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34181.423724 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34181.423724 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82138 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82138 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076042 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077117 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076042 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077117 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993488 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000294 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352979 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352979 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993488 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014248 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993488 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014248 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35642.790262 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35973.549488 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35759.975816 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34121.408616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34121.408616 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34209.841094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35642.790262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.102032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34209.841094 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,60 +589,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 319 # number of writebacks -system.cpu.l2cache.writebacks::total 319 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks +system.cpu.l2cache.writebacks::total 317 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1656 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 586 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1654 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29579 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30647 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952810000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34498500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952810000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352943 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32301.966292 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.952381 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32374.396135 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 29579 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30647 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34670500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19225500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53896000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34670500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918354000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 953024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34670500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918354000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 953024500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352979 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352979 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32463.014981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32808.020478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32585.247884 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.916670 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.916670 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 197e85700..0458ec538 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.368209 # Number of seconds simulated -sim_ticks 368209206000 # Number of ticks simulated -final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365994 # Number of seconds simulated +sim_ticks 365994481000 # Number of ticks simulated +final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 501886 # Simulator instruction rate (inst/s) -host_op_rate 883741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1169699500 # Simulator tick rate (ticks/s) -host_mem_usage 408944 # Number of bytes of host memory used -host_seconds 314.79 # Real time elapsed on the host +host_inst_rate 452383 # Simulator instruction rate (inst/s) +host_op_rate 796575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1047986231 # Simulator tick rate (ticks/s) +host_mem_usage 363904 # Number of bytes of host memory used +host_seconds 349.24 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 29370 # Nu system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory system.physmem.num_writes::total 227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5104924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5245366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5104924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5284822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 736418412 # number of cpu cycles simulated +system.cpu.numCycles 731988962 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 122219135 # nu system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 736418412 # Number of busy cycles +system.cpu.num_busy_cycles 731988962 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.897748 # Cycle average of tags in use +system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.897748 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45336000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45336000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45336000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56108.910891 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56108.910891 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56108.910891 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56108.910891 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42912000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42912000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42912000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42912000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53108.910891 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53108.910891 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.463619 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126234066000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.463619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27487330000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27487330000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2708348000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2708348000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14018.998123 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14018.998123 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25524.206241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25524.206241 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14609.664370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14609.664370 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21605170000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21605170000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2390019500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2390019500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23995189500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23995189500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23995189500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23995189500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386364000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386364000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968690000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23968690000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968690000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23968690000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11018.998123 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11018.998123 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22524.192104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22524.192104 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.741681 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.741681 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.842313 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 19722.099231 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19679.255550 # Cycle average of tags in use system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19370.045173 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 209.723718 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 142.330341 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.601871 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 19326.193704 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 210.694953 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 142.366893 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.589789 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006430 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.004345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.600563 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits @@ -272,14 +272,14 @@ system.cpu.l2cache.overall_misses::total 30178 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1509433500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509435000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1509435000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1527269500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1569285500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1527271000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1569287000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1527269500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1569285500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1527271000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1569287000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) @@ -307,14 +307,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.014595 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.016295 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.016295 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.067971 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.067971 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.977533 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.027238 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.977533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.055499 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.027238 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 5b82c90b2..5a3a68b8e 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.205973 # Number of seconds simulated -sim_ticks 205972871500 # Number of ticks simulated -final_tick 205972871500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.201852 # Number of seconds simulated +sim_ticks 201852280500 # Number of ticks simulated +final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120709 # Simulator instruction rate (inst/s) -host_op_rate 135980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48850733 # Simulator tick rate (ticks/s) -host_mem_usage 233344 # Number of bytes of host memory used -host_seconds 4216.37 # Real time elapsed on the host +host_inst_rate 114620 # Simulator instruction rate (inst/s) +host_op_rate 129121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45458575 # Simulator tick rate (ticks/s) +host_mem_usage 239092 # Number of bytes of host memory used +host_seconds 4440.36 # Real time elapsed on the host sim_insts 508955133 # Number of instructions simulated sim_ops 573341693 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10022656 # Number of bytes read from this memory -system.physmem.bytes_read::total 10241664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6678912 # Number of bytes written to this memory -system.physmem.bytes_written::total 6678912 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156604 # Number of read requests responded to by this memory -system.physmem.num_reads::total 160026 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104358 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104358 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1063286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48660078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49723364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1063286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1063286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 32426173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 32426173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 32426173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1063286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48660078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82149537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10015872 # Number of bytes read from this memory +system.physmem.bytes_read::total 10234688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6679360 # Number of bytes written to this memory +system.physmem.bytes_written::total 6679360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156498 # Number of read requests responded to by this memory +system.physmem.num_reads::total 159917 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104365 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1084040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 49619811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50703851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1084040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1084040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 33090337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 33090337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 33090337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1084040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 49619811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 83794188 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,246 +77,246 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 411945744 # number of cpu cycles simulated +system.cpu.numCycles 403704562 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 184506499 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 144023121 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7811219 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 98943918 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 90574887 # Number of BTB hits +system.cpu.BPredUnit.lookups 183613146 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 143294212 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7789120 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 98042390 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 90143773 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12841570 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116417 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 119775248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 774733961 # Number of instructions fetch has processed -system.cpu.fetch.Branches 184506499 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103416457 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 173948363 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37641339 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 87608822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 852 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 115427194 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2630422 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 410365766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.121718 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.964259 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12795154 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116199 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 119018383 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 771038085 # Number of instructions fetch has processed +system.cpu.fetch.Branches 183613146 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 102938927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 173093371 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 37034444 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 81728576 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 114776707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2639607 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 402291353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.154621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.975773 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236430239 57.61% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14468090 3.53% 61.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23474699 5.72% 66.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23086036 5.63% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21070083 5.13% 77.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13375231 3.26% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13311792 3.24% 84.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12219273 2.98% 87.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52930323 12.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229210831 56.98% 56.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14330362 3.56% 60.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23398991 5.82% 66.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22962860 5.71% 72.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20943651 5.21% 77.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13279878 3.30% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13299573 3.31% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12124758 3.01% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52740449 13.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 410365766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.447890 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.880670 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 130418481 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 81705760 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 163995815 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5288696 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 28957014 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26711151 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78514 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 846352874 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312360 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 28957014 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 138753027 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8994220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57785261 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 160771479 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15104765 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 816103533 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1687 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2833405 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8341364 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 82 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 971919658 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3572964194 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3572962534 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 402291353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.454821 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.909907 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129139991 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76355942 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 163648868 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4771100 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 28375452 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26593121 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78321 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 842377409 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 313716 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 28375452 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 137010485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5387793 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57527480 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 160406240 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13583903 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 812203916 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 883 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2847047 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7163226 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 967528997 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3555884446 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3555882861 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1585 # Number of floating rename lookups system.cpu.rename.CommittedMaps 672200147 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 299719511 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3043063 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3043057 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48313295 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173521024 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75304332 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27654560 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15950244 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 766864948 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4467940 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 673990845 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544807 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 195857289 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 503525509 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746826 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 410365766 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.642415 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726112 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 295328850 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3042535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3042531 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44411709 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172477044 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75019988 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27139166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 14058077 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 762853534 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467400 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 672309193 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1597303 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 191893802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 493277148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746286 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 402291353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148669222 36.23% 36.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76514251 18.65% 54.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69467282 16.93% 71.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 54325200 13.24% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31258060 7.62% 92.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16137199 3.93% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9372373 2.28% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3363475 0.82% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1258704 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9421817 2.34% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3434032 0.85% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1296489 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 410365766 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 402291353 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 465577 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6648335 68.74% 73.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2557266 26.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 436530 4.38% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6785214 68.04% 72.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2750735 27.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 452813787 67.18% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386318 0.06% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 155728522 23.11% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65062093 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451600936 67.17% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 386071 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 155208445 23.09% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65113622 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 673990845 # Type of FU issued -system.cpu.iq.rate 1.636116 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9671178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014349 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1769563162 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 967995399 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 653126941 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 279 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 672309193 # Type of FU issued +system.cpu.iq.rate 1.665350 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9972479 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014833 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1758479254 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 960016621 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 651381097 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 683661882 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8511001 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 682281537 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8428766 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 46747987 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 44107 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 809559 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17700373 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 45704007 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43585 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 806080 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17416029 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1145 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19464 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 28957014 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4178303 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 271851 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 772908179 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1249751 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173521024 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75304332 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2979209 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 139047 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8399 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 809559 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4765794 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4187317 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8953111 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 663675930 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 152077702 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10314915 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 28375452 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1989251 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 96453 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 768887058 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1243291 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172477044 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75019988 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2978672 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38122 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5312 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 806080 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4756345 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4163931 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8920276 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 661932492 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151574229 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10376701 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1575291 # number of nop insts executed -system.cpu.iew.exec_refs 215744053 # number of memory reference insts executed -system.cpu.iew.exec_branches 139807568 # Number of branches executed -system.cpu.iew.exec_stores 63666351 # Number of stores executed -system.cpu.iew.exec_rate 1.611076 # Inst execution rate -system.cpu.iew.wb_sent 658363692 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 653126957 # cumulative count of insts written-back -system.cpu.iew.wb_producers 376897633 # num instructions producing a value -system.cpu.iew.wb_consumers 649094102 # num instructions consuming a value +system.cpu.iew.exec_nop 1566124 # number of nop insts executed +system.cpu.iew.exec_refs 215230219 # number of memory reference insts executed +system.cpu.iew.exec_branches 139385144 # Number of branches executed +system.cpu.iew.exec_stores 63655990 # Number of stores executed +system.cpu.iew.exec_rate 1.639646 # Inst execution rate +system.cpu.iew.wb_sent 656632887 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 651381113 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375930281 # num instructions producing a value +system.cpu.iew.wb_consumers 649035735 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.585468 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580652 # average fanout of values written-back +system.cpu.iew.wb_rate 1.613509 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579214 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 198243748 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 194215600 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3721114 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7735785 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 381408753 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.506745 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186982 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7713933 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 373915902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.536938 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.196487 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 167968054 44.04% 44.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103591951 27.16% 71.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34406436 9.02% 80.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19105358 5.01% 85.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16473336 4.32% 89.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7646678 2.00% 91.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6906631 1.81% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3084312 0.81% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22225997 5.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 161102013 43.09% 43.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102670077 27.46% 70.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 34449601 9.21% 79.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18433917 4.93% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17480337 4.67% 89.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7750601 2.07% 91.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6975147 1.87% 93.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3144360 0.84% 94.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21909849 5.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 381408753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 373915902 # Number of insts commited each cycle system.cpu.commit.committedInsts 510299017 # Number of instructions committed system.cpu.commit.committedOps 574685577 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,69 +327,69 @@ system.cpu.commit.branches 122291783 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 473701621 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22225997 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 21909849 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1132104943 # The number of ROB reads -system.cpu.rob.rob_writes 1574958649 # The number of ROB writes -system.cpu.timesIdled 76497 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1579978 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1120900092 # The number of ROB reads +system.cpu.rob.rob_writes 1566319482 # The number of ROB writes +system.cpu.timesIdled 51224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1413209 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 508955133 # Number of Instructions Simulated system.cpu.committedOps 573341693 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 508955133 # Number of Instructions Simulated -system.cpu.cpi 0.809395 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809395 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235491 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235491 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3096810735 # number of integer regfile reads -system.cpu.int_regfile_writes 761477780 # number of integer regfile writes +system.cpu.cpi 0.793203 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.793203 # CPI: Total CPI of All Threads +system.cpu.ipc 1.260712 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.260712 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3088645957 # number of integer regfile reads +system.cpu.int_regfile_writes 759574381 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1003236717 # number of misc regfile reads +system.cpu.misc_regfile_reads 999041226 # number of misc regfile reads system.cpu.misc_regfile_writes 4464048 # number of misc regfile writes -system.cpu.icache.replacements 15737 # number of replacements -system.cpu.icache.tagsinuse 1093.946958 # Cycle average of tags in use -system.cpu.icache.total_refs 115407568 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17598 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6557.993408 # Average number of references to valid blocks. +system.cpu.icache.replacements 15551 # number of replacements +system.cpu.icache.tagsinuse 1091.493459 # Cycle average of tags in use +system.cpu.icache.total_refs 114757583 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17412 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6590.718068 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1093.946958 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.534154 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.534154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 115407568 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 115407568 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 115407568 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 115407568 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 115407568 # number of overall hits -system.cpu.icache.overall_hits::total 115407568 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19626 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19626 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19626 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19626 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19626 # number of overall misses -system.cpu.icache.overall_misses::total 19626 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 282974000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 282974000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 282974000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 282974000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 282974000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 282974000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115427194 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115427194 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115427194 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115427194 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115427194 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115427194 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000170 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000170 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000170 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000170 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000170 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000170 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14418.322633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14418.322633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14418.322633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14418.322633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14418.322633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14418.322633 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1091.493459 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.532956 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.532956 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114757583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114757583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114757583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114757583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114757583 # number of overall hits +system.cpu.icache.overall_hits::total 114757583 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19124 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19124 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19124 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19124 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19124 # number of overall misses +system.cpu.icache.overall_misses::total 19124 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 228709500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 228709500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 228709500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 228709500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 228709500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 228709500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114776707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114776707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114776707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114776707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114776707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114776707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000167 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000167 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000167 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000167 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000167 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000167 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11959.291989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11959.291989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11959.291989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11959.291989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,254 +398,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1971 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1971 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1971 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1971 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1971 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1971 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17655 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17655 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17655 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17655 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17655 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17655 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184079500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 184079500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184079500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 184079500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184079500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 184079500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10426.479751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10426.479751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10426.479751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10426.479751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10426.479751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10426.479751 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1676 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1676 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1676 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1676 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1676 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1676 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17448 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17448 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17448 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17448 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17448 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17448 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154473000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 154473000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154473000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 154473000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154473000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 154473000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000152 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000152 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000152 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8853.335626 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8853.335626 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1189180 # number of replacements -system.cpu.dcache.tagsinuse 4054.532653 # Cycle average of tags in use -system.cpu.dcache.total_refs 194989715 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1193276 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.407053 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4672860000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.532653 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989876 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989876 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137842002 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137842002 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52682481 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52682481 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233095 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1187048 # number of replacements +system.cpu.dcache.tagsinuse 4054.257449 # Cycle average of tags in use +system.cpu.dcache.total_refs 194842504 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1191144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.575944 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4633717000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4054.257449 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989809 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989809 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137485453 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137485453 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52891890 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52891890 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233029 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2233029 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 2232023 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 2232023 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 190524483 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 190524483 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 190524483 # number of overall hits -system.cpu.dcache.overall_hits::total 190524483 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1271675 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1271675 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1556825 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1556825 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2828500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2828500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2828500 # number of overall misses -system.cpu.dcache.overall_misses::total 2828500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15608550500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15608550500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33157971000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33157971000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 519500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 519500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48766521500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48766521500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48766521500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48766521500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 139113677 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 139113677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 190377343 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 190377343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 190377343 # number of overall hits +system.cpu.dcache.overall_hits::total 190377343 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1221436 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1221436 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1347416 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1347416 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 47 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 47 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2568852 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2568852 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2568852 # number of overall misses +system.cpu.dcache.overall_misses::total 2568852 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9648379000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9648379000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23124597500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23124597500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 412500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 412500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32772976500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32772976500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32772976500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32772976500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 138706889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 138706889 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233138 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233138 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233076 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2233076 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232023 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 2232023 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 193352983 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 193352983 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 193352983 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 193352983 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009141 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009141 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028703 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028703 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014629 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014629 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014629 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014629 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12274.009083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12274.009083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21298.457437 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21298.457437 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12081.395349 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12081.395349 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17241.124801 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17241.124801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17241.124801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17241.124801 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 192946195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192946195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192946195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192946195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008806 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008806 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024842 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024842 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000021 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000021 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013314 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013314 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013314 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013314 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7899.209619 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7899.209619 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17162.181168 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17162.181168 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8776.595745 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8776.595745 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3198500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 556 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5752.697842 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1103627 # number of writebacks -system.cpu.dcache.writebacks::total 1103627 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 426551 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 426551 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1208619 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1208619 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1635170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1635170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1635170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1635170 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 845124 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 845124 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348206 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348206 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1193330 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1193330 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1193330 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1193330 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807719000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807719000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284226501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284226501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9091945501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9091945501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9091945501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9091945501 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006075 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006075 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006172 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006172 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006172 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006172 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5688.773482 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5688.773482 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12303.712460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12303.712460 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7618.970026 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7618.970026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7618.970026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7618.970026 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks +system.cpu.dcache.writebacks::total 1101507 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 378352 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 378352 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 999317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 999317 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 47 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1377669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1377669 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1377669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1377669 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843084 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 843084 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348099 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348099 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1191183 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1191183 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1191183 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1191183 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3511124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3511124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4141906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4141906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7653031000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7653031000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7653031000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7653031000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006078 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006078 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006418 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006418 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006174 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006174 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4164.620014 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4164.620014 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11898.645213 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11898.645213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 128816 # number of replacements -system.cpu.l2cache.tagsinuse 26503.825438 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1724855 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 160033 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 10.778121 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 106591903000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22677.867679 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 308.367342 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3517.590417 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.692074 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.009411 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.107348 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.808833 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14164 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 788094 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 802258 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1103627 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1103627 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 50 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 248556 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 248556 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065673 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.102564 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.102564 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296724 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296724 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.132321 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.132321 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32595.203276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31634.348613 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31692.518814 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.744539 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.744539 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.379310 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31168.985665 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31191.917614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.379310 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31168.985665 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31191.917614 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31090.669167 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31090.669167 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 3143a40a6..27346e35d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.720346 # Number of seconds simulated -sim_ticks 720345914000 # Number of ticks simulated -final_tick 720345914000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.717833 # Number of seconds simulated +sim_ticks 717832876000 # Number of ticks simulated +final_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112468 # Simulator instruction rate (inst/s) -host_op_rate 1253563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1586896277 # Simulator tick rate (ticks/s) -host_mem_usage 231144 # Number of bytes of host memory used -host_seconds 453.93 # Real time elapsed on the host +host_inst_rate 1074460 # Simulator instruction rate (inst/s) +host_op_rate 1210735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1527332222 # Simulator tick rate (ticks/s) +host_mem_usage 237040 # Number of bytes of host memory used +host_seconds 469.99 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 150998 # Nu system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13663213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9127171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9127171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9127171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 22790384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1440691828 # number of cpu cycles simulated +system.cpu.numCycles 1435665752 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 182890034 # nu system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1440691828 # Number of busy cycles +system.cpu.num_busy_cycles 1435665752 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 983.378720 # Cycle average of tags in use +system.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 983.378720 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.480165 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.480165 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 279753000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 279753000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 279753000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 279753000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 279753000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 279753000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24282.006770 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24282.006770 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24282.006770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24282.006770 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 245190000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 245190000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 245190000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 245190000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 245190000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 245190000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21282.006770 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21282.006770 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.381389 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11899663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.381389 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992525 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992525 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13181704000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13181704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327564000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9327564000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22509268000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22509268000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22509268000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22509268000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16842.227384 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16842.227384 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26181.900859 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26181.900859 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19763.730137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19763.730137 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10833730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10833730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8258784000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8258784000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19092514000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19092514000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19092514000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19092514000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10613061000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10613061000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870566000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18870566000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870566000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18870566000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13842.227384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13842.227384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23181.900859 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23181.900859 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13560.279202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13560.279202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.310784 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.310784 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 122482 # number of replacements -system.cpu.l2cache.tagsinuse 26939.836590 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26931.505779 # Cycle average of tags in use system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 344531371000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23226.765026 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 246.719769 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3466.351794 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.708825 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007529 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.105785 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.822139 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 343812481000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 23220.335885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 246.652044 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3464.517849 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.708628 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007527 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.105729 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.821884 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 153785 # nu system.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses system.cpu.l2cache.overall_misses::total 153785 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144924000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480244000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2625168000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371652000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5371652000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7851896000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7996820000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7851896000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7996820000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144931000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480793000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2625724000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371655000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371655000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144931000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7852448000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7997379000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144931000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7852448000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7997379000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.133675 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.511661 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52011.510158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.013390 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.029041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.029041 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52003.634945 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52003.634945 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 153785 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1907880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019360000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6039920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6151400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6039920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6151400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111487000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1908429000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019916000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132043000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132043000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111487000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6040472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6151959000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111487000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6040472000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6151959000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.511661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40011.510158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.013390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.029041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.029041 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 6f010c94a..eb9886f3f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,278 +1,278 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.433409 # Number of seconds simulated -sim_ticks 433408519000 # Number of ticks simulated -final_tick 433408519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.427481 # Number of seconds simulated +sim_ticks 427481057500 # Number of ticks simulated +final_tick 427481057500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113614 # Simulator instruction rate (inst/s) -host_op_rate 210085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59550946 # Simulator tick rate (ticks/s) -host_mem_usage 266596 # Number of bytes of host memory used -host_seconds 7277.95 # Real time elapsed on the host +host_inst_rate 54913 # Simulator instruction rate (inst/s) +host_op_rate 101540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28388930 # Simulator tick rate (ticks/s) +host_mem_usage 267916 # Number of bytes of host memory used +host_seconds 15058.02 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 223616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27616960 # Number of bytes read from this memory -system.physmem.bytes_read::total 27840576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20804096 # Number of bytes written to this memory -system.physmem.bytes_written::total 20804096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431515 # Number of read requests responded to by this memory -system.physmem.num_reads::total 435009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 325064 # Number of write requests responded to by this memory -system.physmem.num_writes::total 325064 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 515947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 63720390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64236338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 515947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 48001124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 48001124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 48001124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 515947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 63720390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 112237462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27608960 # Number of bytes read from this memory +system.physmem.bytes_read::total 27831040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20798528 # Number of bytes written to this memory +system.physmem.bytes_written::total 20798528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3470 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431390 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory +system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64585224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 48653683 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 48653683 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 48653683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64585224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 113758416 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 866817039 # number of cpu cycles simulated +system.cpu.numCycles 854962116 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221487081 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221487081 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14390308 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 156608955 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152775295 # Number of BTB hits +system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221542687 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14424166 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 156350035 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152734220 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187015787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1232613370 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221487081 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152775295 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 382812407 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92129156 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 211136743 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 290923 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 179403606 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4116177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 858776870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.664123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.408324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186980274 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1231567115 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221542687 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 200356871 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 480379655 55.94% 55.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25485451 2.97% 58.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28110483 3.27% 62.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29418527 3.43% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18947498 2.21% 67.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25073247 2.92% 70.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31697541 3.69% 74.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30731731 3.58% 78.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 188932737 22.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 469274174 55.37% 55.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18977949 2.24% 67.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25085896 2.96% 70.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31632952 3.73% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30710148 3.62% 77.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 188811034 22.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 858776870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.255518 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.421999 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 243893330 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 168016637 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 325049297 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44326191 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77491415 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2234477290 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 77491415 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 277619036 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38518487 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15798 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333479611 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 131652523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2182901177 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23899 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19427368 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 98042792 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159033013 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2233248714 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34110312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2180982884 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23384 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17625674 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 93760649 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 161 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282806171 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5519898710 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5519661560 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 237150 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 2280809501 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5515289668 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5515055744 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 233924 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 668765320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1577 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1532 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 321506074 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528464573 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210836617 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 202710665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58518610 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2088631495 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25170 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1835731702 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 979947 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 553767245 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 915534947 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24617 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 858776870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.137612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.891337 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 666768650 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1407 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1265 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 312542490 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 527887651 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210543369 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 206203596 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 60708248 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2086420498 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 33397 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1834774344 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 951947 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 847490251 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233191073 27.15% 27.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 144020170 16.77% 43.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 136609479 15.91% 59.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 135995630 15.84% 75.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 99689263 11.61% 87.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59771994 6.96% 94.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 35471375 4.13% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12162676 1.42% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1865210 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 226384740 26.71% 26.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103773872 12.24% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59584692 7.03% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35598450 4.20% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12150443 1.43% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1920111 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 858776870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 847490251 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5023267 32.65% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7736612 50.28% 82.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2627522 17.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9164809 54.44% 84.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2648245 15.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2697797 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1210853930 65.96% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444242795 24.20% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177937180 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2709053 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1209921951 65.94% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444260889 24.21% 90.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177882451 9.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1835731702 # Type of FU issued -system.cpu.iq.rate 2.117785 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15387401 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4546566873 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2642600298 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1793170888 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 40749 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78738 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 9468 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1848402423 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 18883 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170058795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1834774344 # Type of FU issued +system.cpu.iq.rate 2.146030 # Inst issue rate +system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4534784465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 77216 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9185 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1848880362 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 18181 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 169562147 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144362417 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 511205 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 267668 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61676904 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 143785495 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 532532 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 265743 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61383726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10972 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10593 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77491415 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5069554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 791692 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2088656665 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2509040 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528464573 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210837089 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 437341 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70182 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 267668 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10030872 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4891333 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14922205 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805797916 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 435944125 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29933786 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3929046 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 527887651 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210543911 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5247 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 306238 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13529 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 265743 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10035586 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4925818 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14961404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1804635725 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 435893328 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30138619 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608566280 # number of memory reference insts executed -system.cpu.iew.exec_branches 171216670 # Number of branches executed -system.cpu.iew.exec_stores 172622155 # Number of stores executed -system.cpu.iew.exec_rate 2.083252 # Inst execution rate -system.cpu.iew.wb_sent 1800513420 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1793180356 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362010404 # num instructions producing a value -system.cpu.iew.wb_consumers 1993207324 # num instructions consuming a value +system.cpu.iew.exec_refs 608398138 # number of memory reference insts executed +system.cpu.iew.exec_branches 171115964 # Number of branches executed +system.cpu.iew.exec_stores 172504810 # Number of stores executed +system.cpu.iew.exec_rate 2.110779 # Inst execution rate +system.cpu.iew.wb_sent 1799306282 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1791918855 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1361399176 # num instructions producing a value +system.cpu.iew.wb_consumers 1998222448 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.068695 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683326 # average fanout of values written-back +system.cpu.iew.wb_rate 2.095904 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.681305 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 559701427 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14419517 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 781285455 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.957017 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.446096 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770294264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 285259296 36.51% 36.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 196991997 25.21% 61.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62815706 8.04% 69.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 91733389 11.74% 81.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26919948 3.45% 84.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29020227 3.71% 88.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9830313 1.26% 89.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10314314 1.32% 91.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68400265 8.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276893916 35.95% 35.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27669896 3.59% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28983308 3.76% 88.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10477535 1.36% 89.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10390589 1.35% 91.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68515952 8.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 781285455 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770294264 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -283,69 +283,69 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68400265 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68515952 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2801575316 # The number of ROB reads -system.cpu.rob.rob_writes 4255093941 # The number of ROB writes -system.cpu.timesIdled 198389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8040169 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2788262369 # The number of ROB reads +system.cpu.rob.rob_writes 4250388650 # The number of ROB writes +system.cpu.timesIdled 191112 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7471865 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.048302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.048302 # CPI: Total CPI of All Threads -system.cpu.ipc 0.953923 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.953923 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3391505058 # number of integer regfile reads -system.cpu.int_regfile_writes 1872959305 # number of integer regfile writes -system.cpu.fp_regfile_reads 9467 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 993321385 # number of misc regfile reads -system.cpu.icache.replacements 5754 # number of replacements -system.cpu.icache.tagsinuse 1042.434990 # Cycle average of tags in use -system.cpu.icache.total_refs 179199016 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7367 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24324.557622 # Average number of references to valid blocks. +system.cpu.cpi 1.033965 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.033965 # CPI: Total CPI of All Threads +system.cpu.ipc 0.967151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.967151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3390266607 # number of integer regfile reads +system.cpu.int_regfile_writes 1871785238 # number of integer regfile writes +system.cpu.fp_regfile_reads 9183 # number of floating regfile reads +system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.misc_regfile_reads 992828832 # number of misc regfile reads +system.cpu.icache.replacements 5688 # number of replacements +system.cpu.icache.tagsinuse 1035.102627 # Cycle average of tags in use +system.cpu.icache.total_refs 179169407 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24553.845005 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1042.434990 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.509001 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.509001 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179215714 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179215714 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179215714 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179215714 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179215714 # number of overall hits -system.cpu.icache.overall_hits::total 179215714 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 187892 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 187892 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 187892 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 187892 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 187892 # number of overall misses -system.cpu.icache.overall_misses::total 187892 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1425771000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1425771000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1425771000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1425771000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1425771000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1425771000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179403606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179403606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179403606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179403606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179403606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179403606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001047 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001047 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001047 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001047 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001047 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001047 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7588.247504 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7588.247504 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7588.247504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7588.247504 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1035.102627 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505421 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505421 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179186003 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179186003 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179186003 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179186003 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179186003 # number of overall hits +system.cpu.icache.overall_hits::total 179186003 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 199745 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 199745 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 199745 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 199745 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 199745 # number of overall misses +system.cpu.icache.overall_misses::total 199745 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237682000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1237682000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1237682000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1237682000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1237682000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1237682000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179385748 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179385748 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179385748 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179385748 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179385748 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179385748 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001113 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001113 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001113 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001113 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001113 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001113 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.310296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6196.310296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6196.310296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6196.310296 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 186290 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 186290 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 186290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 789947000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 789947000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 789947000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 789947000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 789947000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 789947000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001038 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001038 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4240.415481 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4240.415481 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4240.415481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4240.415481 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.141332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.141332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529214 # number of replacements -system.cpu.dcache.tagsinuse 4087.821968 # Cycle average of tags in use -system.cpu.dcache.total_refs 410284602 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533310 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 161.955940 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1779749000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.821968 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998003 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998003 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 261560100 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 261560100 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148207018 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148207018 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 409767118 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 162.152895 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1774400000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.729607 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261990574 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261990574 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148196003 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148196003 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 410186577 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 410186577 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 410186577 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18607.522375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14378.659492 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14378.659492 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 413911722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 413911722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 413911722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 413911722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010428 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010428 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006464 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009000 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009000 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009000 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009000 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.054087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.054087 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.940033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.940033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.525841 # 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Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 441022 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 8.189918 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 209697302000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21100.579663 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 146.976593 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8058.630796 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.643939 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.245930 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.894354 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3776 # 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miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992512 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271152 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.271152 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.478885 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170313 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.171193 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.478885 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170313 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.171193 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35283.717579 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.546683 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34441.696046 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 56.948727 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 56.948727 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34236.014588 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34236.014588 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35283.717579 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34335.177855 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34342.746281 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35283.717579 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34335.177855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34342.746281 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,60 +596,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 325064 # number of writebacks -system.cpu.l2cache.writebacks::total 325064 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3494 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 225783 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 177436 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 177436 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209266 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 209266 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3494 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 431555 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 435049 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3494 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 431555 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 435049 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111572500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6940846499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7052418999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5502498500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5502498500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6489948500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6489948500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111572500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13430794999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13542367499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111572500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13430794999 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13542367499 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991855 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991855 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271084 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271084 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.171237 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.171237 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31932.598741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31224.426305 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31235.385299 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.173043 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.173043 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.914186 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.914186 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 324977 # number of writebacks +system.cpu.l2cache.writebacks::total 324977 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225672 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 189416 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 189416 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209218 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209218 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 431420 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 434890 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3470 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 431420 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 434890 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111424500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957189466 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068613966 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5872774499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5872774499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6488320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6488320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111424500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445509466 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13556933966 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111424500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445509466 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13556933966 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126143 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127588 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992512 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992512 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271152 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271152 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171193 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171193 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32110.806916 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.201825 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.512168 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31004.637934 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31004.637934 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.245600 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.245600 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 20a253054..3dab46390 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.652607 # Number of seconds simulated -sim_ticks 1652606827000 # Number of ticks simulated -final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.649901 # Number of seconds simulated +sim_ticks 1649900881000 # Number of ticks simulated +final_tick 1649900881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 548890 # Simulator instruction rate (inst/s) -host_op_rate 1014960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1097019218 # Simulator tick rate (ticks/s) -host_mem_usage 278012 # Number of bytes of host memory used -host_seconds 1506.45 # Real time elapsed on the host +host_inst_rate 669860 # Simulator instruction rate (inst/s) +host_op_rate 1238647 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1336598464 # Simulator tick rate (ticks/s) +host_mem_usage 232964 # Number of bytes of host memory used +host_seconds 1234.40 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 427498 # Nu system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 74904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16582737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16657641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 74904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12551348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12551348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12551348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 74904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16582737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29208989 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3305213654 # number of cpu cycles simulated +system.cpu.numCycles 3299801762 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262341 # nu system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3305213654 # Number of busy cycles +system.cpu.num_busy_cycles 3299801762 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use +system.cpu.icache.tagsinuse 881.283724 # Cycle average of tags in use system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 881.283724 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.430314 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.430314 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 117690500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 117690500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 117690500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 117690500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 117690500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 117690500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42925.373134 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42925.373134 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41823.205402 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41823.205402 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41823.205402 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41823.205402 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 112350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 112350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112350000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 112350000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112062500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 112062500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112062500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 112062500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112062500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 112062500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39823.205402 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39823.205402 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.427569 # Cycle average of tags in use system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.427569 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997663 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997663 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31594062000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31594062000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100972000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19100972000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 50695034000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 50695034000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 50695034000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 50695034000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19314.579481 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19314.579481 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25147.278154 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25147.278154 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21146.621663 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21146.621663 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18289.803139 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18289.803139 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24146.535465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24146.535465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20129.394256 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20129.394256 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28182031000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28182031000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17519463000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17519463000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45701494000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45701494000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45701494000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45701494000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518884000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518884000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45658118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45658118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45658118000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45658118000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16314.578323 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16314.578323 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.803139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.803139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.535465 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.535465 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 403150 # number of replacements -system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29110.547277 # Cycle average of tags in use system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 772497646000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21034.967888 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 79.712550 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7995.866840 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641936 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.244014 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.888383 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits @@ -272,17 +272,17 @@ system.cpu.l2cache.demand_misses::total 429429 # nu system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses system.cpu.l2cache.overall_misses::total 429429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100412000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313120000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11413532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916779000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10916779000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 100412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22229899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22330311000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 100412000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22229899000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22330311000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100418500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313280000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11413698500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916780000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10916780000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 100418500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22230060000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22330478500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 100418500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22230060000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22330478500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) @@ -307,17 +307,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.170322 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.014290 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.014290 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.006986 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.006986 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.366132 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.735429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.758573 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.019053 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.019053 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.397039 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.397039 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -339,17 +339,17 @@ system.cpu.l2cache.demand_mshr_misses::total 429429 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77246000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702551000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779797000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17099920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17177160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17099920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17177160000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77246000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17100071000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17177317000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77246000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17100071000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17177317000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses @@ -361,17 +361,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.107198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.694061 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.715291 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index c000798eb..63bbc9ea5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141187 # Number of seconds simulated -sim_ticks 141187061500 # Number of ticks simulated -final_tick 141187061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141181 # Number of seconds simulated +sim_ticks 141180939500 # Number of ticks simulated +final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158597 # Simulator instruction rate (inst/s) -host_op_rate 158597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56167220 # Simulator tick rate (ticks/s) -host_mem_usage 225028 # Number of bytes of host memory used -host_seconds 2513.69 # Real time elapsed on the host +host_inst_rate 88431 # Simulator instruction rate (inst/s) +host_op_rate 88431 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31316360 # Simulator tick rate (ticks/s) +host_mem_usage 225476 # Number of bytes of host memory used +host_seconds 4508.22 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214592 # Nu system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1519913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1799145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3319058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1519913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1519913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1519913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1799145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3319058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -35,18 +35,18 @@ system.cpu.dtb.read_hits 94755019 # DT system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 94755040 # DTB read accesses -system.cpu.dtb.write_hits 73522100 # DTB write hits +system.cpu.dtb.write_hits 73522102 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73522135 # DTB write accesses -system.cpu.dtb.data_hits 168277119 # DTB hits +system.cpu.dtb.write_accesses 73522137 # DTB write accesses +system.cpu.dtb.data_hits 168277121 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168277175 # DTB accesses -system.cpu.itb.fetch_hits 49112134 # ITB hits -system.cpu.itb.fetch_misses 88783 # ITB misses +system.cpu.dtb.data_accesses 168277177 # DTB accesses +system.cpu.itb.fetch_hits 49111833 # ITB hits +system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49200917 # ITB accesses +system.cpu.itb.fetch_accesses 49200615 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282374124 # number of cpu cycles simulated +system.cpu.numCycles 282361880 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53870034 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30921446 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16037248 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33426490 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15653868 # Number of BTB hits +system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.830726 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29683710 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24186324 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280818505 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440154364 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119907678 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220104159 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100457715 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168700471 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14475138 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1561451 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16036589 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28550962 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.966517 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205751085 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124334 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168700458 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281932231 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 9236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13499283 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268874841 # Number of cycles cpu stages are processed. -system.cpu.activity 95.219363 # Percentage of cycles cpu is active +system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed. +system.cpu.activity 95.223370 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,72 +107,72 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708300 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708300 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411831 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411831 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78560366 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203813758 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.178624 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108887705 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173486419 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.438497 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104664774 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177709350 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.934007 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183592728 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98781396 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.982453 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92681683 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189692441 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.177700 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1973 # number of replacements -system.cpu.icache.tagsinuse 1829.856986 # Cycle average of tags in use -system.cpu.icache.total_refs 49107743 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3900 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12591.728974 # Average number of references to valid blocks. +system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1974 # number of replacements +system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use +system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.856986 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893485 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893485 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49107743 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49107743 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49107743 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49107743 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49107743 # number of overall hits -system.cpu.icache.overall_hits::total 49107743 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4390 # number of overall misses -system.cpu.icache.overall_misses::total 4390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220305000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220305000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220305000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220305000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220305000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220305000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49112133 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49112133 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49112133 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49112133 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49112133 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49112133 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits +system.cpu.icache.overall_hits::total 49107443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses +system.cpu.icache.overall_misses::total 4389 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50183.371298 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50183.371298 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50183.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50183.371298 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49040.669856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49040.669856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49040.669856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3900 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3900 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3900 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3900 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3900 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3900 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190927000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 190927000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190927000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 190927000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190927000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 190927000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 190519000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190519000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 190519000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190519000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 190519000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48955.641026 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48955.641026 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.502948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48838.502948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.708505 # Cycle average of tags in use -system.cpu.dcache.total_refs 168261813 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3284.744401 # Cycle average of tags in use +system.cpu.dcache.total_refs 168261808 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40525.484827 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40525.483622 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.708505 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.801931 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.801931 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3284.744401 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801940 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801940 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73508552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73508552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168261813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168261813 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168261813 # number of overall hits -system.cpu.dcache.overall_hits::total 168261813 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261808 # number of overall hits +system.cpu.dcache.overall_hits::total 168261808 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 12177 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 12177 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 13405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 13405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13405 # number of overall misses -system.cpu.dcache.overall_misses::total 13405 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68612500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68612500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 712613500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 712613500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 781226000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 781226000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 781226000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 781226000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 12182 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12182 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13410 # number of overall misses +system.cpu.dcache.overall_misses::total 13410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65498000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65498000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 641953000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 641953000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 707451000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 707451000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 707451000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 707451000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -261,32 +261,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55873.371336 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55873.371336 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58521.269607 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58521.269607 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58278.701977 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58278.701977 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53337.133550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53337.133550 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52696.847808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52696.847808 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 86009500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85964000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1905 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45149.343832 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45078.133193 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8975 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8975 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9253 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9253 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9253 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9253 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8980 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8980 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9258 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9258 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9258 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9258 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48743500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48743500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 176149500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 176149500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224893000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 224893000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224893000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 224893000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 175965000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 175965000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224460500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224460500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51308.947368 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51308.947368 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55012.336040 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55012.336040 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51047.894737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51047.894737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54954.715803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54954.715803 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3900.249221 # Cycle average of tags in use -system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3900.293758 # Cycle average of tags in use +system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.159839 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.495467 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.223601 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.530153 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.502388 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.254610 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.536760 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088570 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119026 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 547 # number of ReadReq hits +system.cpu.l2cache.occ_percent::total 0.119028 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 670 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 547 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 730 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 547 # number of overall hits +system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits -system.cpu.l2cache.overall_hits::total 730 # number of overall hits +system.cpu.l2cache.overall_hits::total 731 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses @@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 7322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180755000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45853500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 226608500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 171775500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 171775500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 180755000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 217629000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 398384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 180755000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 217629000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 398384000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3900 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 181079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 181079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 218267500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 399347000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4847 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3900 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8052 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3900 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8052 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859744 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.861770 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859744 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.909339 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859744 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.909339 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53908.440203 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55647.451456 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54251.496289 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54618.600954 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54618.600954 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54409.177820 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54409.177820 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54540.699262 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 7322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139951500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35886500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175838000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139951500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169310500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 309262000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139951500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169310500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 309262000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 140250000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176303500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133849000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140250000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 310152500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 310152500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.909339 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.909339 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41739.188786 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43551.577670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42096.720134 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42424.165342 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42424.165342 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 33f2699f3..9ec4bfca0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080362 # Number of seconds simulated -sim_ticks 80362284000 # Number of ticks simulated -final_tick 80362284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080354 # Number of seconds simulated +sim_ticks 80354154000 # Number of ticks simulated +final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 277812 # Simulator instruction rate (inst/s) -host_op_rate 277812 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59443930 # Simulator tick rate (ticks/s) -host_mem_usage 226052 # Number of bytes of host memory used -host_seconds 1351.90 # Real time elapsed on the host +host_inst_rate 172564 # Simulator instruction rate (inst/s) +host_op_rate 172564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36920064 # Simulator tick rate (ticks/s) +host_mem_usage 226504 # Number of bytes of host memory used +host_seconds 2176.44 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 477824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3477 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7466 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2769060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3176814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5945874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2769060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2769060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2769060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3176814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5945874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory +system.physmem.bytes_read::total 478400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7475 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2774916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3178728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5953644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2774916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2774916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2774916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3178728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5953644 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103417276 # DTB read hits -system.cpu.dtb.read_misses 89602 # DTB read misses +system.cpu.dtb.read_hits 103401614 # DTB read hits +system.cpu.dtb.read_misses 88552 # DTB read misses system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103506878 # DTB read accesses -system.cpu.dtb.write_hits 79004376 # DTB write hits -system.cpu.dtb.write_misses 1630 # DTB write misses +system.cpu.dtb.read_accesses 103490166 # DTB read accesses +system.cpu.dtb.write_hits 79056152 # DTB write hits +system.cpu.dtb.write_misses 1601 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79006006 # DTB write accesses -system.cpu.dtb.data_hits 182421652 # DTB hits -system.cpu.dtb.data_misses 91232 # DTB misses +system.cpu.dtb.write_accesses 79057753 # DTB write accesses +system.cpu.dtb.data_hits 182457766 # DTB hits +system.cpu.dtb.data_misses 90153 # DTB misses system.cpu.dtb.data_acv 48605 # DTB access violations -system.cpu.dtb.data_accesses 182512884 # DTB accesses -system.cpu.itb.fetch_hits 52579177 # ITB hits -system.cpu.itb.fetch_misses 445 # ITB misses +system.cpu.dtb.data_accesses 182547919 # DTB accesses +system.cpu.itb.fetch_hits 52578444 # ITB hits +system.cpu.itb.fetch_misses 446 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52579622 # ITB accesses +system.cpu.itb.fetch_accesses 52578890 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160724570 # number of cpu cycles simulated +system.cpu.numCycles 160708310 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52097236 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30296765 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1606699 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28205553 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24320024 # Number of BTB hits +system.cpu.BPredUnit.lookups 52055858 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30270064 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1609565 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28583053 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24291253 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9390300 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1099 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53639869 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462587639 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52097236 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33710324 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81534889 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7793517 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19277229 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9332 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52579177 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 630275 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160609062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.880209 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314061 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9363483 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1125 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53630506 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462761975 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52055858 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33654736 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81569260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7805922 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19227823 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8640 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52578444 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 632985 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160593743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.881569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314206 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79074173 49.23% 49.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4377828 2.73% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7270092 4.53% 56.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5630004 3.51% 59.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12402470 7.72% 67.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8106533 5.05% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5708692 3.55% 76.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1929242 1.20% 77.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36110028 22.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79024483 49.21% 49.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4373999 2.72% 51.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7277585 4.53% 56.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5624285 3.50% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12451588 7.75% 67.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8090347 5.04% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5701462 3.55% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1906860 1.19% 77.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36143134 22.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160609062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324140 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.878139 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59173788 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14742505 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76724469 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3825000 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6143300 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9747252 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 160593743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323915 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.879515 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59159628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14701180 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76777373 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3802489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6153073 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9767212 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 4329 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457055568 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12267 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6143300 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62453650 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4799000 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 401905 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77381021 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9430186 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451385457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 27 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7813364 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295061939 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593486774 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314314250 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279172524 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 457201252 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12277 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6153073 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62463630 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4784250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 400809 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77384574 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9407407 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451419869 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20713 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7782416 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 295098377 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593658097 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314398187 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279259910 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35529610 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38241 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 341 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27266716 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107002651 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81768344 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8923759 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6384538 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416452671 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 325 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407888910 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1078553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40628099 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19685259 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160609062 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.539638 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.007756 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 35566048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38393 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27305396 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 107006158 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81864884 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8914753 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6402170 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416586090 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 336 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407940469 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1092011 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40751586 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19838559 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160593743 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.540202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.007855 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32138937 20.01% 20.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26538030 16.52% 36.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25997150 16.19% 52.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24815453 15.45% 68.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21510440 13.39% 81.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15487887 9.64% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8719479 5.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4101336 2.55% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1300350 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32107491 19.99% 19.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26532573 16.52% 36.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26024058 16.20% 52.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24782303 15.43% 68.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21577160 13.44% 81.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15465247 9.63% 91.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8675795 5.40% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4109702 2.56% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1319414 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160609062 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160593743 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35567 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35836 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 73106 0.62% 0.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5073 0.04% 0.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3115 0.03% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1847413 15.60% 16.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1780061 15.04% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5074453 42.86% 74.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3020406 25.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 73145 0.62% 0.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5467 0.05% 0.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3221 0.03% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1851348 15.57% 16.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1774625 14.92% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5106562 42.94% 74.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3040891 25.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158124852 38.77% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126520 0.52% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33455961 8.20% 47.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7846153 1.92% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2842255 0.70% 50.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16560349 4.06% 54.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1591354 0.39% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158120657 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126534 0.52% 39.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33463281 8.20% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7848056 1.92% 49.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2840409 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16567576 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1592675 0.39% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.57% # Type of FU issued @@ -221,84 +221,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.57% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105304781 25.82% 80.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80003104 19.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105294166 25.81% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80053534 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407888910 # Type of FU issued -system.cpu.iq.rate 2.537813 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11839194 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029026 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648060515 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 269929713 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237794597 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341244114 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187202465 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162943481 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245434368 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174260155 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14844596 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407940469 # Type of FU issued +system.cpu.iq.rate 2.538391 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11891095 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029149 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 648130283 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 270005016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237809508 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341327504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187383841 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162964934 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245490516 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174307467 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14797790 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12248164 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 129765 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 51115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8247615 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12251671 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123751 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50882 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8344155 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260830 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 260839 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6143300 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2503230 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370145 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441398780 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177151 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107002651 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81768344 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 325 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 68 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 51115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1257944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570703 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1828647 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403351252 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103555560 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4537658 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6153073 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2493888 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367103 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441513906 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 235069 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 107006158 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81864884 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 336 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 120 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50882 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1249323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 568752 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1818075 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403380721 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103538845 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4559748 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24945784 # number of nop insts executed -system.cpu.iew.exec_refs 182561595 # number of memory reference insts executed -system.cpu.iew.exec_branches 47229945 # Number of branches executed -system.cpu.iew.exec_stores 79006035 # Number of stores executed -system.cpu.iew.exec_rate 2.509581 # Inst execution rate -system.cpu.iew.wb_sent 401565360 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400738078 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195225884 # num instructions producing a value -system.cpu.iew.wb_consumers 273294717 # num instructions consuming a value +system.cpu.iew.exec_nop 24927480 # number of nop insts executed +system.cpu.iew.exec_refs 182596628 # number of memory reference insts executed +system.cpu.iew.exec_branches 47226669 # Number of branches executed +system.cpu.iew.exec_stores 79057783 # Number of stores executed +system.cpu.iew.exec_rate 2.510018 # Inst execution rate +system.cpu.iew.wb_sent 401610425 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400774442 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195308199 # num instructions producing a value +system.cpu.iew.wb_consumers 273451305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.493322 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714342 # average fanout of values written-back +system.cpu.iew.wb_rate 2.493800 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714234 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42764408 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42890401 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1602444 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154465762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.580925 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.966951 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1605306 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154440670 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.581345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965853 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58951255 38.16% 38.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23354970 15.12% 53.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13285334 8.60% 61.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11679330 7.56% 69.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8439151 5.46% 74.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5483127 3.55% 78.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5136953 3.33% 81.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3378138 2.19% 83.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24757504 16.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58870445 38.12% 38.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23396206 15.15% 53.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13280012 8.60% 61.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11680215 7.56% 69.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8466998 5.48% 74.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5501467 3.56% 78.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5150112 3.33% 81.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3370011 2.18% 83.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24725204 16.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154465762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154440670 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +309,70 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24757504 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24725204 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571134272 # The number of ROB reads -system.cpu.rob.rob_writes 889015019 # The number of ROB writes -system.cpu.timesIdled 3240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 115508 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571267473 # The number of ROB reads +system.cpu.rob.rob_writes 889277309 # The number of ROB writes +system.cpu.timesIdled 3039 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 114567 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.427943 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.427943 # CPI: Total CPI of All Threads -system.cpu.ipc 2.336760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.336760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402895481 # number of integer regfile reads -system.cpu.int_regfile_writes 172638002 # number of integer regfile writes -system.cpu.fp_regfile_reads 158340215 # number of floating regfile reads -system.cpu.fp_regfile_writes 105188641 # number of floating regfile writes +system.cpu.cpi 0.427900 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427900 # CPI: Total CPI of All Threads +system.cpu.ipc 2.336997 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.336997 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402957504 # number of integer regfile reads +system.cpu.int_regfile_writes 172619998 # number of integer regfile writes +system.cpu.fp_regfile_reads 158343155 # number of floating regfile reads +system.cpu.fp_regfile_writes 105226626 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2209 # number of replacements -system.cpu.icache.tagsinuse 1834.486163 # Cycle average of tags in use -system.cpu.icache.total_refs 52573796 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4140 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12698.984541 # Average number of references to valid blocks. +system.cpu.icache.replacements 2218 # number of replacements +system.cpu.icache.tagsinuse 1836.523631 # Cycle average of tags in use +system.cpu.icache.total_refs 52573018 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4149 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12671.250422 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.486163 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895745 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895745 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52573796 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52573796 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52573796 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52573796 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52573796 # number of overall hits -system.cpu.icache.overall_hits::total 52573796 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5381 # number of overall misses -system.cpu.icache.overall_misses::total 5381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 173584500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 173584500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 173584500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 173584500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 173584500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 173584500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52579177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52579177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52579177 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52579177 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52579177 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52579177 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000102 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000102 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000102 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32258.780896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 32258.780896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 32258.780896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 32258.780896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 32258.780896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 32258.780896 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1836.523631 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.896740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.896740 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52573018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52573018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52573018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52573018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52573018 # number of overall hits +system.cpu.icache.overall_hits::total 52573018 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5426 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5426 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5426 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5426 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5426 # number of overall misses +system.cpu.icache.overall_misses::total 5426 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 168571000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 168571000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 168571000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 168571000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 168571000 # 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miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31067.268706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31067.268706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31067.268706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31067.268706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,98 +381,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 129086500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 129086500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 129086500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31481.521739 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31112.677754 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 796 # number of replacements -system.cpu.dcache.tagsinuse 3296.720309 # Cycle average of tags in use -system.cpu.dcache.total_refs 161811337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4197 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38554.047415 # Average number of references to valid blocks. +system.cpu.dcache.replacements 788 # number of replacements +system.cpu.dcache.tagsinuse 3297.853996 # Cycle average of tags in use +system.cpu.dcache.total_refs 161841661 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38625.694749 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3296.720309 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804863 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804863 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88310042 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88310042 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501280 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501280 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161811322 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161811322 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161811322 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161863693 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161863693 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161863693 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161863693 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000131 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000131 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38257.821229 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38257.821229 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37607.229163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37607.229163 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37662.060361 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37662.060361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37662.060361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37662.060361 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000275 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000275 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34581.853496 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34581.853496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30887.766693 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30887.766693 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -481,32 +481,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 7500 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 676 # number of writebacks -system.cpu.dcache.writebacks::total 676 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 798 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 798 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16244 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38052.307692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.466131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40136.807818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38052.307692 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7466 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112721000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31878000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 144599000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115138500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115138500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112721000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147016500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 259737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112721000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147016500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 259737500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.839855 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.864919 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.844700 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976911 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.976911 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.839855 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950441 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.895526 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.839855 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950441 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.895526 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32419.039402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37153.846154 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33356.170704 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36773.714468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36773.714468 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32419.039402 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36855.477563 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34789.378516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32419.039402 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36855.477563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34789.378516 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3484 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 859 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4343 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3991 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3484 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3991 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7475 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112975000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31822500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 144797500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115935000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115935000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112975000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147757500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 260732500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112975000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147757500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 260732500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868554 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.845271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978444 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978444 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.896390 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.896390 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32426.808266 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37045.983702 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33340.432880 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37016.283525 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37016.283525 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index df4992494..10dc822fe 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567366 # Number of seconds simulated -sim_ticks 567365869000 # Number of ticks simulated -final_tick 567365869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567335 # Number of seconds simulated +sim_ticks 567335093000 # Number of ticks simulated +final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2066411 # Simulator instruction rate (inst/s) -host_op_rate 2066411 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2940844836 # Simulator tick rate (ticks/s) -host_mem_usage 224004 # Number of bytes of host memory used -host_seconds 192.93 # Real time elapsed on the host +host_inst_rate 1259990 # Simulator instruction rate (inst/s) +host_op_rate 1259990 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1793077476 # Simulator tick rate (ticks/s) +host_mem_usage 225476 # Number of bytes of host memory used +host_seconds 316.40 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 361550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134731738 # number of cpu cycles simulated +system.cpu.numCycles 1134670186 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134731738 # Number of busy cycles +system.cpu.num_busy_cycles 1134670186 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.107538 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.138964 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.107538 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.876517 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.876517 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186108000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186108000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186108000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186108000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186108000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186108000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50669.207732 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50669.207732 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50669.207732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50669.207732 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175089000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175089000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175089000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175089000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175089000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175089000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47669.207732 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47669.207732 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.859436 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.859436 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802944 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802944 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48094000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48094000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 176797000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 176797000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 224891000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 224891000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 224891000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 224891000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50625.263158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50625.263158 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55214.553404 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55214.553404 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54164.499037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54164.499037 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212435000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212435000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212435000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212435000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47625.263158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47625.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52214.553404 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52214.553404 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3772.396394 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.526936 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.408528 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.460931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084546 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115124 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115127 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 57c2e3ca3..8292ba84e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070907 # Number of seconds simulated -sim_ticks 70907303500 # Number of ticks simulated -final_tick 70907303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.070882 # Number of seconds simulated +sim_ticks 70882487500 # Number of ticks simulated +final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128530 # Simulator instruction rate (inst/s) -host_op_rate 164318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33377575 # Simulator tick rate (ticks/s) -host_mem_usage 237852 # Number of bytes of host memory used -host_seconds 2124.40 # Real time elapsed on the host -sim_insts 273048456 # Number of instructions simulated -sim_ops 349076180 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 467136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7299 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2745669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3842312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6587981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2745669 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2745669 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2745669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3842312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6587981 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 119635 # Simulator instruction rate (inst/s) +host_op_rate 152946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31056895 # Simulator tick rate (ticks/s) +host_mem_usage 243232 # Number of bytes of host memory used +host_seconds 2282.34 # Real time elapsed on the host +sim_insts 273048441 # Number of instructions simulated +sim_ops 349076165 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272768 # Number of bytes read from this memory +system.physmem.bytes_read::total 467648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2749339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3848172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6597511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2749339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2749339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2749339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3848172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6597511 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +70,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 141814608 # number of cpu cycles simulated +system.cpu.numCycles 141764976 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43021564 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21750711 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2101631 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27856122 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17838153 # Number of BTB hits +system.cpu.BPredUnit.lookups 43022632 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21746290 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2100537 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27784307 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17845610 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6966793 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7520 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40921334 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 328638556 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43021564 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24804946 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73672457 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8389816 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20828697 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3338 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39391876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 684935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 141703595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.981779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454940 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6965581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7462 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40878725 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 328721134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 43022632 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24811191 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 73667201 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8391169 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20823021 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3522 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39401519 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 692730 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 141652682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.982295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454701 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68712087 48.49% 48.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7380491 5.21% 53.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5816522 4.10% 57.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6226633 4.39% 62.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4949598 3.49% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4317646 3.05% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3315601 2.34% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4325062 3.05% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36659955 25.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68666188 48.48% 48.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7372946 5.20% 53.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5824782 4.11% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6228810 4.40% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4953654 3.50% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4319066 3.05% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3319868 2.34% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4326916 3.05% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36640452 25.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 141703595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303365 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.317382 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47754995 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16062481 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69284862 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2393411 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6207846 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7495010 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414601239 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 219868 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6207846 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53518393 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1558450 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65839797 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14237834 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 404012192 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667987 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10221278 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1168 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443337202 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2387138833 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1300349332 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086789501 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 58752232 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14504 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14503 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35673328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105504454 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93209227 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4624259 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5728531 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 391940261 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25587 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 377964584 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1402397 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 41905319 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 110211682 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1107 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 141703595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.667290 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.042913 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 141652682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.303479 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.318775 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47724056 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16047440 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69280897 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2389978 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6210311 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7496443 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70615 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 414536105 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 220570 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6210311 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53491207 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1558118 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 338571 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 65828585 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14225890 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 403967880 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1665803 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10197275 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 723 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 443295910 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2386846444 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1300310044 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1086536400 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 58710964 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14469 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14467 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35655672 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105463248 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93220202 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4594940 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5698907 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 391915159 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25548 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378021086 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1395950 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 41892562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 109796784 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 141652682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.668648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.042717 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28741246 20.28% 20.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20522205 14.48% 34.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20900588 14.75% 49.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18202387 12.85% 62.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24092550 17.00% 79.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15957128 11.26% 90.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9055746 6.39% 97.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3310234 2.34% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 921511 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28697410 20.26% 20.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20492119 14.47% 34.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20907256 14.76% 49.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18207035 12.85% 62.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24094157 17.01% 79.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15966233 11.27% 90.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9051361 6.39% 97.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3319497 2.34% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 917614 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 141703595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 141652682 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9264 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4697 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8869 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,22 +189,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45902 0.26% 0.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45720 0.25% 0.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7808 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 380 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7848 0.04% 0.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 429 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193577 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 5090 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240664 1.34% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 193652 1.08% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4980 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 240582 1.34% 2.82% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9480378 52.69% 55.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8006063 44.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9467921 52.63% 55.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8015707 44.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128177934 33.91% 33.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174662 0.58% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128195849 33.91% 33.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174611 0.58% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.49% # Type of FU issued @@ -223,167 +223,167 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.49% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6842006 1.81% 36.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6839706 1.81% 36.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692020 2.30% 38.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3461453 0.92% 39.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1621602 0.43% 39.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21340607 5.65% 45.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172753 1.90% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136617 1.89% 49.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102440165 27.10% 76.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88729478 23.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8692181 2.30% 38.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3465000 0.92% 39.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1622054 0.43% 39.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21343322 5.65% 45.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172329 1.90% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135364 1.89% 49.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102447083 27.10% 76.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88758301 23.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 377964584 # Type of FU issued -system.cpu.iq.rate 2.665202 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17993826 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047607 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 665793984 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301139104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252255785 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251235002 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132745901 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118864658 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266433376 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129525034 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10838927 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378021086 # Type of FU issued +system.cpu.iq.rate 2.666534 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17990410 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 665853263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 301144367 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252283124 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 251227951 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132702727 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118872712 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266490153 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129521343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10844694 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10853359 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121041 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10831289 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10812156 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14360 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10842267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20682 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 118 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29815 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 119 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6207846 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 63522 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8302 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 391975437 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1065471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105504454 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93209227 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14418 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 255 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 232 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1674842 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 501476 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2176318 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373329400 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101074307 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4635184 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6210311 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7651 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 391949728 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1062817 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105463248 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93220202 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14378 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 211 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 349 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14360 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1675475 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 499111 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2174586 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373364048 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101084784 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4657038 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9589 # number of nop insts executed -system.cpu.iew.exec_refs 188479981 # number of memory reference insts executed -system.cpu.iew.exec_branches 38700000 # Number of branches executed -system.cpu.iew.exec_stores 87405674 # Number of stores executed -system.cpu.iew.exec_rate 2.632517 # Inst execution rate -system.cpu.iew.wb_sent 371919298 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371120443 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184768812 # num instructions producing a value -system.cpu.iew.wb_consumers 367722333 # num instructions consuming a value +system.cpu.iew.exec_nop 9021 # number of nop insts executed +system.cpu.iew.exec_refs 188503459 # number of memory reference insts executed +system.cpu.iew.exec_branches 38700482 # Number of branches executed +system.cpu.iew.exec_stores 87418675 # Number of stores executed +system.cpu.iew.exec_rate 2.633683 # Inst execution rate +system.cpu.iew.wb_sent 371949572 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371155836 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184798274 # num instructions producing a value +system.cpu.iew.wb_consumers 367725403 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.616941 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502468 # average fanout of values written-back +system.cpu.iew.wb_rate 2.618107 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502544 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42898696 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24480 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2031740 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135495750 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.576293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.655015 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 42873018 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2030662 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135442372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.577309 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.655328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38151746 28.16% 28.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29172803 21.53% 49.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13488501 9.95% 59.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11127648 8.21% 67.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13794811 10.18% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7272808 5.37% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3959931 2.92% 86.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3978843 2.94% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14548659 10.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38119190 28.14% 28.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29150867 21.52% 49.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13483643 9.96% 59.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11130935 8.22% 67.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13797972 10.19% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7276796 5.37% 83.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3948237 2.92% 86.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3977327 2.94% 89.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14557405 10.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135495750 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049068 # Number of instructions committed -system.cpu.commit.committedOps 349076792 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 135442372 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049053 # Number of instructions committed +system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029033 # Number of memory references committed -system.cpu.commit.loads 94651095 # Number of loads committed +system.cpu.commit.refs 177029027 # Number of memory references committed +system.cpu.commit.loads 94651092 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549058 # Number of branches committed +system.cpu.commit.branches 36549055 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279593995 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593983 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14548659 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14557405 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 512920056 # The number of ROB reads -system.cpu.rob.rob_writes 790163258 # The number of ROB writes -system.cpu.timesIdled 3290 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 111013 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048456 # Number of Instructions Simulated -system.cpu.committedOps 349076180 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048456 # Number of Instructions Simulated -system.cpu.cpi 0.519375 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.519375 # CPI: Total CPI of All Threads -system.cpu.ipc 1.925390 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.925390 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783222925 # number of integer regfile reads -system.cpu.int_regfile_writes 236048544 # number of integer regfile writes -system.cpu.fp_regfile_reads 189858898 # number of floating regfile reads -system.cpu.fp_regfile_writes 133648833 # number of floating regfile writes -system.cpu.misc_regfile_reads 990710631 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426475 # number of misc regfile writes -system.cpu.icache.replacements 13954 # number of replacements -system.cpu.icache.tagsinuse 1852.950065 # Cycle average of tags in use -system.cpu.icache.total_refs 39375254 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15846 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2484.870251 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 512832239 # The number of ROB reads +system.cpu.rob.rob_writes 790114412 # The number of ROB writes +system.cpu.timesIdled 3064 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 112294 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048441 # Number of Instructions Simulated +system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated +system.cpu.cpi 0.519194 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.519194 # CPI: Total CPI of All Threads +system.cpu.ipc 1.926064 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.926064 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1783379175 # number of integer regfile reads +system.cpu.int_regfile_writes 236079321 # number of integer regfile writes +system.cpu.fp_regfile_reads 189868959 # number of floating regfile reads +system.cpu.fp_regfile_writes 133650660 # number of floating regfile writes +system.cpu.misc_regfile_reads 990849298 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes +system.cpu.icache.replacements 13928 # number of replacements +system.cpu.icache.tagsinuse 1856.985526 # Cycle average of tags in use +system.cpu.icache.total_refs 39384906 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15824 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2488.934909 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1852.950065 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.904761 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.904761 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39375254 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39375254 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39375254 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39375254 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39375254 # number of overall hits -system.cpu.icache.overall_hits::total 39375254 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16622 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16622 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16622 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16622 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16622 # number of overall misses -system.cpu.icache.overall_misses::total 16622 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 210340000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 210340000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 210340000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 210340000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 210340000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 210340000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39391876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39391876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39391876 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39391876 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39391876 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39391876 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1856.985526 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906731 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39384906 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39384906 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39384906 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39384906 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39384906 # number of overall hits +system.cpu.icache.overall_hits::total 39384906 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16613 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16613 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16613 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16613 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16613 # number of overall misses +system.cpu.icache.overall_misses::total 16613 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188398500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188398500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188398500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188398500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188398500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188398500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39401519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39401519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39401519 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39401519 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39401519 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39401519 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000422 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000422 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000422 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000422 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000422 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000422 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12654.313560 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12654.313560 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12654.313560 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12654.313560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12654.313560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12654.313560 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11340.426172 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11340.426172 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11340.426172 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11340.426172 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,146 +392,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 775 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 775 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 775 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 775 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 775 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 775 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15847 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15847 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15847 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15847 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15847 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15847 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 138958000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 138958000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 138958000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 138958000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 138958000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 138958000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 789 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 789 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 789 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 789 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 789 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15824 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15824 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15824 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15824 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15824 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15824 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 136475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 136475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 136475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 136475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 136475000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 136475000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000402 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000402 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000402 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8768.725942 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8768.725942 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8768.725942 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8768.725942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8768.725942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8768.725942 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8624.557634 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8624.557634 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1429 # number of replacements -system.cpu.dcache.tagsinuse 3114.485618 # Cycle average of tags in use -system.cpu.dcache.total_refs 172071632 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4623 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37220.772658 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1417 # number of replacements +system.cpu.dcache.tagsinuse 3115.188705 # Cycle average of tags in use +system.cpu.dcache.total_refs 172067508 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4618 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37260.179298 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3114.485618 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.760372 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.760372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90013475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90013475 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031354 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031354 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13548 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13548 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13255 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13255 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172044829 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172044829 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172044829 # number of overall hits -system.cpu.dcache.overall_hits::total 172044829 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3882 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3882 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21306 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21306 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3115.188705 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.760544 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.760544 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90009194 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90009194 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031517 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031517 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13545 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13252 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13252 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172040711 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172040711 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172040711 # number of overall hits +system.cpu.dcache.overall_hits::total 172040711 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3936 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3936 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21143 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21143 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25188 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25188 # number of overall misses -system.cpu.dcache.overall_misses::total 25188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 139835000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 139835000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 825940000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 825940000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 965775000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 965775000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 965775000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 965775000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90017357 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90017357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25079 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25079 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25079 # number of overall misses +system.cpu.dcache.overall_misses::total 25079 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 123444000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 123444000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 700240500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 700240500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 74000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 74000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 823684500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 823684500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 823684500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 823684500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90013130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90013130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13550 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13550 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13255 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13255 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172070017 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172070017 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172070017 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172070017 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000260 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000260 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13547 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13547 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172065790 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172065790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172065790 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172065790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36021.380732 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36021.380732 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38765.605933 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38765.605933 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38342.663173 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38342.663173 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38342.663173 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38342.663173 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31362.804878 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31362.804878 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33119.259329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33119.259329 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32843.594242 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 306000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 313000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19562.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1044 # number of writebacks -system.cpu.dcache.writebacks::total 1044 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2066 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2066 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18499 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18499 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks +system.cpu.dcache.writebacks::total 1041 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2130 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2130 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18331 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18331 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20565 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20565 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20565 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20565 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2807 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2807 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4623 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4623 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4623 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4623 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 59352000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 59352000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108156000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 108156000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167508000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 167508000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167508000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 167508000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20461 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20461 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20461 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20461 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4618 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4618 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4618 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4618 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 58649500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 58649500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107455500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 107455500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166105000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 166105000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166105000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 166105000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -540,98 +540,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32682.819383 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32682.819383 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38530.815818 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38530.815818 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36233.614536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36233.614536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36233.614536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36233.614536 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32474.806202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32474.806202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38213.193457 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38213.193457 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3980.169826 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13209 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5419 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.437535 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3978.553859 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13166 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5424 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.427360 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.857779 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2790.653305 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 816.658743 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011379 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.085164 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024922 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.121465 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12787 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 310 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13097 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1044 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1044 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12787 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 328 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13115 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812188 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255900 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.357468 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.357468 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32086.371100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34445.429741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32853.025937 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34246.959943 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34246.959943 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 7b678cb0b..793868398 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525920 # Number of seconds simulated -sim_ticks 525920061000 # Number of ticks simulated -final_tick 525920061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525834 # Number of seconds simulated +sim_ticks 525834342000 # Number of ticks simulated +final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787177 # Simulator instruction rate (inst/s) -host_op_rate 1006377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1517904458 # Simulator tick rate (ticks/s) -host_mem_usage 235608 # Number of bytes of host memory used -host_seconds 346.48 # Real time elapsed on the host +host_inst_rate 739511 # Simulator instruction rate (inst/s) +host_op_rate 945437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1425757824 # Simulator tick rate (ticks/s) +host_mem_usage 241188 # Number of bytes of host memory used +host_seconds 368.81 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 166976 # Nu system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 513903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 513903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051840122 # number of cpu cycles simulated +system.cpu.numCycles 1051668684 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739283 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 177024356 # nu system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051840122 # Number of busy cycles +system.cpu.num_busy_cycles 1051668684 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.965460 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.965460 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.862288 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.862288 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328087000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328087000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328087000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328087000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328087000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328087000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21027.174261 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21027.174261 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21027.174261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21027.174261 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281278000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281278000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281278000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281278000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281278000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281278000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18027.174261 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18027.174261 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.361570 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.361570 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.751553 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.751553 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 4478 # n system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses system.cpu.dcache.overall_misses::total 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80120000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80120000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 160192000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 160192000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 240312000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 240312000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 240312000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 240312000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49887.920299 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49887.920299 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55777.158774 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55777.158774 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53665.029031 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53665.029031 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4478 system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75302000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75302000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151576000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151576000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46887.920299 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46887.920299 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52777.158774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52777.158774 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3487.655618 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.607182 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2408.352970 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 737.695465 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073497 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106435 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 0912a812f..1c7f4cd18 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.646278 # Number of seconds simulated -sim_ticks 646278143000 # Number of ticks simulated -final_tick 646278143000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.644314 # Number of seconds simulated +sim_ticks 644314104000 # Number of ticks simulated +final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208687 # Simulator instruction rate (inst/s) -host_op_rate 208687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73980757 # Simulator tick rate (ticks/s) -host_mem_usage 229204 # Number of bytes of host memory used -host_seconds 8735.76 # Real time elapsed on the host +host_inst_rate 127860 # Simulator instruction rate (inst/s) +host_op_rate 127860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45189117 # Simulator tick rate (ticks/s) +host_mem_usage 230524 # Number of bytes of host memory used +host_seconds 14258.17 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 191680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94465088 # Number of bytes read from this memory -system.physmem.bytes_read::total 94656768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 191680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 191680 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94463936 # Number of bytes read from this memory +system.physmem.bytes_read::total 94654784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 190848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 190848 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476017 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2982 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475999 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1478981 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 296591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146167852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146464443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 296591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 296591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6624813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6624813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6624813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 296591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146167852 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153089256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 296203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146611622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146907826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 296203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 296203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6645007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6645007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6645007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 296203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146611622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153552833 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 528353322 # DTB read hits -system.cpu.dtb.read_misses 626455 # DTB read misses +system.cpu.dtb.read_hits 526091283 # DTB read hits +system.cpu.dtb.read_misses 609189 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 528979777 # DTB read accesses -system.cpu.dtb.write_hits 292227311 # DTB write hits -system.cpu.dtb.write_misses 54391 # DTB write misses +system.cpu.dtb.read_accesses 526700472 # DTB read accesses +system.cpu.dtb.write_hits 292251681 # DTB write hits +system.cpu.dtb.write_misses 54656 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 292281702 # DTB write accesses -system.cpu.dtb.data_hits 820580633 # DTB hits -system.cpu.dtb.data_misses 680846 # DTB misses +system.cpu.dtb.write_accesses 292306337 # DTB write accesses +system.cpu.dtb.data_hits 818342964 # DTB hits +system.cpu.dtb.data_misses 663845 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 821261479 # DTB accesses -system.cpu.itb.fetch_hits 401438115 # ITB hits -system.cpu.itb.fetch_misses 852 # ITB misses +system.cpu.dtb.data_accesses 819006809 # DTB accesses +system.cpu.itb.fetch_hits 402493704 # ITB hits +system.cpu.itb.fetch_misses 819 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 401438967 # ITB accesses +system.cpu.itb.fetch_accesses 402494523 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1292556287 # number of cpu cycles simulated +system.cpu.numCycles 1288628209 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 394747270 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 256599366 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27590844 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 323468940 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262010178 # Number of BTB hits +system.cpu.BPredUnit.lookups 393523603 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 256622136 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27591372 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 324682531 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262034039 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57787448 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7273 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421195062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3322341707 # Number of instructions fetch has processed -system.cpu.fetch.Branches 394747270 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 319797626 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638354680 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162914776 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 98034186 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9284 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 401438115 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8412038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1292428872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.570619 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.140035 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57682078 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6792 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421081938 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3322079900 # Number of instructions fetch has processed +system.cpu.fetch.Branches 393523603 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 319716117 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638226273 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162822813 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 94445154 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8938 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402493704 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9540813 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1288505558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.578243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.138227 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 654074192 50.61% 50.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60911661 4.71% 55.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43750931 3.39% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72637907 5.62% 64.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126293368 9.77% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45669959 3.53% 77.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41606825 3.22% 80.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7021986 0.54% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 240462043 18.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 650279285 50.47% 50.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 59669001 4.63% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43760756 3.40% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72624833 5.64% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127388332 9.89% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46848563 3.64% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41619525 3.23% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7020509 0.54% 81.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 239294754 18.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1292428872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305400 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.570365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 452871377 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80658879 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 614115225 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9960097 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134823294 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 34649231 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12312 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3231646719 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46688 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134823294 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 482927898 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33597059 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 26321 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 592678255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48376045 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3142025529 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 359 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42577598 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2088048291 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3654580534 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3537192548 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117387986 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1288505558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305382 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.577997 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 453351036 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 77522549 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 613342023 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9559025 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134730925 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33522574 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12306 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3228150524 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46600 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134730925 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 483601779 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 32079469 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 591314469 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46752919 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3136805366 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 365 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7001 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40828800 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2086363185 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3649389993 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3531980340 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117409653 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 703079221 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4247 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 139 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 143016934 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 739120183 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 360450433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67842482 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9359459 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2647443516 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 119 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2196739037 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17945817 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 824288886 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 711675229 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1292428872 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.699698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805222 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 701394115 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4228 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 134 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 140886298 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 736269341 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 360318998 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68834783 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9382400 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2642228655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2193185137 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17944949 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 819070745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 708820503 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 83 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1288505558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.702115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805670 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470829232 36.43% 36.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 219635474 16.99% 53.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252835921 19.56% 72.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120249084 9.30% 82.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106312849 8.23% 90.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 78591497 6.08% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21017973 1.63% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17286986 1.34% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5669856 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470226956 36.49% 36.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 215277039 16.71% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 253569254 19.68% 72.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121312750 9.41% 82.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106354397 8.25% 90.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 77759673 6.03% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21099202 1.64% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17230121 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5676166 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1292428872 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1288505558 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1140834 3.16% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24068551 66.72% 69.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10866173 30.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1175249 3.24% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24027488 66.23% 69.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11077412 30.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1257954367 57.26% 57.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29223285 1.33% 58.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254700 0.38% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204654 0.33% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 590393009 26.88% 86.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 303689578 13.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1255595425 57.25% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16675 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29225002 1.33% 58.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589172005 26.86% 86.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 303713925 13.85% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2196739037 # Type of FU issued -system.cpu.iq.rate 1.699531 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36075558 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5585448865 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3387972537 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2024033733 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 154479456 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 83833082 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75371142 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2153745375 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 79066468 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69378492 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2193185137 # Type of FU issued +system.cpu.iq.rate 1.701953 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36280149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016542 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5574611120 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3377500690 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2021426713 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 154489810 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 83871907 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75374894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2150389693 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 79072841 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67211668 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 228050157 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2255425 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 75959 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 149655537 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 225199315 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24267 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76315 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 149524102 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4423 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4398 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134823294 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4267155 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 460832 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3006059047 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2702146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 739120183 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 360450433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 119 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 451591 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5232 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 75959 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27593158 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31610 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27624768 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2105923301 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 528979869 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90815736 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134730925 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4001327 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 199767 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3000725705 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2706866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 736269341 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 360318998 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195059 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4865 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76315 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27584399 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31784 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27616183 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2101081456 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526700571 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 92103681 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358615412 # number of nop insts executed -system.cpu.iew.exec_refs 821261997 # number of memory reference insts executed -system.cpu.iew.exec_branches 282350798 # Number of branches executed -system.cpu.iew.exec_stores 292282128 # Number of stores executed -system.cpu.iew.exec_rate 1.629270 # Inst execution rate -system.cpu.iew.wb_sent 2102194150 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2099404875 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185212780 # num instructions producing a value -system.cpu.iew.wb_consumers 1754721967 # num instructions consuming a value +system.cpu.iew.exec_nop 358496928 # number of nop insts executed +system.cpu.iew.exec_refs 819007361 # number of memory reference insts executed +system.cpu.iew.exec_branches 281208089 # Number of branches executed +system.cpu.iew.exec_stores 292306790 # Number of stores executed +system.cpu.iew.exec_rate 1.630479 # Inst execution rate +system.cpu.iew.wb_sent 2099578580 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2096801607 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1184710151 # num instructions producing a value +system.cpu.iew.wb_consumers 1754117094 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.624227 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675442 # average fanout of values written-back +system.cpu.iew.wb_rate 1.627158 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675388 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 980398495 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 975019383 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27578641 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1157605578 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.735468 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.494432 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27579200 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1153774633 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.741231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495587 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 541345066 46.76% 46.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227581476 19.66% 66.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119272186 10.30% 76.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56742028 4.90% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 51019590 4.41% 86.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24162950 2.09% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18255180 1.58% 89.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15605334 1.35% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103621768 8.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 537356152 46.57% 46.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227667410 19.73% 66.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119239977 10.33% 76.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56780365 4.92% 81.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50766064 4.40% 85.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24581833 2.13% 88.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18432159 1.60% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15672614 1.36% 91.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103278059 8.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1157605578 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1153774633 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103621768 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103278059 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4037733499 # The number of ROB reads -system.cpu.rob.rob_writes 6113598006 # The number of ROB writes -system.cpu.timesIdled 3575 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 127415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4028867151 # The number of ROB reads +system.cpu.rob.rob_writes 6102747283 # The number of ROB writes +system.cpu.timesIdled 3543 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 122651 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.709010 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.709010 # CPI: Total CPI of All Threads -system.cpu.ipc 1.410417 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.410417 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2681938582 # number of integer regfile reads -system.cpu.int_regfile_writes 1518871452 # number of integer regfile writes -system.cpu.fp_regfile_reads 81943465 # number of floating regfile reads -system.cpu.fp_regfile_writes 54033824 # number of floating regfile writes +system.cpu.cpi 0.706855 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.706855 # CPI: Total CPI of All Threads +system.cpu.ipc 1.414716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.414716 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2678227479 # number of integer regfile reads +system.cpu.int_regfile_writes 1517398403 # number of integer regfile writes +system.cpu.fp_regfile_reads 81948895 # number of floating regfile reads +system.cpu.fp_regfile_writes 54035615 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8410 # number of replacements -system.cpu.icache.tagsinuse 1670.523326 # Cycle average of tags in use -system.cpu.icache.total_refs 401426768 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10133 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39615.786835 # Average number of references to valid blocks. +system.cpu.icache.replacements 8420 # number of replacements +system.cpu.icache.tagsinuse 1668.242053 # Cycle average of tags in use +system.cpu.icache.total_refs 402482315 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39688.621931 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1670.523326 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.815685 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.815685 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 401426768 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 401426768 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 401426768 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 401426768 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 401426768 # number of overall hits -system.cpu.icache.overall_hits::total 401426768 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11347 # number of overall misses -system.cpu.icache.overall_misses::total 11347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204562000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204562000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204562000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204562000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204562000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204562000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 401438115 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 401438115 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 401438115 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 401438115 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 401438115 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 401438115 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1668.242053 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.814571 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.814571 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402482315 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402482315 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402482315 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402482315 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402482315 # number of overall hits +system.cpu.icache.overall_hits::total 402482315 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11389 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11389 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11389 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11389 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11389 # number of overall misses +system.cpu.icache.overall_misses::total 11389 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 178670000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 178670000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 178670000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 178670000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 178670000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 178670000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402493704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402493704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402493704 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402493704 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 402493704 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 402493704 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.848771 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18027.848771 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18027.848771 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18027.848771 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15687.944508 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15687.944508 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15687.944508 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15687.944508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15687.944508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15687.944508 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +388,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1213 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1213 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1213 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1213 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1213 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1213 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10134 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10134 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10134 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10134 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10134 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10134 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139352000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 139352000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139352000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 139352000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139352000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 139352000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1247 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1247 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1247 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1247 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1247 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1247 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10142 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10142 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10142 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10142 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10142 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10142 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124096500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124096500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13750.937438 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13750.937438 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13750.937438 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13750.937438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13750.937438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13750.937438 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12235.900217 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12235.900217 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12235.900217 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12235.900217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12235.900217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12235.900217 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1528066 # number of replacements -system.cpu.dcache.tagsinuse 4095.024861 # Cycle average of tags in use -system.cpu.dcache.total_refs 667221349 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532162 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 435.477025 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 286461000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.024861 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999762 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999762 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 457042035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457042035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210179266 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210179266 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 48 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 48 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667221301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667221301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667221301 # number of overall hits -system.cpu.dcache.overall_hits::total 667221301 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928301 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1928301 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 615630 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 615630 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2543931 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2543931 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2543931 # number of overall misses -system.cpu.dcache.overall_misses::total 2543931 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609210500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76609210500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362476485 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30362476485 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106971686985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106971686985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106971686985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106971686985 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 458970336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 458970336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1528011 # number of replacements +system.cpu.dcache.tagsinuse 4095.070038 # Cycle average of tags in use +system.cpu.dcache.total_refs 666681777 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1532107 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 435.140481 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 262302000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.070038 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999773 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999773 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 456946751 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 456946751 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209734975 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209734975 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 51 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 51 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 666681726 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666681726 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666681726 # number of overall hits +system.cpu.dcache.overall_hits::total 666681726 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928385 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928385 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1059921 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1059921 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2988306 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2988306 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2988306 # number of overall misses +system.cpu.dcache.overall_misses::total 2988306 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71846140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71846140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29139765486 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29139765486 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 19500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 19500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 100985905486 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 100985905486 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 100985905486 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 100985905486 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 458875136 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458875136 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 48 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 48 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 669765232 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 669765232 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 669765232 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 669765232 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004201 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004201 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002921 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002921 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003798 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003798 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003798 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003798 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.865203 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.865203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.358194 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.358194 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42049.759598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42049.759598 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 174500 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669670032 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669670032 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669670032 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669670032 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005028 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005028 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.019231 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.019231 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004462 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004462 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004462 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004462 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37257.155599 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37257.155599 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27492.393760 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27492.393760 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33793.696324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33793.696324 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9184.210526 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7952.380952 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109390 # number of writebacks -system.cpu.dcache.writebacks::total 109390 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467746 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467746 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 544023 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 544023 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1011769 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1011769 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1011769 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1011769 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460555 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460555 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71607 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71607 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1532162 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1532162 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1532162 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1532162 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266349000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266349000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176578500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176578500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 53442927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 53442927500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 109393 # number of writebacks +system.cpu.dcache.writebacks::total 109393 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467889 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467889 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 988310 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 988310 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1456199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1456199 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1456199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1456199 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460496 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460496 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71611 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71611 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1532107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532107 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532107 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532107 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50211071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50211071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3191098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3191098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53402169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 53402169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53402169000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 53402169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003183 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003183 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.923399 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.923399 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.284511 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.284511 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34379.464922 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34379.464922 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44561.561771 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44561.561771 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34855.378247 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34855.378247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34855.378247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34855.378247 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480672 # number of replacements -system.cpu.l2cache.tagsinuse 32700.801233 # Cycle average of tags in use -system.cpu.l2cache.total_refs 66336 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.043832 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480649 # number of replacements +system.cpu.l2cache.tagsinuse 32705.674184 # Cycle average of tags in use +system.cpu.l2cache.total_refs 66319 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513383 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.043822 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3222.422931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 46.121134 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29432.257169 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.098341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001408 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.898201 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997949 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7139 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51386 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 58525 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109390 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109390 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4759 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7139 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 56145 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 63284 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7139 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 56145 # number of overall hits -system.cpu.l2cache.overall_hits::total 63284 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964838 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933614 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933614 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.958977 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.958977 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32524.983233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31227.504751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31230.244653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43580.260855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43580.260855 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index ed560b063..a8bcfc08a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.813572 # Number of seconds simulated -sim_ticks 2813572242000 # Number of ticks simulated -final_tick 2813572242000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.811836 # Number of seconds simulated +sim_ticks 2811836424000 # Number of ticks simulated +final_tick 2811836424000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1893151 # Simulator instruction rate (inst/s) -host_op_rate 1893151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2651343461 # Simulator tick rate (ticks/s) -host_mem_usage 227888 # Number of bytes of host memory used -host_seconds 1061.19 # Real time elapsed on the host +host_inst_rate 1325085 # Simulator instruction rate (inst/s) +host_op_rate 1325085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1854626286 # Simulator tick rate (ticks/s) +host_mem_usage 228472 # Number of bytes of host memory used +host_seconds 1516.12 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475279 # Nu system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33558000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33612069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1521721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1521721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1521721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33558000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35133790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33578716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33632818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54103 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54103 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1522660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1522660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1522660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33578716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35155479 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5627144484 # number of cpu cycles simulated +system.cpu.numCycles 5623672848 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5627144484 # Number of busy cycles +system.cpu.num_busy_cycles 5623672848 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.417406 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.427768 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.417406 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721883 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721883 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1478.427768 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.721889 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.721889 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 248319000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 248319000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 248319000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 248319000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 248319000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 248319000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 237582000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 237582000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 237582000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 237582000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 237582000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 237582000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23435.164213 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23435.164213 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22421.857305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216531000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216531000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216531000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216531000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216531000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216531000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.192384 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.209846 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1063975000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.192384 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999803 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999803 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.209846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999807 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999807 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567803000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79567803000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3816006000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3816006000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83383809000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83383809000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83383809000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83383809000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81853590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81853590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81853590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81853590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54494.092713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54494.092713 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53566.024227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53566.024227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53494.043698 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793377000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78793377000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793377000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78793377000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1479705 # number of replacements -system.cpu.l2cache.tagsinuse 32703.875584 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32704.499819 # Cycle average of tags in use system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3255.326122 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.503711 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29415.045751 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.099345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3254.482584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.474832 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29416.542403 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.099319 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.897676 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.897722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998062 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b1563a03b..70391a345 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.653191 # Number of seconds simulated -sim_ticks 653190727500 # Number of ticks simulated -final_tick 653190727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.659244 # Number of seconds simulated +sim_ticks 659244465000 # Number of ticks simulated +final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90710 # Simulator instruction rate (inst/s) -host_op_rate 123535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42799734 # Simulator tick rate (ticks/s) -host_mem_usage 235092 # Number of bytes of host memory used -host_seconds 15261.56 # Real time elapsed on the host -sim_insts 1384379220 # Number of instructions simulated -sim_ops 1885333972 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 203328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94517952 # Number of bytes read from this memory -system.physmem.bytes_read::total 94721280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 203328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 203328 # Number of instructions bytes read from this memory +host_inst_rate 88407 # Simulator instruction rate (inst/s) +host_op_rate 120399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42099861 # Simulator tick rate (ticks/s) +host_mem_usage 243836 # Number of bytes of host memory used +host_seconds 15659.07 # Real time elapsed on the host +sim_insts 1384375635 # Number of instructions simulated +sim_ops 1885330387 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94515200 # Number of bytes read from this memory +system.physmem.bytes_read::total 94714816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 199616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 199616 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476843 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1480020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476800 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479919 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 311284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 144701919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 145013204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 311284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 311284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6476418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6476418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6476418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 311284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 144701919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 151489621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 143368970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 143671765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6416946 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6416946 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6416946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 143368970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 150088711 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1306381456 # number of cpu cycles simulated +system.cpu.numCycles 1318488931 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 451886525 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 356592173 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33205003 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 281633187 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 237475635 # Number of BTB hits +system.cpu.BPredUnit.lookups 461326092 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 364071075 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 34100101 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 298580925 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 245422956 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53725762 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2808142 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 371691213 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2329385713 # Number of instructions fetch has processed -system.cpu.fetch.Branches 451886525 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 291201397 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621090552 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 170450530 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 138693587 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 29461 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 349470928 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11301689 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1268700671 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.542231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.167897 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 54976315 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2806988 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 381926912 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2354617227 # Number of instructions fetch has processed +system.cpu.fetch.Branches 461326092 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 300399271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 631966560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 174781634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133381872 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1547 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 26290 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 359560180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11891763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1287933807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.529860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156146 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 647656502 51.05% 51.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44886599 3.54% 54.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100617653 7.93% 62.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 60404416 4.76% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73875113 5.82% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44960792 3.54% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31035484 2.45% 79.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30635125 2.41% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 234628987 18.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 656012764 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47127862 3.66% 54.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105351348 8.18% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 60429666 4.69% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 75027065 5.83% 73.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45419751 3.53% 76.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32157937 2.50% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 32241388 2.50% 81.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 234166026 18.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1268700671 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345907 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.783082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 423570129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 110130146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 579255946 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18563929 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 137180521 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 50568077 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 14826 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3119517279 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28937 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 137180521 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 460603750 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40419610 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 558753819 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71243284 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3033648086 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 193 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4887381 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56133943 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1685 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2996122982 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14446186472 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13843342856 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 602843616 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153898 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1002969084 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28984 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 185421286 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 977548256 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 509159433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36902722 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 39166460 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2862588309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35911 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2484024411 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13118317 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 964784903 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2432051802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12801 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1268700671 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.957928 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.885204 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1287933807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349890 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.785845 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433461682 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105761116 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 591844441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16248270 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 140618298 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 52072887 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12605 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3150187282 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 23939 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 140618298 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 469309271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39277977 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 483250 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 570159229 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68085782 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3069262221 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 155 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4380621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54394099 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1922 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3038163295 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14611934802 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13977694721 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 634240081 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993148162 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1045015133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27322 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23140 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179514029 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 982659180 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 514844433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35819898 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36120464 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2890303698 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 33130 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2506565055 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17234382 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 992532581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2476785189 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1287933807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.946191 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883330 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 413577866 32.60% 32.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 194484687 15.33% 47.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 205713957 16.21% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171271635 13.50% 77.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 131142170 10.34% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97400688 7.68% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37845090 2.98% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12462379 0.98% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4802199 0.38% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 425460645 33.03% 33.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 193710960 15.04% 48.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 207680071 16.13% 64.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 174651445 13.56% 77.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137124890 10.65% 88.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 94993427 7.38% 95.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35869114 2.79% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12687801 0.99% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5755454 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1268700671 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1287933807 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 960888 1.05% 1.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23894 0.03% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55821815 60.83% 61.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 34963808 38.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 692420 0.75% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24115 0.03% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56113360 61.04% 61.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35101326 38.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1133289530 45.62% 45.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11232040 0.45% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876506 0.28% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503108 0.22% 46.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23588545 0.95% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 841636528 33.88% 81.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 460522863 18.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1147061112 45.76% 45.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11228333 0.45% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876483 0.27% 46.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5512765 0.22% 46.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 16 0.00% 46.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23755231 0.95% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 846734490 33.78% 81.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 464021335 18.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2484024411 # Type of FU issued -system.cpu.iq.rate 1.901454 # Inst issue rate -system.cpu.iq.fu_busy_cnt 91770405 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036944 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6213658406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3738455000 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2292430207 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 127979809 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 89021624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58699426 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2509271154 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66523662 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 80303664 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2506565055 # Type of FU issued +system.cpu.iq.rate 1.901089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91931221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036676 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6281789129 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3788847878 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2312502456 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 128440391 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 94088071 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58648289 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2531838073 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66658203 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 81288215 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 346159349 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1403998 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 232162410 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 351270990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1405210 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 237848127 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 137180521 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17480517 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1686547 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2862638347 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 10688123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 977548256 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 509159433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24752 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1673918 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2091 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1403998 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34817527 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1757167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36574694 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2405136648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 795998932 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78887763 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 140618298 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16819525 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1547443 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2890351322 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8718298 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 982659180 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 514844433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22537 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1538114 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1067 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1405210 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36121914 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2298987 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 38420901 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2424696979 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 800223206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 81868076 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14127 # number of nop insts executed -system.cpu.iew.exec_refs 1234173393 # number of memory reference insts executed -system.cpu.iew.exec_branches 329367580 # Number of branches executed -system.cpu.iew.exec_stores 438174461 # Number of stores executed -system.cpu.iew.exec_rate 1.841068 # Inst execution rate -system.cpu.iew.wb_sent 2376887575 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2351129633 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1360698402 # num instructions producing a value -system.cpu.iew.wb_consumers 2562363668 # num instructions consuming a value +system.cpu.iew.exec_nop 14494 # number of nop insts executed +system.cpu.iew.exec_refs 1240121255 # number of memory reference insts executed +system.cpu.iew.exec_branches 334180264 # Number of branches executed +system.cpu.iew.exec_stores 439898049 # Number of stores executed +system.cpu.iew.exec_rate 1.838997 # Inst execution rate +system.cpu.iew.wb_sent 2396725321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2371150745 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1368219909 # num instructions producing a value +system.cpu.iew.wb_consumers 2564381587 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.799727 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.531033 # average fanout of values written-back +system.cpu.iew.wb_rate 1.798385 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533548 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 977293768 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23110 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33191422 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1131520152 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.666205 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.368466 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 1005010225 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22393 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 34087773 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1147315511 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.643263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.351044 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 484597847 42.83% 42.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 298921465 26.42% 69.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90821305 8.03% 77.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 72269012 6.39% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 45034307 3.98% 87.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23256378 2.06% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15793077 1.40% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9817791 0.87% 91.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 91008970 8.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 497187613 43.33% 43.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 300050723 26.15% 69.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93458742 8.15% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72384885 6.31% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45393865 3.96% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22818775 1.99% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15801520 1.38% 91.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11015018 0.96% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89204370 7.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1131520152 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390236 # Number of instructions committed -system.cpu.commit.committedOps 1885344988 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1147315511 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384386651 # Number of instructions committed +system.cpu.commit.committedOps 1885341403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385930 # Number of memory references committed -system.cpu.commit.loads 631388907 # Number of loads committed +system.cpu.commit.refs 908384496 # Number of memory references committed +system.cpu.commit.loads 631388190 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299636121 # Number of branches committed +system.cpu.commit.branches 299635404 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705771 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653702903 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 91008970 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89204370 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3903131593 # The number of ROB reads -system.cpu.rob.rob_writes 5862472148 # The number of ROB writes -system.cpu.timesIdled 1341228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37680785 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379220 # Number of Instructions Simulated -system.cpu.committedOps 1885333972 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379220 # Number of Instructions Simulated -system.cpu.cpi 0.943659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.943659 # CPI: Total CPI of All Threads -system.cpu.ipc 1.059705 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.059705 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11952036932 # number of integer regfile reads -system.cpu.int_regfile_writes 2256711080 # number of integer regfile writes -system.cpu.fp_regfile_reads 70681119 # number of floating regfile reads -system.cpu.fp_regfile_writes 50325350 # number of floating regfile writes -system.cpu.misc_regfile_reads 3723531681 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776354 # number of misc regfile writes -system.cpu.icache.replacements 23459 # number of replacements -system.cpu.icache.tagsinuse 1656.238339 # Cycle average of tags in use -system.cpu.icache.total_refs 349436364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 25154 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13891.880576 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3948444424 # The number of ROB reads +system.cpu.rob.rob_writes 5921335810 # The number of ROB writes +system.cpu.timesIdled 1335770 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30555124 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384375635 # Number of Instructions Simulated +system.cpu.committedOps 1885330387 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384375635 # Number of Instructions Simulated +system.cpu.cpi 0.952407 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.952407 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049971 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049971 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12040516185 # number of integer regfile reads +system.cpu.int_regfile_writes 2278755627 # number of integer regfile writes +system.cpu.fp_regfile_reads 70304928 # number of floating regfile reads +system.cpu.fp_regfile_writes 50983418 # number of floating regfile writes +system.cpu.misc_regfile_reads 3755360027 # number of misc regfile reads +system.cpu.misc_regfile_writes 13774920 # number of misc regfile writes +system.cpu.icache.replacements 22971 # number of replacements +system.cpu.icache.tagsinuse 1659.651348 # Cycle average of tags in use +system.cpu.icache.total_refs 359526375 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24666 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14575.787521 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1656.238339 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808710 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808710 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 349440471 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 349440471 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 349440471 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 349440471 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 349440471 # number of overall hits -system.cpu.icache.overall_hits::total 349440471 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30457 # number of overall misses -system.cpu.icache.overall_misses::total 30457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 315232000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 315232000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 315232000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 315232000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 315232000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 315232000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 349470928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 349470928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 349470928 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 349470928 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 349470928 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 349470928 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10350.067308 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10350.067308 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10350.067308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10350.067308 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1659.651348 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.810377 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.810377 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 359530551 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 359530551 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 359530551 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 359530551 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 359530551 # number of overall hits +system.cpu.icache.overall_hits::total 359530551 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 29629 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 29629 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 29629 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 29629 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 29629 # number of overall misses +system.cpu.icache.overall_misses::total 29629 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 243264500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 243264500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 243264500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 243264500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 243264500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 243264500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 359560180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 359560180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 359560180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 359560180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 359560180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 359560180 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000082 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000082 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000082 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000082 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000082 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000082 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8210.351345 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8210.351345 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8210.351345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8210.351345 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 916 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 916 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 916 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 916 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 916 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 916 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29541 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 29541 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 29541 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 29541 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 29541 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 29541 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 200922000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 200922000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 200922000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 200922000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 200922000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 200922000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6801.462374 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6801.462374 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 731 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 731 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 731 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 731 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 731 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 731 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28898 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28898 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28898 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28898 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28898 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28898 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 166216000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 166216000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 166216000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 166216000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 166216000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 166216000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5751.816735 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5751.816735 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533244 # number of replacements -system.cpu.dcache.tagsinuse 4094.802366 # Cycle average of tags in use -system.cpu.dcache.total_refs 977260435 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537340 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 635.682695 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 300664000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.802366 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 701107300 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 701107300 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276115713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276115713 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 12426 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 12426 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11711 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11711 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 977223013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 977223013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 977223013 # number of overall hits -system.cpu.dcache.overall_hits::total 977223013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2133926 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2133926 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 819965 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 819965 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2953891 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2953891 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2953891 # number of overall misses -system.cpu.dcache.overall_misses::total 2953891 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80611211500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80611211500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33925562500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33925562500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 304000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114536774000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114536774000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114536774000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114536774000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 703241226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 703241226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533081 # number of replacements +system.cpu.dcache.tagsinuse 4094.855996 # Cycle average of tags in use +system.cpu.dcache.total_refs 980345028 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537177 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 637.756763 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 283497000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.855996 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999721 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999721 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 704193068 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 704193068 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276118274 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276118274 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11579 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11579 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10994 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10994 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 980311342 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 980311342 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 980311342 # number of overall hits +system.cpu.dcache.overall_hits::total 980311342 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2282979 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2282979 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 817404 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 817404 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3100383 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3100383 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3100383 # number of overall misses +system.cpu.dcache.overall_misses::total 3100383 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77215847500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77215847500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27888772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27888772000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105104619500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105104619500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105104619500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105104619500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 706476047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 706476047 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 980176904 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 980176904 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 980176904 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 980176904 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003034 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003034 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002961 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002961 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000884 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000884 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37776.010743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37776.010743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41374.403176 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41374.403176 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 27636.363636 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 27636.363636 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38774.881673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38774.881673 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11582 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11582 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10994 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10994 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 983411725 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 983411725 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 983411725 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 983411725 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002952 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002952 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000259 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000259 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33822.408134 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33822.408134 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34118.712411 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34118.712411 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108418 # number of writebacks -system.cpu.dcache.writebacks::total 108418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 669125 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 669125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 11 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 11 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1412163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1412163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1412163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1412163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464801 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464801 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76927 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76927 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541728 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541728 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541728 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541728 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50340349002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50340349002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506118000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506118000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52846467002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52846467002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52846467002 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52846467002 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001573 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001573 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34366.681209 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34366.681209 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32577.872529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32577.872529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks +system.cpu.dcache.writebacks::total 108430 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 818362 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 818362 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740610 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 740610 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1558972 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1558972 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1558972 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1558972 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464617 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76794 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76794 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541411 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541411 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541411 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541411 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50261586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50261586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2476957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2476957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52738544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52738544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52738544000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52738544000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002073 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002073 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001567 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34317.221840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34317.221840 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32254.570670 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32254.570670 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480210 # number of replacements -system.cpu.l2cache.tagsinuse 32693.720569 # Cycle average of tags in use -system.cpu.l2cache.total_refs 84475 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512954 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.055834 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480118 # number of replacements +system.cpu.l2cache.tagsinuse 32698.465426 # Cycle average of tags in use +system.cpu.l2cache.total_refs 83907 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512862 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.055462 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3140.945883 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 59.138585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29493.636100 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.095854 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001805 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.900074 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997733 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 54011 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 75979 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108418 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 131130000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 131130000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049298500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049298500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101115000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46222898000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46324013000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101115000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46222898000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46324013000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.949342 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999291 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999291 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910683 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910683 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.947546 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.947546 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32419.044566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31312.826651 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31315.267025 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.917193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.917193 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 06a14cc7a..1b9ad306d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.369932 # Number of seconds simulated -sim_ticks 2369931974000 # Number of ticks simulated -final_tick 2369931974000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.368273 # Number of seconds simulated +sim_ticks 2368273403000 # Number of ticks simulated +final_tick 2368273403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 844398 # Simulator instruction rate (inst/s) -host_op_rate 1145486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1448435887 # Simulator tick rate (ticks/s) -host_mem_usage 232760 # Number of bytes of host memory used -host_seconds 1636.20 # Real time elapsed on the host +host_inst_rate 821983 # Simulator instruction rate (inst/s) +host_op_rate 1115078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1408999350 # Simulator tick rate (ticks/s) +host_mem_usage 241788 # Number of bytes of host memory used +host_seconds 1680.82 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475585 # Nu system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39848165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39909115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60950 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60950 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785003 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785003 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39848165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41694118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 60993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39876072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39937065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1786253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1786253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1786253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39876072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41723318 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4739863948 # number of cpu cycles simulated +system.cpu.numCycles 4736546806 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1381604339 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 908382479 # nu system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4739863948 # Number of busy cycles +system.cpu.num_busy_cycles 4736546806 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.322496 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1392.329214 # Cycle average of tags in use system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.322496 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.679845 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.679845 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1392.329214 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.679848 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.679848 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 19803 # n system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 372133000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 372133000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 372133000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 372133000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 372133000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 372133000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352238000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352238000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352238000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352238000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352238000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352238000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18791.748725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18791.748725 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18791.748725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18791.748725 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17787.102964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17787.102964 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 19803 system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312724000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312724000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312724000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312724000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312724000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312724000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312632000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312632000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15791.748725 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15791.748725 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.950469 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.965929 # Cycle average of tags in use system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1004561000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.950469 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999744 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999744 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.965929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999748 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999748 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650958000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79650958000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794840000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3794840000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83445798000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83445798000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83445798000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83445798000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78190013000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78190013000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81912059000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81912059000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81912059000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81912059000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.849009 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.849009 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.247595 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.247595 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54409.829342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54409.829342 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53409.773267 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268339000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268339000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844839000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78844839000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844839000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78844839000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.849009 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.849009 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.247595 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.247595 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1478696 # number of replacements -system.cpu.l2cache.tagsinuse 32689.689328 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32690.092056 # Cycle average of tags in use system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3194.581985 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.931287 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29462.176056 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.097491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3194.112587 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 32.917167 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29463.062302 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.097477 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.899114 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.899141 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997622 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 1477842 # nu system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1475585 # number of overall misses system.cpu.l2cache.overall_misses::total 1477842 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117364000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117369000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73293584000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73410948000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73410953000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 117364000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 117369000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 76730420000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76847784000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 117364000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 76847789000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 117369000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 76730420000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76847784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76847789000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.951325 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.215330 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.003542 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.215330 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.003383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.215330 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.003383 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1477842 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1475585 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1477842 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90285000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56379680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469965000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90285000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59023400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59113680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90280000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59113685000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90285000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59023400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59113680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59113685000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 361b9fcbc..1f592bc6b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047911 # Number of seconds simulated -sim_ticks 47910588500 # Number of ticks simulated -final_tick 47910588500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.046793 # Number of seconds simulated +sim_ticks 46793182500 # Number of ticks simulated +final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102205 # Simulator instruction rate (inst/s) -host_op_rate 102205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55429613 # Simulator tick rate (ticks/s) -host_mem_usage 227308 # Number of bytes of host memory used -host_seconds 864.35 # Real time elapsed on the host +host_inst_rate 59681 # Simulator instruction rate (inst/s) +host_op_rate 59681 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31612654 # Simulator tick rate (ticks/s) +host_mem_usage 227600 # Number of bytes of host memory used +host_seconds 1480.20 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10788288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272832 # Number of bytes read from this memory +system.physmem.bytes_read::total 10787712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 514880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 514880 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160515 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160513 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168558 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10756036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 214419408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 225175443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10756036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10756036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154921913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154921913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154921913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10756036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 214419408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380097356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 11003312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 219536938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 230540250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11003312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11003312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158621397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158621397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158621397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11003312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 219536938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 389161648 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -42,18 +42,18 @@ system.cpu.dtb.read_hits 20277225 # DT system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 20367373 # DTB read accesses -system.cpu.dtb.write_hits 14736863 # DTB write hits +system.cpu.dtb.write_hits 14736820 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744115 # DTB write accesses -system.cpu.dtb.data_hits 35014088 # DTB hits +system.cpu.dtb.write_accesses 14744072 # DTB write accesses +system.cpu.dtb.data_hits 35014045 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111488 # DTB accesses -system.cpu.itb.fetch_hits 12475946 # ITB hits -system.cpu.itb.fetch_misses 12952 # ITB misses +system.cpu.dtb.data_accesses 35111445 # DTB accesses +system.cpu.itb.fetch_hits 12477645 # ITB hits +system.cpu.itb.fetch_misses 12958 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12488898 # ITB accesses +system.cpu.itb.fetch_accesses 12490603 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 95821178 # number of cpu cycles simulated +system.cpu.numCycles 93586366 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12442338 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5025331 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16200752 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5042995 # Number of BTB hits +system.cpu.branch_predictor.lookups 18829185 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12442057 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5026145 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16204746 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5047870 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.128154 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8471214 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10358543 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74332888 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 31.150565 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8475762 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10353423 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74332851 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126652138 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65238 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126652101 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65265 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292868 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14120784 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064786 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4680831 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 234000 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4914831 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8857404 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.686517 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775821 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292895 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14120054 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064610 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4681911 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233734 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4915645 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8856618 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.692355 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775927 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78582835 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78075293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 467389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25530263 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70290915 # Number of cycles cpu stages are processed. -system.cpu.activity 73.356346 # Percentage of cycles cpu is active +system.cpu.timesIdled 311800 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23300937 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70285429 # Number of cycles cpu stages are processed. +system.cpu.activity 75.102210 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.084678 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.059380 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.084678 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921933 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.059380 # CPI: Total CPI of All Threads +system.cpu.ipc 0.943948 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921933 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 42394050 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53427128 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 55.757119 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 53163082 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42658096 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 44.518442 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 52694545 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43126633 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.007413 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 73699998 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121180 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.085899 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 49718969 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46102209 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 48.112755 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85335 # number of replacements -system.cpu.icache.tagsinuse 1885.674638 # Cycle average of tags in use -system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks. +system.cpu.ipc_total 0.943948 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 40161098 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53425268 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 57.086593 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 50931554 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42654812 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.578019 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 50461046 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43125320 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 46.080772 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 71466223 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120143 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.636074 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47482076 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46104290 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.263896 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85221 # number of replacements +system.cpu.icache.tagsinuse 1887.407088 # Cycle average of tags in use +system.cpu.icache.total_refs 12359392 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87267 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.627328 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1885.674638 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12357256 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12357256 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12357256 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12357256 # number of overall hits -system.cpu.icache.overall_hits::total 12357256 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118639 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118639 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118639 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses -system.cpu.icache.overall_misses::total 118639 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081863500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2081863500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2081863500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2081863500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2081863500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2081863500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12475895 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12475895 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12475895 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009509 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009509 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.884760 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17547.884760 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17547.884760 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17547.884760 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1887.407088 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921585 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921585 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12359392 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12359392 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12359392 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12359392 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12359392 # number of overall hits +system.cpu.icache.overall_hits::total 12359392 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118206 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118206 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118206 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118206 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118206 # number of overall misses +system.cpu.icache.overall_misses::total 118206 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1871587000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1871587000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1871587000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1871587000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1871587000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1871587000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12477598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12477598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12477598 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12477598 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12477598 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12477598 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15833.265655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15833.265655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15833.265655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1025000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 105 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 11204.761905 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 10904.255319 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31258 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 31258 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 31258 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 31258 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 31258 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 31258 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87381 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87381 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87381 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364888000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1364888000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364888000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1364888000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364888000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1364888000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.963150 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.963150 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30939 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30939 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30939 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30939 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30939 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87267 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87267 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87267 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87267 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87267 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87267 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1309592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1309592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1309592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1309592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1309592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1309592500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006994 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006994 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006994 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15006.732213 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15006.732213 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.238819 # Cycle average of tags in use -system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4072.865489 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126021 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.238819 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945417 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945417 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34125947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34125947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34125947 # number of overall hits -system.cpu.dcache.overall_hits::total 34125947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96108 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96108 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667960 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667960 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 764068 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses -system.cpu.dcache.overall_misses::total 764068 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4228645000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 42089863000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 42089863000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46318508000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46318508000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46318508000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46318508000 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000352 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 486992000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.865489 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994352 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994352 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180532 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180532 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945489 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945489 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126021 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126021 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126021 # number of overall hits +system.cpu.dcache.overall_hits::total 34126021 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96106 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96106 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667888 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667888 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 763994 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 763994 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 763994 # number of overall misses +system.cpu.dcache.overall_misses::total 763994 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3881207000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3881207000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 34562623000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 34562623000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38443830000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38443830000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38443830000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38443830000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045709 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045709 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.886669 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.886669 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63012.550153 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63012.550153 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60620.923792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60620.923792 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045704 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045704 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40384.648201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40384.648201 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51749.130094 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51749.130094 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6946123500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6260683500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 55940.882990 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50440.975999 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks -system.cpu.dcache.writebacks::total 165805 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35341 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35341 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524380 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524380 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559721 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559721 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559721 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559721 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks +system.cpu.dcache.writebacks::total 165811 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35339 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35339 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524308 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524308 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559647 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559647 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559647 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559647 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7870166500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7870166500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9807011500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9807011500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9807011500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9807011500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1916080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1916080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7177771000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7177771000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9093851000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9093851000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9093851000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9093851000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -318,98 +318,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54813.807633 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54813.807633 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31531.587868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31531.587868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49991.440312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49991.440312 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 136141 # number of replacements -system.cpu.l2cache.tagsinuse 28773.050902 # Cycle average of tags in use -system.cpu.l2cache.total_refs 146499 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 167004 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.877219 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 136130 # number of replacements +system.cpu.l2cache.tagsinuse 28810.787246 # Cycle average of tags in use +system.cpu.l2cache.total_refs 146402 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 166994 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.876690 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25287.699561 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1723.905670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1761.445671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.771719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052609 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.053755 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.878084 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 79329 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31110 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 110439 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 165805 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 165805 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 25348.854435 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1730.144008 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1731.788804 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.773586 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052800 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.052850 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.879235 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 79222 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31112 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 110334 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 165811 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 165811 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52692.610285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53139.403356 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52617.962408 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52642.849939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53139.403356 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52617.962408 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52642.849939 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,50 +420,50 @@ system.cpu.l2cache.fast_writes 0 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329317000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6454083000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6783400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329317000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6454083000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6783400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486414 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253718 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.577822 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40106.060375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40106.060375 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.578018 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.578018 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40934.369173 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40104.136971 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40282.197222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40232.698955 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40232.698955 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index e1fb122e9..dcb5671a4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021620 # Number of seconds simulated -sim_ticks 21619627000 # Number of ticks simulated -final_tick 21619627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021083 # Number of seconds simulated +sim_ticks 21083079000 # Number of ticks simulated +final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209503 # Simulator instruction rate (inst/s) -host_op_rate 209503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56907639 # Simulator tick rate (ticks/s) -host_mem_usage 228332 # Number of bytes of host memory used -host_seconds 379.91 # Real time elapsed on the host +host_inst_rate 162660 # Simulator instruction rate (inst/s) +host_op_rate 162660 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43087037 # Simulator tick rate (ticks/s) +host_mem_usage 228624 # Number of bytes of host memory used +host_seconds 489.31 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10295552 # Number of bytes read from this memory -system.physmem.bytes_read::total 10855232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426432 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160868 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169613 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116038 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116038 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25887588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476213211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 502100799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25887588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25887588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 343504169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 343504169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 343504169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25887588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476213211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845604968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10295232 # Number of bytes read from this memory +system.physmem.bytes_read::total 10854784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 559552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 559552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426304 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160863 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169606 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116036 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116036 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 26540336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 488317290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 514857626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 26540336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 26540336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 352240012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 352240012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 352240012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 26540336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 488317290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867097638 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22478221 # DTB read hits -system.cpu.dtb.read_misses 218727 # DTB read misses -system.cpu.dtb.read_acv 49 # DTB read access violations -system.cpu.dtb.read_accesses 22696948 # DTB read accesses -system.cpu.dtb.write_hits 15797623 # DTB write hits -system.cpu.dtb.write_misses 42281 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15839904 # DTB write accesses -system.cpu.dtb.data_hits 38275844 # DTB hits -system.cpu.dtb.data_misses 261008 # DTB misses -system.cpu.dtb.data_acv 51 # DTB access violations -system.cpu.dtb.data_accesses 38536852 # DTB accesses -system.cpu.itb.fetch_hits 14126153 # ITB hits -system.cpu.itb.fetch_misses 38209 # ITB misses +system.cpu.dtb.read_hits 22489278 # DTB read hits +system.cpu.dtb.read_misses 215924 # DTB read misses +system.cpu.dtb.read_acv 41 # DTB read access violations +system.cpu.dtb.read_accesses 22705202 # DTB read accesses +system.cpu.dtb.write_hits 15793400 # DTB write hits +system.cpu.dtb.write_misses 42287 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 15835687 # DTB write accesses +system.cpu.dtb.data_hits 38282678 # DTB hits +system.cpu.dtb.data_misses 258211 # DTB misses +system.cpu.dtb.data_acv 41 # DTB access violations +system.cpu.dtb.data_accesses 38540889 # DTB accesses +system.cpu.itb.fetch_hits 14126698 # ITB hits +system.cpu.itb.fetch_misses 39196 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14164362 # ITB accesses +system.cpu.itb.fetch_accesses 14165894 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 43239256 # number of cpu cycles simulated +system.cpu.numCycles 42166161 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16713940 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10785641 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474517 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12148042 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7471828 # Number of BTB hits +system.cpu.BPredUnit.lookups 16730416 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10797894 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 473008 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12422807 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7474415 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1996046 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44341 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15442173 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106653150 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16713940 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9467874 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19795691 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2142333 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5738431 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 318072 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14126153 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221095 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42854841 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.488707 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154001 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1997304 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44664 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15021331 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106728114 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16730416 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9471719 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19806820 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2130939 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5131628 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318680 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14126698 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218104 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 41829396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.551510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.168900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23059150 53.81% 53.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1544639 3.60% 57.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1408806 3.29% 60.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1522467 3.55% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4195710 9.79% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1864977 4.35% 78.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 685640 1.60% 79.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1085683 2.53% 82.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7487769 17.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22022576 52.65% 52.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1548600 3.70% 56.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1408416 3.37% 59.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1521519 3.64% 63.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4198220 10.04% 73.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1858565 4.44% 77.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685862 1.64% 79.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1087856 2.60% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7497782 17.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42854841 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.386546 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.466582 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16604436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5227614 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18845700 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 731163 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1445928 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3801623 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109086 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104782719 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304838 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1445928 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17078558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2955442 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82947 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19068517 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2223449 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103359605 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 254 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 47854 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2072460 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62291613 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124619411 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124164571 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 454840 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 41829396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.396774 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.531132 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16130863 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4679035 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18837705 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 745587 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1436206 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3804156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108982 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104831583 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305633 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1436206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16616599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2463979 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 82005 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19040737 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2189870 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103389139 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14351 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2051944 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62312738 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124671441 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124212160 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 459281 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9744732 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5573 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5571 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4558890 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23363714 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16388828 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1131841 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 391237 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91420984 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5434 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89018152 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120887 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11240273 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4901766 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 851 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42854841 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.077202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.113927 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9765857 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5555 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5551 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4525057 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23373120 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16387776 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1111175 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 372431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91431067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5402 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89032304 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 124930 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11266116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4904200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 819 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 41829396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.128463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.117137 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 14370838 33.53% 33.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7100087 16.57% 50.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5540527 12.93% 63.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4772141 11.14% 74.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4704722 10.98% 85.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2673915 6.24% 91.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1941470 4.53% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1325823 3.09% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 425318 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13456265 32.17% 32.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6919123 16.54% 48.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5589725 13.36% 62.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4803253 11.48% 73.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4671765 11.17% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2679732 6.41% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1951840 4.67% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1334332 3.19% 98.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 423361 1.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42854841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 41829396 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 128315 6.76% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 799448 42.10% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 971123 51.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 128041 6.73% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 804964 42.29% 49.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 970251 50.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49717774 55.85% 55.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43792 0.05% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49721701 55.85% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43788 0.05% 55.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 120893 0.14% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121944 0.14% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38928 0.04% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22969813 25.80% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16004865 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121439 0.14% 56.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 86 0.00% 56.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 122461 0.14% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38932 0.04% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22979273 25.81% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16004570 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89018152 # Type of FU issued -system.cpu.iq.rate 2.058735 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1898886 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222303440 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102266391 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86984314 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 607478 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 416601 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296142 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90613228 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 303810 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1449481 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89032304 # Type of FU issued +system.cpu.iq.rate 2.111463 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1903256 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021377 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221310686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102298169 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86978851 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420531 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 298097 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90629664 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305896 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1444097 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3087076 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1775451 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3096482 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5652 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1774399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2459 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2494 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 46 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1445928 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1740049 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88499 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100965460 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 244137 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23363714 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16388828 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5434 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 53254 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 431 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17226 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250564 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 172705 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423269 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88055069 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22700407 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 963083 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1436206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1444549 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 56493 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100968085 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 243573 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23373120 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16387776 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5402 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48618 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 436 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 252218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 171298 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423516 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88057641 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22708636 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 974663 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9539042 # number of nop insts executed -system.cpu.iew.exec_refs 38540674 # number of memory reference insts executed -system.cpu.iew.exec_branches 15139519 # Number of branches executed -system.cpu.iew.exec_stores 15840267 # Number of stores executed -system.cpu.iew.exec_rate 2.036461 # Inst execution rate -system.cpu.iew.wb_sent 87694134 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87280456 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33430607 # num instructions producing a value -system.cpu.iew.wb_consumers 43860363 # num instructions consuming a value +system.cpu.iew.exec_nop 9531616 # number of nop insts executed +system.cpu.iew.exec_refs 38544729 # number of memory reference insts executed +system.cpu.iew.exec_branches 15136263 # Number of branches executed +system.cpu.iew.exec_stores 15836093 # Number of stores executed +system.cpu.iew.exec_rate 2.088349 # Inst execution rate +system.cpu.iew.wb_sent 87691296 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87276948 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33460873 # num instructions producing a value +system.cpu.iew.wb_consumers 43882648 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.018547 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762205 # average fanout of values written-back +system.cpu.iew.wb_rate 2.069834 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762508 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9526459 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9477917 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 368198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41408913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.133373 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.803824 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 366510 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40393190 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.187019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.818394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18342699 44.30% 44.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7125223 17.21% 61.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3513214 8.48% 69.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2087650 5.04% 75.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2070192 5.00% 80.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1179714 2.85% 82.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1132729 2.74% 85.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 709577 1.71% 87.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5247915 12.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17375613 43.02% 43.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7063647 17.49% 60.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3493568 8.65% 69.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2102678 5.21% 74.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2090838 5.18% 79.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1172557 2.90% 82.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1137405 2.82% 85.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 723784 1.79% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5233100 12.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41408913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40393190 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5247915 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5233100 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132710787 # The number of ROB reads -system.cpu.rob.rob_writes 197183581 # The number of ROB writes -system.cpu.timesIdled 23387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 384415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131661337 # The number of ROB reads +system.cpu.rob.rob_writes 197076783 # The number of ROB writes +system.cpu.timesIdled 11011 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 336765 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.543263 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.543263 # CPI: Total CPI of All Threads -system.cpu.ipc 1.840729 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.840729 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116590843 # number of integer regfile reads -system.cpu.int_regfile_writes 57851456 # number of integer regfile writes -system.cpu.fp_regfile_reads 250950 # number of floating regfile reads -system.cpu.fp_regfile_writes 240941 # number of floating regfile writes -system.cpu.misc_regfile_reads 38077 # number of misc regfile reads +system.cpu.cpi 0.529781 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.529781 # CPI: Total CPI of All Threads +system.cpu.ipc 1.887574 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.887574 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116593496 # number of integer regfile reads +system.cpu.int_regfile_writes 57858579 # number of integer regfile writes +system.cpu.fp_regfile_reads 252858 # number of floating regfile reads +system.cpu.fp_regfile_writes 241901 # number of floating regfile writes +system.cpu.misc_regfile_reads 38310 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92836 # number of replacements -system.cpu.icache.tagsinuse 1929.378925 # Cycle average of tags in use -system.cpu.icache.total_refs 14026889 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94884 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.831974 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18060721000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1929.378925 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942080 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942080 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14026889 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14026889 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14026889 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14026889 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14026889 # number of overall hits -system.cpu.icache.overall_hits::total 14026889 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99264 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99264 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99264 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99264 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99264 # number of overall misses -system.cpu.icache.overall_misses::total 99264 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1029034500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1029034500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1029034500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1029034500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1029034500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1029034500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14126153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14126153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14126153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007027 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007027 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10366.643496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10366.643496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10366.643496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10366.643496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10366.643496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10366.643496 # average overall miss latency +system.cpu.icache.replacements 94995 # number of replacements +system.cpu.icache.tagsinuse 1931.010955 # Cycle average of tags in use +system.cpu.icache.total_refs 14025954 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 97043 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 144.533392 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17649756000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1931.010955 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942876 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942876 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14025954 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14025954 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14025954 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14025954 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14025954 # number of overall hits +system.cpu.icache.overall_hits::total 14025954 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 100744 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 100744 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 100744 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 100744 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 100744 # number of overall misses +system.cpu.icache.overall_misses::total 100744 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 779635000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 779635000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 779635000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 779635000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 779635000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 779635000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14126698 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14126698 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14126698 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14126698 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14126698 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14126698 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007131 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007131 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007131 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007131 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007131 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007131 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7738.773525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7738.773525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7738.773525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7738.773525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +388,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4379 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4379 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4379 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4379 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4379 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637176500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 637176500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006717 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006717 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6715.250040 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6715.250040 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3700 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3700 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3700 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3700 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3700 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3700 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 97044 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 97044 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 97044 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 97044 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 97044 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 97044 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 497811000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 497811000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 497811000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 497811000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 497811000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 497811000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006870 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006870 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5129.745270 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5129.745270 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5129.745270 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5129.745270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5129.745270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5129.745270 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201660 # number of replacements -system.cpu.dcache.tagsinuse 4075.950117 # Cycle average of tags in use -system.cpu.dcache.total_refs 34352002 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205756 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.955044 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 168155000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4075.950117 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995105 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20774603 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20774603 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13577332 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13577332 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 67 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 67 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34351935 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34351935 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34351935 # number of overall hits -system.cpu.dcache.overall_hits::total 34351935 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 251586 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 251586 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1036045 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54515031500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21026189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21026189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201505 # number of replacements +system.cpu.dcache.tagsinuse 4076.313431 # Cycle average of tags in use +system.cpu.dcache.total_refs 34371357 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205601 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.175048 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 155296000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.313431 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995194 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995194 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20790228 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20790228 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13581056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13581056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 73 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 73 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34371284 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34371284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34371284 # number of overall hits +system.cpu.dcache.overall_hits::total 34371284 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 252353 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 252353 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1032321 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1032321 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1284674 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1284674 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1284674 # number of overall misses +system.cpu.dcache.overall_misses::total 1284674 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7773688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7773688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39504948500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39504948500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 47278637000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 47278637000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 47278637000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 47278637000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21042581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21042581 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35639566 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35639566 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35639566 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35639566 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011965 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011965 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070897 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070897 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33918.886584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33918.886584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44381.773475 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44381.773475 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42337.464305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42337.464305 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 96000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5647.058824 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 73 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 73 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35655958 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35655958 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35655958 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35655958 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011992 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011992 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070642 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070642 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036030 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036030 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036030 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036030 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30804.819043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30804.819043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38268.085702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38268.085702 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36802.050170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36802.050170 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 90500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6033.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166377 # number of writebacks -system.cpu.dcache.writebacks::total 166377 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189261 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 189261 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892614 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 892614 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1081875 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1081875 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1081875 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1081875 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62325 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62325 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143431 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143431 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205756 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1244348500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1244348500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521425000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521425000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6765773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6765773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6765773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6765773500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002964 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002964 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 166256 # number of writebacks +system.cpu.dcache.writebacks::total 166256 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 190181 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 190181 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 888892 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 888892 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1079073 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1079073 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1079073 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1079073 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62172 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62172 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143429 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143429 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205601 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205601 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205601 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205601 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1152797500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1152797500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5564302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5564302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6717099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6717099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6717099500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6717099500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002955 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002955 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005773 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005773 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005773 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005773 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19965.479342 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19965.479342 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38495.339222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38495.339222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32882.508894 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32882.508894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32882.508894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32882.508894 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005766 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005766 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18542.068777 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18542.068777 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38794.818342 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38794.818342 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32670.558509 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32670.558509 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32670.558509 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32670.558509 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 137206 # number of replacements -system.cpu.l2cache.tagsinuse 29113.613445 # Cycle average of tags in use -system.cpu.l2cache.total_refs 155241 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 168083 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.923597 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 137202 # number of replacements +system.cpu.l2cache.tagsinuse 29157.346540 # Cycle average of tags in use +system.cpu.l2cache.total_refs 157131 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 168078 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.934870 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25325.507446 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1911.510034 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1876.595965 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.772873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.058335 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.057269 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.888477 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 86140 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32424 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 118564 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 166377 # 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number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130969 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8745 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 160868 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 169613 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8745 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 160868 # number of overall misses -system.cpu.l2cache.overall_misses::total 169613 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 308885000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1032985000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1341870000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5046309500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5046309500 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913102 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.913102 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.781839 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.564171 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.781839 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.564171 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35321.326472 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34549.148801 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34723.889866 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38530.564485 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38530.564485 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35321.326472 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37790.576746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37663.265787 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35321.326472 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37790.576746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37663.265787 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 25380.921968 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1917.691461 # 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number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8743 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 160863 # number of overall misses +system.cpu.l2cache.overall_misses::total 169606 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 311485000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1056324500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1367809500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5399152500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5399152500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 311485000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6455477000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6766962000 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205601 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 302645 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 97044 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205601 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 302645 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.090093 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.480891 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.242692 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913094 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.913094 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.090093 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.782404 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.560412 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.090093 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.782404 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.560412 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.787144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35332.123624 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35398.796584 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41225.604355 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41225.604355 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 39898.128604 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 39898.128604 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3409.090909 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 116038 # number of writebacks -system.cpu.l2cache.writebacks::total 116038 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8745 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29899 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 38644 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130969 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130969 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8745 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 169613 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8745 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160868 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169613 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 281196000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941994500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223190500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4649150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4649150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281196000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5591145000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5872341000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281196000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5591145000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5872341000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.479743 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.245814 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913102 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913102 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.564171 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.564171 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32155.060034 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31505.886484 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31652.792154 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35498.098787 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35498.098787 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 116036 # number of writebacks +system.cpu.l2cache.writebacks::total 116036 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8743 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29897 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38640 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130966 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130966 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8743 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169606 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8743 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160863 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169606 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 283805000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 965325500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1249130500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4998997500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4998997500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283805000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5964323000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6248128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283805000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5964323000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6248128000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480891 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.242692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782404 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.560412 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782404 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.560412 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32460.825803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32288.373415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32327.393892 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38170.193027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38170.193027 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32460.825803 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37077.034495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36839.074089 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32460.825803 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37077.034495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36839.074089 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 5c01fa696..456c7f9d2 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134581 # Number of seconds simulated -sim_ticks 134581343000 # Number of ticks simulated -final_tick 134581343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133756 # Number of seconds simulated +sim_ticks 133756135000 # Number of ticks simulated +final_tick 133756135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1566292 # Simulator instruction rate (inst/s) -host_op_rate 1566291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2386143258 # Simulator tick rate (ticks/s) -host_mem_usage 226128 # Number of bytes of host memory used -host_seconds 56.40 # Real time elapsed on the host +host_inst_rate 1270571 # Simulator instruction rate (inst/s) +host_op_rate 1270570 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923763163 # Simulator tick rate (ticks/s) +host_mem_usage 227600 # Number of bytes of host memory used +host_seconds 69.53 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160477 # Nu system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3606087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76314649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79920736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3606087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3606087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55142264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55142264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55142264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3606087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76314649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 135063001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3628335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76785472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 80413807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3628335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3628335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55482464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55482464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55482464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3628335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76785472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 135896271 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 269162686 # number of cpu cycles simulated +system.cpu.numCycles 267512270 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 269162686 # Number of busy cycles +system.cpu.num_busy_cycles 267512270 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.699205 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.674409 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.699205 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913916 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913916 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.674409 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913904 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913904 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1390813000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1390813000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1390813000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1390813000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1390813000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1390813000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312229000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1312229000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1312229000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1312229000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1312229000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1312229000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18195.784709 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18195.784709 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18195.784709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18195.784709 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17167.682767 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17167.682767 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17167.682767 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17167.682767 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1161505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1161505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1161505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1161505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1161505000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1161505000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159357000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1159357000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159357000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1159357000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159357000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1159357000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15195.784709 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15195.784709 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15167.682767 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15167.682767 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.801621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.879185 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 947396000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.801621 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995801 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995801 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.879185 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995820 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995820 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2092728000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2092728000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513894000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7513894000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9606622000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9606622000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9606622000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9606622000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2026896000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2026896000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7369702000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7369702000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9396598000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9396598000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9396598000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9396598000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34439.127143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34439.127143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52333.184750 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52333.184750 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47012.009161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47012.009161 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33355.758154 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33355.758154 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51328.908329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51328.908329 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45984.212896 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45984.212896 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910430000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910430000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7083160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7083160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8993590000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8993590000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8993590000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8993590000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905364000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905364000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082546000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082546000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987910000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987910000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8987910000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31439.127143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31439.127143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49333.184750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49333.184750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31355.758154 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31355.758154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.908329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.908329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 135625 # number of replacements -system.cpu.l2cache.tagsinuse 29002.571879 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29005.267541 # Cycle average of tags in use system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25772.303239 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1646.708734 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1583.559905 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.786508 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050254 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.048326 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.885088 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 25782.627688 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1648.153103 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1574.486750 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.786823 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.050298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.048050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.885171 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 68853 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31317 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 100170 # number of ReadReq hits @@ -304,17 +304,17 @@ system.cpu.l2cache.demand_misses::total 168060 # nu system.cpu.l2cache.overall_misses::cpu.inst 7583 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 160477 # number of overall misses system.cpu.l2cache.overall_misses::total 168060 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531348000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1925664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813456000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6813456000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 394316000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8344804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8739120000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 394316000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8344804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8739120000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394391000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531428000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1925819000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813468000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6813468000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 394391000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8344896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8739287000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 394391000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8344896000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8739287000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) @@ -339,17 +339,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.598547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099207 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.785328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.598547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.890545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.716561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.185569 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.091583 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.091583 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.993693 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.993693 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,17 +371,17 @@ system.cpu.l2cache.demand_mshr_misses::total 168060 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 160477 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 168060 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1177960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6722400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6722400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303395000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1178040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481435000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241132000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241132000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303395000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419172000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6722567000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303395000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419172000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6722567000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.484630 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269909 # mshr miss rate for ReadReq accesses @@ -393,17 +393,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.598547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.598547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.890545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.716561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40004.185569 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.091583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.091583 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index fdf8f5a60..3a7d388e3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024261 # Number of seconds simulated -sim_ticks 24260940500 # Number of ticks simulated -final_tick 24260940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023747 # Number of seconds simulated +sim_ticks 23747395500 # Number of ticks simulated +final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115016 # Simulator instruction rate (inst/s) -host_op_rate 163211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39343372 # Simulator tick rate (ticks/s) -host_mem_usage 237732 # Number of bytes of host memory used -host_seconds 616.65 # Real time elapsed on the host -sim_insts 70924159 # Number of instructions simulated -sim_ops 100643406 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 327680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory -system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 327680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 327680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417600 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84650 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84650 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13506484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330903577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 344410061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13506484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13506484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 223305440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 223305440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 223305440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13506484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330903577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 567715501 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 107822 # Simulator instruction rate (inst/s) +host_op_rate 153002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36101670 # Simulator tick rate (ticks/s) +host_mem_usage 242616 # Number of bytes of host memory used +host_seconds 657.79 # Real time elapsed on the host +sim_insts 70924309 # Number of instructions simulated +sim_ops 100643556 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8028992 # Number of bytes read from this memory +system.physmem.bytes_read::total 8354880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 325888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 325888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417728 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417728 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5092 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125453 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130545 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84652 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84652 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13723105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 338099898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 351823003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13723105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13723105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 228139882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 228139882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 228139882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13723105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 338099898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 579962885 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48521882 # number of cpu cycles simulated +system.cpu.numCycles 47494792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16966170 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12979168 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 675165 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11674119 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7996673 # Number of BTB hits +system.cpu.BPredUnit.lookups 16945853 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12976600 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 671047 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11791616 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7980415 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1849293 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114426 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12701255 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 86893403 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16966170 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9845966 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21627617 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2635386 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10974011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 407 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 11950097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 196542 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47237958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.329156 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1850372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114214 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12555295 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 86800259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16945853 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9830787 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21603869 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2612787 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10088905 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 11920379 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 192164 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46165707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.632126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.343505 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25631712 54.26% 54.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2165185 4.58% 58.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027432 4.29% 63.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2093511 4.43% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1492717 3.16% 70.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1413949 2.99% 73.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 984209 2.08% 75.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1226744 2.60% 78.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10202499 21.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24583523 53.25% 53.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2172032 4.70% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2013449 4.36% 62.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2091121 4.53% 66.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1494392 3.24% 70.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1411801 3.06% 73.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 982905 2.13% 75.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1224192 2.65% 77.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10192292 22.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47237958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.349660 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.790809 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14870883 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9280138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19842641 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1415670 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1828626 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3426061 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108157 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118947297 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 370581 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1828626 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16604946 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2957626 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 761420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19440844 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5644496 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116783060 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12596 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4803591 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 254 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117118920 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 537771429 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537766148 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5281 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17959800 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25743 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25726 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13145883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29944086 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22669898 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3682577 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4376453 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112886356 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41706 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108196580 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 320650 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12119727 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28466628 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4614 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47237958 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.991605 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46165707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.356794 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.827574 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14647959 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8470510 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19858799 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1377235 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1811204 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3409264 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108749 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118806925 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 370081 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1811204 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16375618 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2381141 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 742521 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19461585 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5393638 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116666793 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9401 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4563999 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 255 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117035573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 537232740 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537225721 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7019 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159360 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17876213 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25291 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25289 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12820996 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29922759 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22636012 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3511140 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4209388 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112770529 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108119060 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 319934 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12017924 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28288746 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4343 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46165707 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.341978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.993843 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11517306 24.38% 24.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8382479 17.75% 42.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7488515 15.85% 57.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7167095 15.17% 73.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5452995 11.54% 84.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3887775 8.23% 92.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1886175 3.99% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 877063 1.86% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578555 1.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10763393 23.31% 23.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8065577 17.47% 40.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7395154 16.02% 56.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7189034 15.57% 72.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5495666 11.90% 84.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3896907 8.44% 92.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1882413 4.08% 96.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 886108 1.92% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 591455 1.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47237958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46165707 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 110786 4.40% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1390381 55.25% 59.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1015261 40.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111137 4.37% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1401194 55.04% 59.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1033519 40.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57217754 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91589 0.08% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 191 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29118364 26.91% 79.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21768675 20.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57171551 52.88% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91476 0.08% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 254 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29115621 26.93% 79.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21740151 20.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108196580 # Type of FU issued -system.cpu.iq.rate 2.229851 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2516428 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023258 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266467665 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125074926 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106294504 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 794 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110712739 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 269 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2177452 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108119060 # Type of FU issued +system.cpu.iq.rate 2.276440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2545850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023547 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 265268953 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124855497 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106214423 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 658 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1042 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110664579 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 331 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2183386 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2633672 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7610 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29131 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2110854 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2612315 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 27815 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2076938 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1828626 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 932107 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 39617 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112937916 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 341621 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29944086 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22669898 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25185 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2553 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3723 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29131 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 450221 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 202626 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 652847 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107016957 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28768203 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1179623 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1811204 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 969930 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37593 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112821828 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 344750 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29922759 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22636012 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24938 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1077 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4742 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27815 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 448633 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 200270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 648903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106941825 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28766464 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1177235 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9854 # number of nop insts executed -system.cpu.iew.exec_refs 50224831 # number of memory reference insts executed -system.cpu.iew.exec_branches 14719282 # Number of branches executed -system.cpu.iew.exec_stores 21456628 # Number of stores executed -system.cpu.iew.exec_rate 2.205540 # Inst execution rate -system.cpu.iew.wb_sent 106535697 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106294668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53446146 # num instructions producing a value -system.cpu.iew.wb_consumers 103592779 # num instructions consuming a value +system.cpu.iew.exec_nop 9834 # number of nop insts executed +system.cpu.iew.exec_refs 50197967 # number of memory reference insts executed +system.cpu.iew.exec_branches 14707935 # Number of branches executed +system.cpu.iew.exec_stores 21431503 # Number of stores executed +system.cpu.iew.exec_rate 2.251654 # Inst execution rate +system.cpu.iew.wb_sent 106459563 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106214621 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53551409 # num instructions producing a value +system.cpu.iew.wb_consumers 103987749 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.190654 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.515925 # average fanout of values written-back +system.cpu.iew.wb_rate 2.236342 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514978 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12289679 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569161 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45409333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.216482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.738259 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12173182 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37122 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 565028 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44354504 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.269197 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.754788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15949772 35.12% 35.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11950425 26.32% 61.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3594230 7.92% 69.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2920439 6.43% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880725 4.14% 79.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1913412 4.21% 84.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 683428 1.51% 85.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 576988 1.27% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5939914 13.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15099779 34.04% 34.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11755524 26.50% 60.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3528202 7.95% 68.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2907503 6.56% 75.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1884478 4.25% 79.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1967896 4.44% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685684 1.55% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580329 1.31% 86.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5945109 13.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45409333 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929711 # Number of instructions committed -system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44354504 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929861 # Number of instructions committed +system.cpu.commit.committedOps 100649108 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869458 # Number of memory references committed -system.cpu.commit.loads 27310414 # Number of loads committed +system.cpu.commit.refs 47869518 # Number of memory references committed +system.cpu.commit.loads 27310444 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744811 # Number of branches committed +system.cpu.commit.branches 13744841 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486123 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5939914 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5945109 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 152382757 # The number of ROB reads -system.cpu.rob.rob_writes 227716793 # The number of ROB writes -system.cpu.timesIdled 52521 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1283924 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924159 # Number of Instructions Simulated -system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated -system.cpu.cpi 0.684138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.684138 # CPI: Total CPI of All Threads -system.cpu.ipc 1.461694 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.461694 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515060291 # number of integer regfile reads -system.cpu.int_regfile_writes 104149739 # number of integer regfile writes -system.cpu.fp_regfile_reads 734 # number of floating regfile reads -system.cpu.fp_regfile_writes 618 # number of floating regfile writes -system.cpu.misc_regfile_reads 145340198 # number of misc regfile reads -system.cpu.misc_regfile_writes 38452 # number of misc regfile writes -system.cpu.icache.replacements 30556 # number of replacements -system.cpu.icache.tagsinuse 1813.467317 # Cycle average of tags in use -system.cpu.icache.total_refs 11916104 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32594 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 365.591949 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 151206386 # The number of ROB reads +system.cpu.rob.rob_writes 227466743 # The number of ROB writes +system.cpu.timesIdled 61795 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1329085 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924309 # Number of Instructions Simulated +system.cpu.committedOps 100643556 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924309 # Number of Instructions Simulated +system.cpu.cpi 0.669655 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669655 # CPI: Total CPI of All Threads +system.cpu.ipc 1.493307 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.493307 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 514746035 # number of integer regfile reads +system.cpu.int_regfile_writes 104090442 # number of integer regfile writes +system.cpu.fp_regfile_reads 1004 # number of floating regfile reads +system.cpu.fp_regfile_writes 868 # number of floating regfile writes +system.cpu.misc_regfile_reads 145207051 # number of misc regfile reads +system.cpu.misc_regfile_writes 38512 # number of misc regfile writes +system.cpu.icache.replacements 28686 # number of replacements +system.cpu.icache.tagsinuse 1815.800680 # Cycle average of tags in use +system.cpu.icache.total_refs 11888473 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30726 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 386.918994 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1813.467317 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885482 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885482 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11916104 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11916104 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11916104 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11916104 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11916104 # number of overall hits -system.cpu.icache.overall_hits::total 11916104 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33993 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33993 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33993 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33993 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33993 # number of overall misses -system.cpu.icache.overall_misses::total 33993 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409410000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409410000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409410000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409410000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409410000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409410000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11950097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11950097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11950097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11950097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11950097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11950097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002845 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002845 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002845 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002845 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002845 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002845 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12043.950225 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12043.950225 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12043.950225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12043.950225 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1815.800680 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.886621 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.886621 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11888474 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11888474 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11888474 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11888474 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11888474 # number of overall hits +system.cpu.icache.overall_hits::total 11888474 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31905 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31905 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31905 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31905 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31905 # number of overall misses +system.cpu.icache.overall_misses::total 31905 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328897000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328897000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328897000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328897000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328897000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328897000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11920379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11920379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11920379 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11920379 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11920379 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11920379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002677 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002677 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002677 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002677 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002677 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002677 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10308.635010 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10308.635010 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10308.635010 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10308.635010 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1348 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1348 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1348 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1348 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1348 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1348 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32645 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32645 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32645 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32645 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32645 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32645 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 275574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 275574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275574000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 275574000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002732 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002732 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002732 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8441.537755 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8441.537755 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8441.537755 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8441.537755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8441.537755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8441.537755 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1159 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1159 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1159 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30746 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 30746 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 30746 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 30746 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 30746 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 30746 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238224500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 238224500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238224500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 238224500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238224500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 238224500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002579 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002579 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002579 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7748.146100 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7748.146100 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7748.146100 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7748.146100 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158553 # number of replacements -system.cpu.dcache.tagsinuse 4072.119478 # Cycle average of tags in use -system.cpu.dcache.total_refs 44571992 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162649 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.037910 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 270825000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.119478 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994170 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994170 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26246711 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26246711 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18285374 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18285374 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20492 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20492 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44532085 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44532085 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2591609000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63424341000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63424341000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 645500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 645500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 66015950000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 66015950000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 66015950000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 66015950000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26353893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26353893 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19255 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19255 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44525902 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44525902 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44525902 # number of overall hits +system.cpu.dcache.overall_hits::total 44525902 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 105303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 105303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1564883 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1564883 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670186 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670186 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670186 # number of overall misses +system.cpu.dcache.overall_misses::total 1670186 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2142178000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2142178000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 54165146000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 54165146000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 358500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 56307324000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56307324000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56307324000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56307324000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26346187 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26346187 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20537 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20537 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46203794 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46203794 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46203794 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46203794 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004067 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078818 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078818 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002191 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002191 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036181 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036181 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036181 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036181 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24179.517083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24179.517083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40538.987822 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40538.987822 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14344.444444 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14344.444444 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39490.096662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39490.096662 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20497 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20497 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19255 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19255 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46196088 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46196088 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46196088 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46196088 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078836 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078836 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036154 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036154 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036154 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036154 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20342.991178 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20342.991178 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34612.904607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34612.904607 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8535.714286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8535.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33713.205595 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 209500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 197000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19045.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19700 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128129 # number of writebacks -system.cpu.dcache.writebacks::total 128129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51511 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51511 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457497 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1457497 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1509008 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1509008 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1509008 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1509008 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55671 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55671 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162701 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162701 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162701 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162701 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 988702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3843974500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3843974500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4832676500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4832676500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4832676500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4832676500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17759.731278 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17759.731278 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320094 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.692308 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.692308 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.668712 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.668712 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32058.789062 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32795.415225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32661.862606 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31361.111111 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31361.111111 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31732.872026 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31732.872026 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 84652 # number of writebacks +system.cpu.l2cache.writebacks::total 84652 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 36 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 100 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5092 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23138 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 28230 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102315 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102315 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5092 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130545 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5092 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125453 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130545 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164482000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 778171500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 942653500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 567000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 567000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3395437000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3395437000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164482000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4173608500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4338090500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164482000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4173608500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4338090500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416473 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.327187 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955983 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955983 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.675325 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.675325 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32302.042419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33631.752960 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33391.905774 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33186.111518 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33186.111518 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index c163d61b7..88647a82b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133513 # Number of seconds simulated -sim_ticks 133513136000 # Number of ticks simulated -final_tick 133513136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132746 # Number of seconds simulated +sim_ticks 132746076000 # Number of ticks simulated +final_tick 132746076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 903503 # Simulator instruction rate (inst/s) -host_op_rate 1281191 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1714129830 # Simulator tick rate (ticks/s) -host_mem_usage 235208 # Number of bytes of host memory used -host_seconds 77.89 # Real time elapsed on the host +host_inst_rate 594787 # Simulator instruction rate (inst/s) +host_op_rate 843423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1121948184 # Simulator tick rate (ticks/s) +host_mem_usage 240564 # Number of bytes of host memory used +host_seconds 118.32 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 125054 # Nu system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2050195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59945083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61995278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2050195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2050195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40470864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40470864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40470864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2050195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59945083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102466142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2062042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60291470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62353512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2062042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2062042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40704721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40704721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40704721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2062042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60291470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 103058233 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 267026272 # number of cpu cycles simulated +system.cpu.numCycles 265492152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267026272 # Number of busy cycles +system.cpu.num_busy_cycles 265492152 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1735.470121 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1736.430287 # Cycle average of tags in use system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1735.470121 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847398 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847398 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1736.430287 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847866 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847866 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 445311000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 445311000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 445311000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 445311000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 445311000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 445311000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 425522000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 425522000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 425522000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 425522000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 425522000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 425522000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23551.459700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23551.459700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23551.459700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23551.459700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22504.865665 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22504.865665 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22504.865665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22504.865665 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 388587000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 388587000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 388587000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 388587000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 388587000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 388587000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387706000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 387706000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387706000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 387706000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387706000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 387706000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20551.459700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20551.459700 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20504.865665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20504.865665 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.664624 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.962537 # Cycle average of tags in use system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1111220000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.664624 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.962537 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995352 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995352 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1699159000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1699159000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5797120000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5797120000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7496279000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7496279000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7496279000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7496279000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1642566000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1642566000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689754000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689754000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7332320000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7332320000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7332320000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7332320000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32080.183514 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32080.183514 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54162.493460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54162.493460 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46852.329404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46852.329404 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31011.705622 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31011.705622 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53159.372898 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53159.372898 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45827.572845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45827.572845 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1540261000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1540261000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5476024000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5476024000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7016285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7016285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7016285000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7016285000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536634000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536634000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475690000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475690000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012324000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7012324000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012324000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7012324000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.183514 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29080.183514 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51162.493460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51162.493460 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29011.705622 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29011.705622 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.372898 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.372898 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 96735 # number of replacements -system.cpu.l2cache.tagsinuse 28857.116422 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 28875.776749 # Cycle average of tags in use system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26427.849240 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 949.438432 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1479.828749 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.806514 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.028975 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.880649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 26451.163706 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 950.000997 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1474.612046 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.807225 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.028992 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.045002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.881219 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 129331 # nu system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses system.cpu.l2cache.overall_misses::total 129331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222404000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181076000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1403480000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321732000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5321732000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 222404000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6502808000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6725212000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 222404000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6502808000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6725212000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222488000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1403626000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321748000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5321748000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 222488000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6502886000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6725374000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 222488000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6502886000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6725374000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.722899 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52019.639935 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.729714 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.409411 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.156340 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.156340 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.252600 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.252600 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 129331 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5173240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5173240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171164000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908582000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079746000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093656000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093656000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171164000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002238000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5173402000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171164000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002238000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5173402000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40019.639935 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.729714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.409411 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.156340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.156340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index fbfcfb090..1d85fdbdf 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.204097 # Number of seconds simulated -sim_ticks 204097178000 # Number of ticks simulated -final_tick 204097178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202343 # Number of seconds simulated +sim_ticks 202342809000 # Number of ticks simulated +final_tick 202342809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1441199 # Simulator instruction rate (inst/s) -host_op_rate 1459859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2188591939 # Simulator tick rate (ticks/s) -host_mem_usage 238748 # Number of bytes of host memory used -host_seconds 93.26 # Real time elapsed on the host +host_inst_rate 1232815 # Simulator instruction rate (inst/s) +host_op_rate 1248778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1856050290 # Simulator tick rate (ticks/s) +host_mem_usage 230736 # Number of bytes of host memory used +host_seconds 109.02 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 123533 # Nu system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3261505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38736998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41998503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3261505 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3261505 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25974764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25974764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25974764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3261505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38736998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67973267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3289783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39072859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 42362642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3289783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3289783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26199972 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26199972 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26199972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3289783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39072859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68562614 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 408194356 # number of cpu cycles simulated +system.cpu.numCycles 404685618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 408194356 # Number of busy cycles +system.cpu.num_busy_cycles 404685618 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.409949 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.814192 # Cycle average of tags in use system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 145330286000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.409949 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978716 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978716 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 144074079000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.814192 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978913 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3060544000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3060544000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3060544000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3060544000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3060544000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3060544000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2868177000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2868177000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2868177000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2868177000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2868177000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2868177000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16364.445205 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16364.445205 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16364.445205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16364.445205 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15335.876679 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15335.876679 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15335.876679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15335.876679 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2499472000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2499472000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2499472000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2499472000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2499472000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2499472000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494129000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2494129000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494129000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2494129000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494129000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2494129000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13364.445205 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13364.445205 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.876679 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.876679 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.413116 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.652500 # Cycle average of tags in use system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 812030000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.413116 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997904 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.652500 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997962 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1571682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1571682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5728295000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5728295000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 430000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 430000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7299977000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7299977000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7299977000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7299977000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1523847000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1523847000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5622992000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5622992000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7146839000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7146839000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7146839000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7146839000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34543.220730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34543.220730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54470.113347 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54470.113347 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28666.666667 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 28666.666667 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48452.353929 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48452.353929 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33491.878942 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33491.878942 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53468.791602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53468.791602 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47435.926538 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47435.926538 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1435185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1435185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412803000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412803000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 385000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 385000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6847988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6847988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6847988000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6847988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432849000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432849000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845513000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6845513000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845513000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6845513000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31543.220730 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31543.220730 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51470.113347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51470.113347 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25666.666667 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25666.666667 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31491.878942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31491.878942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 101560 # number of replacements -system.cpu.l2cache.tagsinuse 29278.942435 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29290.996090 # Cycle average of tags in use system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 24760.228137 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3263.271559 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1255.442739 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.755622 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.099587 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.038313 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893522 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 24775.786415 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3266.546663 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1248.663012 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.756097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.099687 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.038106 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.893890 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits @@ -292,17 +292,17 @@ system.cpu.l2cache.demand_misses::total 133934 # nu system.cpu.l2cache.overall_misses::cpu.inst 10401 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123533 # number of overall misses system.cpu.l2cache.overall_misses::total 133934 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540852000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154296000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1695148000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540875000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154340000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1695215000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5269420000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5269420000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 540852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6423716000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6964568000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 540852000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6423716000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6964568000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 540875000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6423760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6964635000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 540875000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6423760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6964635000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) @@ -327,17 +327,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.396604 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.055613 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.819848 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.396604 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.211326 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.982161 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.055278 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.500246 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.500246 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,17 +359,17 @@ system.cpu.l2cache.demand_mshr_misses::total 133934 system.cpu.l2cache.overall_mshr_misses::cpu.inst 10401 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 133934 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1303960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416063000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887964000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1304027000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4053400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4053400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5357360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5357360000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416063000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941364000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5357427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416063000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941364000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5357427000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.487879 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.140197 # mshr miss rate for ReadReq accesses @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.396604 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.396604 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.211326 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.982161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.055278 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 0d873282b..9df6e0f0a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.996063 # Number of seconds simulated -sim_ticks 996062814500 # Number of ticks simulated -final_tick 996062814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.983203 # Number of seconds simulated +sim_ticks 983202553500 # Number of ticks simulated +final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142352 # Simulator instruction rate (inst/s) -host_op_rate 142352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77916645 # Simulator tick rate (ticks/s) -host_mem_usage 219096 # Number of bytes of host memory used -host_seconds 12783.70 # Real time elapsed on the host +host_inst_rate 94547 # Simulator instruction rate (inst/s) +host_op_rate 94547 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51082649 # Simulator tick rate (ticks/s) +host_mem_usage 219392 # Number of bytes of host memory used +host_seconds 19247.29 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579648 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137579776 # Number of bytes read from this memory +system.physmem.bytes_read::total 137634752 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105024 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149682 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138123466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138178659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67370273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67370273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67370273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138123466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205548932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149684 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150543 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139930247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139986162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 68251540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 68251540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 68251540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139930247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 208237702 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444620890 # DTB read hits +system.cpu.dtb.read_hits 444615529 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449517968 # DTB read accesses -system.cpu.dtb.write_hits 160920434 # DTB write hits +system.cpu.dtb.read_accesses 449512607 # DTB read accesses +system.cpu.dtb.write_hits 160920414 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162621738 # DTB write accesses -system.cpu.dtb.data_hits 605541324 # DTB hits +system.cpu.dtb.write_accesses 162621718 # DTB write accesses +system.cpu.dtb.data_hits 605535943 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612139706 # DTB accesses -system.cpu.itb.fetch_hits 232151959 # ITB hits +system.cpu.dtb.data_accesses 612134325 # DTB accesses +system.cpu.itb.fetch_hits 232170189 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232151981 # ITB accesses +system.cpu.itb.fetch_accesses 232170211 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1992125630 # number of cpu cycles simulated +system.cpu.numCycles 1966405108 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253784019 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 139998376 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232594122 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138120343 # Number of BTB hits +system.cpu.branch_predictor.lookups 328916467 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253806684 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140065896 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232656738 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138122512 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669698372 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.367510 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175157469 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153758998 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669786412 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045900989 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045989029 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651085046 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617993265 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121277812 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139625100 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 650997764 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989099 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121287494 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12179944 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133467438 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81732764 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.020127 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139628962 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1749884347 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746556255 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7972692 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415154081 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576971549 # Number of cycles cpu stages are processed. -system.cpu.activity 79.160246 # Percentage of cycles cpu is active +system.cpu.timesIdled 7516835 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 389335212 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1577069896 # Number of cycles cpu stages are processed. +system.cpu.activity 80.200661 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.094707 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.080573 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.094707 # CPI: Total CPI of All Threads -system.cpu.ipc 0.913487 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.080573 # CPI: Total CPI of All Threads +system.cpu.ipc 0.925435 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.913487 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 801360547 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190765083 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.773594 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1059717687 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932407943 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.804676 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1018191600 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.889187 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1582470698 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.563710 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 969332524 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022793106 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.341797 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.925435 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 775560339 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190844769 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.559483 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1034052370 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932352738 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.414072 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 992429233 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973975875 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.530784 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1556696076 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409709032 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.835434 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 943449824 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022955284 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.021594 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.783134 # Cycle average of tags in use -system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.559426 # Cycle average of tags in use +system.cpu.icache.total_refs 232169108 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270278.356228 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.783134 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232150871 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232150871 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232150871 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232150871 # number of overall hits -system.cpu.icache.overall_hits::total 232150871 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1085 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1085 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1085 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1085 # number of overall misses -system.cpu.icache.overall_misses::total 1085 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60468000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60468000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60468000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60468000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60468000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60468000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232151956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232151956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232151956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232151956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232151956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232151956 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.559426 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325468 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325468 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232169108 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232169108 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232169108 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232169108 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232169108 # number of overall hits +system.cpu.icache.overall_hits::total 232169108 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1077 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1077 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1077 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1077 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1077 # number of overall misses +system.cpu.icache.overall_misses::total 1077 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58736500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58736500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58736500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58736500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58736500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58736500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232170185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232170185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232170185 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232170185 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232170185 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232170185 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55730.875576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55730.875576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55730.875576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55730.875576 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54537.140204 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54537.140204 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54537.140204 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 114500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 22900 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 218 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 218 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47379000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47379000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47379000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47379000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47379000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47379000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47121000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47121000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47121000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47121000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47121000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47121000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55155.995343 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55155.995343 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54855.646100 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54855.646100 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107311 # number of replacements -system.cpu.dcache.tagsinuse 4082.354222 # Cycle average of tags in use -system.cpu.dcache.total_refs 595073825 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111407 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310860 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.354222 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157802392 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157802392 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595073825 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595073825 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595073825 # number of overall hits -system.cpu.dcache.overall_hits::total 595073825 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324230 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324230 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2926110 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2926110 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10250340 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10250340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10250340 # number of overall misses -system.cpu.dcache.overall_misses::total 10250340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 166497124500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 166497124500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 130098294500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 130098294500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296595419000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296595419000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296595419000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296595419000 # number of overall miss cycles +system.cpu.dcache.replacements 9107371 # number of replacements +system.cpu.dcache.tagsinuse 4082.143149 # Cycle average of tags in use +system.cpu.dcache.total_refs 595063275 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.309272 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12675157000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.143149 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996617 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996617 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157791841 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157791841 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595063275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595063275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595063275 # number of overall hits +system.cpu.dcache.overall_hits::total 595063275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2936661 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2936661 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10260890 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10260890 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10260890 # number of overall misses +system.cpu.dcache.overall_misses::total 10260890 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 153812326500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 153812326500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 102755788500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 102755788500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 256568115000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 256568115000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 256568115000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 256568115000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018205 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018205 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.372481 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.372481 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44461.176955 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44461.176955 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28935.178638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28935.178638 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78626000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8150818500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14909 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5273.727279 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39101.656496 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21000.480255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21000.480255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34990.687893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34990.687893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389635 # number of writebacks -system.cpu.dcache.writebacks::total 3389635 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036985 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1036985 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1138933 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1138933 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1138933 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1138933 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889125 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111407 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111407 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111407 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111407 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938792000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938792000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71755618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71755618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212694410500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212694410500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212694410500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212694410500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks +system.cpu.dcache.writebacks::total 3389692 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101949 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101949 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047474 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1047474 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1149423 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1149423 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1149423 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1149423 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889187 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889187 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111467 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111467 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111467 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111467 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137359214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137359214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55152222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 55152222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192511436500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 192511436500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192511436500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 192511436500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,149 +318,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.440450 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.440450 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37983.520678 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37983.520678 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.815942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.815942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29193.628000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29193.628000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133758 # number of replacements -system.cpu.l2cache.tagsinuse 30551.128505 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448354 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 30529.573479 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8448408 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905040 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 184403463000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14423.846214 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.322158 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16092.960133 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860989 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389635 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389635 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6961725 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961725 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6961725 # number of overall hits -system.cpu.l2cache.overall_hits::total 6961725 # number of overall hits +system.cpu.l2cache.avg_refs 3.905065 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 182812071500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14439.033310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.753993 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16055.786176 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440644 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001061 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.489984 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.931689 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389692 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389692 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100796 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100796 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6961783 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6961783 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6961783 # number of overall hits +system.cpu.l2cache.overall_hits::total 6961783 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1361711 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 788830 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 788830 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1360851 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1361710 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32423383500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35788000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87234710500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87270498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35788000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87234710500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87270498500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40255.827232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40256.648437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41156.282723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41156.282723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41662.398137 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40277.243431 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40278.117220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41102.975535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41102.975535 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 693f470b9..b5afab091 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.621337 # Number of seconds simulated -sim_ticks 621337354500 # Number of ticks simulated -final_tick 621337354500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.601884 # Number of seconds simulated +sim_ticks 601884201500 # Number of ticks simulated +final_tick 601884201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185902 # Simulator instruction rate (inst/s) -host_op_rate 185902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66535120 # Simulator tick rate (ticks/s) -host_mem_usage 220128 # Number of bytes of host memory used -host_seconds 9338.49 # Real time elapsed on the host +host_inst_rate 130981 # Simulator instruction rate (inst/s) +host_op_rate 130981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45411041 # Simulator tick rate (ticks/s) +host_mem_usage 220420 # Number of bytes of host memory used +host_seconds 13254.14 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138182080 # Number of bytes read from this memory -system.physmem.bytes_read::total 138244288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67208384 # Number of bytes written to this memory -system.physmem.bytes_written::total 67208384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2159095 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2160067 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050131 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050131 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 100120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 222394612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 222494732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100120 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100120 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 108167300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 108167300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 108167300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 222394612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 330662032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138169152 # Number of bytes read from this memory +system.physmem.bytes_read::total 138230976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67208000 # Number of bytes written to this memory +system.physmem.bytes_written::total 67208000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158893 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159859 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050125 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050125 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 229561021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 229663739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 111662675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 111662675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 111662675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 229561021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 341326414 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 614254083 # DTB read hits -system.cpu.dtb.read_misses 10995703 # DTB read misses +system.cpu.dtb.read_hits 610881152 # DTB read hits +system.cpu.dtb.read_misses 10794363 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625249786 # DTB read accesses -system.cpu.dtb.write_hits 208699163 # DTB write hits -system.cpu.dtb.write_misses 6860235 # DTB write misses +system.cpu.dtb.read_accesses 621675515 # DTB read accesses +system.cpu.dtb.write_hits 207421516 # DTB write hits +system.cpu.dtb.write_misses 6613595 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 215559398 # DTB write accesses -system.cpu.dtb.data_hits 822953246 # DTB hits -system.cpu.dtb.data_misses 17855938 # DTB misses +system.cpu.dtb.write_accesses 214035111 # DTB write accesses +system.cpu.dtb.data_hits 818302668 # DTB hits +system.cpu.dtb.data_misses 17407958 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 840809184 # DTB accesses -system.cpu.itb.fetch_hits 402673269 # ITB hits -system.cpu.itb.fetch_misses 61 # ITB misses +system.cpu.dtb.data_accesses 835710626 # DTB accesses +system.cpu.itb.fetch_hits 399285601 # ITB hits +system.cpu.itb.fetch_misses 63 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402673330 # ITB accesses +system.cpu.itb.fetch_accesses 399285664 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1242674710 # number of cpu cycles simulated +system.cpu.numCycles 1203768404 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 383387811 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 295251517 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19004234 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 268604084 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 264111879 # Number of BTB hits +system.cpu.BPredUnit.lookups 378661928 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 290874773 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18850616 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 264881962 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 260540807 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25192938 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6291 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 414146940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3172273422 # Number of instructions fetch has processed -system.cpu.fetch.Branches 383387811 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 289304817 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 579090604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 137696439 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133107618 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1380 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402673269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10484478 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1238186640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.562032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158458 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25136701 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6159 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410735894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3138932224 # Number of instructions fetch has processed +system.cpu.fetch.Branches 378661928 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 285677508 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 572729793 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 132567804 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 108566970 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 399285601 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10259418 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1199047347 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.617855 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.169243 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 659096036 53.23% 53.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43594264 3.52% 56.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22394894 1.81% 58.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41029945 3.31% 61.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127979061 10.34% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63938505 5.16% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40814246 3.30% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30412222 2.46% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 208927467 16.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 626317554 52.23% 52.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42572057 3.55% 55.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22209930 1.85% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40806426 3.40% 61.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 126340363 10.54% 71.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63640386 5.31% 76.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40565082 3.38% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30197237 2.52% 82.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 206398312 17.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1238186640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308518 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.552779 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 444874368 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117661314 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 546409633 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17402131 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 111839194 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60535765 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 960 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3092199728 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2107 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 111839194 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 466426212 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65454708 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5539 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540814331 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53646656 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3009948527 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 590628 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2809331 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 47992017 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2251177447 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3888711604 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3887318453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1393151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1199047347 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.314564 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.607588 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438876145 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95310008 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542739947 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15108786 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 107012461 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60159953 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 978 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3060008107 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2177 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 107012461 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 459450274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50562010 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 536182540 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45835018 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2978218339 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 422353 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1724352 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 41499068 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2227532255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3846059420 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3844664884 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1394536 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 874974484 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 207 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112977902 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679363507 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 252361148 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 62396219 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36704407 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2703896552 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 180 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2499071963 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3469199 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 959964040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 407445563 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 151 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1238186640 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018332 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.960312 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 851329292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 212 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95534350 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 674543157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250165929 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 60031674 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34641501 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2674307937 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2477606155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3178446 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 927538702 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 394492556 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1199047347 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.066312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969260 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 396950099 32.06% 32.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203265879 16.42% 48.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185984424 15.02% 63.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153264847 12.38% 75.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136492690 11.02% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79936535 6.46% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62863067 5.08% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14221934 1.15% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5207165 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 374590988 31.24% 31.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 190702947 15.90% 47.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 181537142 15.14% 62.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153695699 12.82% 75.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136730734 11.40% 86.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80190081 6.69% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 61698536 5.15% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14532490 1.21% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5368730 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1238186640 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1199047347 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1904668 10.20% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12253005 65.59% 75.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4524321 24.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2248592 11.88% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12188219 64.39% 76.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4492341 23.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1633622343 65.37% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 285 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 166 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 37 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 642829515 25.72% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 222619482 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1617099394 65.27% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 639262195 25.80% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 221243949 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2499071963 # Type of FU issued -system.cpu.iq.rate 2.011043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18681994 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6256498920 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3662616880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2395384352 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1982839 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1348326 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 869815 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2516779289 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974668 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57504336 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2477606155 # Type of FU issued +system.cpu.iq.rate 2.058208 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18929152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007640 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6174384179 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3600600502 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2375948293 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1983076 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1349305 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 869249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2495560681 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974626 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 56273066 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234767844 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 254077 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 105937 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 91632646 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229947494 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 250240 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 104617 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 89437427 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 220 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 267187 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 223 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 81293 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 111839194 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23661056 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1167024 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2847195647 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17872608 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679363507 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 252361148 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 180 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 266250 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15108 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 105937 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13288388 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8880688 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22169076 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2446901289 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625251329 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52170674 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 107012461 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18493719 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 964338 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2816222496 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17539215 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 674543157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 250165929 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 222443 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13054 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 104617 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13266110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8853005 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22119115 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2426782897 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 621677051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 50823258 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143298915 # number of nop insts executed -system.cpu.iew.exec_refs 840810767 # number of memory reference insts executed -system.cpu.iew.exec_branches 299911480 # Number of branches executed -system.cpu.iew.exec_stores 215559438 # Number of stores executed -system.cpu.iew.exec_rate 1.969060 # Inst execution rate -system.cpu.iew.wb_sent 2424991603 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2396254167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1371180261 # num instructions producing a value -system.cpu.iew.wb_consumers 1736709964 # num instructions consuming a value +system.cpu.iew.exec_nop 141914378 # number of nop insts executed +system.cpu.iew.exec_refs 835712197 # number of memory reference insts executed +system.cpu.iew.exec_branches 297017404 # Number of branches executed +system.cpu.iew.exec_stores 214035146 # Number of stores executed +system.cpu.iew.exec_rate 2.015988 # Inst execution rate +system.cpu.iew.wb_sent 2405357276 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2376817542 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1361466858 # num instructions producing a value +system.cpu.iew.wb_consumers 1724557006 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.928304 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789527 # average fanout of values written-back +system.cpu.iew.wb_rate 1.974481 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 793091861 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 756599351 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19003362 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1126347446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.615647 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.496030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18849719 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1092034886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.666412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.514594 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 601147369 53.37% 53.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181479999 16.11% 69.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90892282 8.07% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53587955 4.76% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36442488 3.24% 85.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28128451 2.50% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22594945 2.01% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22821835 2.03% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89252122 7.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 565812226 51.81% 51.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181963708 16.66% 68.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91431923 8.37% 76.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53287438 4.88% 81.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36685843 3.36% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28834990 2.64% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22491649 2.06% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22994830 2.11% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88532279 8.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1126347446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1092034886 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89252122 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88532279 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3564188111 # The number of ROB reads -system.cpu.rob.rob_writes 5337700893 # The number of ROB writes -system.cpu.timesIdled 386272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4488070 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3494102884 # The number of ROB reads +system.cpu.rob.rob_writes 5259875951 # The number of ROB writes +system.cpu.timesIdled 272602 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4721057 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.715808 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.715808 # CPI: Total CPI of All Threads -system.cpu.ipc 1.397022 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.397022 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289961218 # number of integer regfile reads -system.cpu.int_regfile_writes 1921862672 # number of integer regfile writes -system.cpu.fp_regfile_reads 50916 # number of floating regfile reads -system.cpu.fp_regfile_writes 565 # number of floating regfile writes +system.cpu.cpi 0.693397 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.693397 # CPI: Total CPI of All Threads +system.cpu.ipc 1.442174 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.442174 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3262431101 # number of integer regfile reads +system.cpu.int_regfile_writes 1906790236 # number of integer regfile writes +system.cpu.fp_regfile_reads 51143 # number of floating regfile reads +system.cpu.fp_regfile_writes 554 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 773.343215 # Cycle average of tags in use -system.cpu.icache.total_refs 402671818 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 414271.417695 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 770.355491 # Cycle average of tags in use +system.cpu.icache.total_refs 399284112 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 966 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 413337.590062 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 773.343215 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.377609 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.377609 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402671818 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402671818 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402671818 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402671818 # 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miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36123.707788 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36123.707788 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36123.707788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36123.707788 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34421.759570 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34421.759570 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34421.759570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34421.759570 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,301 +388,299 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37590.062112 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37590.062112 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37590.062112 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37590.062112 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 715323578 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 715323578 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 715323578 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 715323578 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017837 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017837 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030418 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030418 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.020664 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.020664 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.020664 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.020664 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13684.862961 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13684.862961 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26281.742768 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26281.742768 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 42500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17851.375235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17851.375235 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 54186258 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148410500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 10025 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5405.113017 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32993.081684 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3417249 # number of writebacks -system.cpu.dcache.writebacks::total 3417249 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3065881 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3065881 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021758 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3021758 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6087639 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6087639 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6087639 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6087639 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7298174 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7298174 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883662 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883662 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3416507 # number of writebacks +system.cpu.dcache.writebacks::total 3416507 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2595838 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2595838 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3005313 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3005313 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5601151 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5601151 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5601151 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5601151 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883747 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883747 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9181836 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9181836 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9181836 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9181836 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97342451000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 97342451000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53846535513 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53846535513 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180253 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180253 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180253 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180253 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63651885000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63651885000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 32596175026 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 32596175026 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151188986513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151188986513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151188986513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151188986513 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96248060026 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 96248060026 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96248060026 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 96248060026 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013156 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012800 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012800 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.918636 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.918636 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28586.092151 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28586.092151 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012834 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012834 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8723.611685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8723.611685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17303.902820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17303.902820 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 40500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143649 # number of replacements -system.cpu.l2cache.tagsinuse 30911.087928 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8542511 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173346 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.930580 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 109479230000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14438.028494 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 30.254344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16442.805090 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440614 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.501795 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943332 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5921437 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5921437 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3417249 # 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Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14425.723577 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.926005 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16429.394573 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000944 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.501385 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942567 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5920206 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5920206 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3416507 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3416507 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1101155 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180254 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181220 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180254 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181220 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188640 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188748 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415341 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.415341 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188624 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188731 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415447 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.415447 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235148 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235229 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235167 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.235247 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235148 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235229 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36570.473251 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35668.945014 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35669.581063 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36380.095498 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36380.095498 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36570.473251 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35926.636296 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 35926.926014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36570.473251 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35926.636296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 35926.926014 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 7260431 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235167 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235247 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36575.569358 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35933.943887 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35934.393919 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37037.053564 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37037.053564 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36333.930435 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36333.930435 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 23861689 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 813 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3922 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8930.419434 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6084.061448 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050131 # number of writebacks -system.cpu.l2cache.writebacks::total 1050131 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376729 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377701 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782366 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782366 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2159095 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2160067 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2159095 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2160067 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32474500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44762602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44795076500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26015406452 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26015406452 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32474500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 70778008452 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 70810482952 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32474500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 70778008452 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 70810482952 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1050125 # number of writebacks +system.cpu.l2cache.writebacks::total 1050125 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376292 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1377258 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782601 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782601 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158893 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2159859 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158893 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2159859 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32266500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45051953000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 45084219500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26472928656 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26472928656 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 71524881656 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 71557148156 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32266500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 71524881656 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 71557148156 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415341 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188731 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415447 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415447 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235229 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235247 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235229 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33409.979424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32513.735092 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32514.367414 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33252.220127 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33252.220127 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33409.979424 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32781.331276 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32781.614159 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33409.979424 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32781.331276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32781.614159 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235247 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33402.173913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32734.298390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.766834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33826.852580 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33826.852580 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 15b5a360c..78e7b43f1 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.642008 # Number of seconds simulated -sim_ticks 2642007987000 # Number of ticks simulated -final_tick 2642007987000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631385 # Number of seconds simulated +sim_ticks 2631384990000 # Number of ticks simulated +final_tick 2631384990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1913242 # Simulator instruction rate (inst/s) -host_op_rate 1913242 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2777698581 # Simulator tick rate (ticks/s) -host_mem_usage 217920 # Number of bytes of host memory used -host_seconds 951.15 # Real time elapsed on the host +host_inst_rate 1011793 # Simulator instruction rate (inst/s) +host_op_rate 1011793 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1463043658 # Simulator tick rate (ticks/s) +host_mem_usage 219388 # Number of bytes of host memory used +host_seconds 1798.57 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2149692 # Nu system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52074138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52093565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25399469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25399469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25399469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52074138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77493034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 19506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52284363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52303869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25502008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25502008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25502008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52284363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77805877 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5284015974 # number of cpu cycles simulated +system.cpu.numCycles 5262769980 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5284015974 # Number of busy cycles +system.cpu.num_busy_cycles 5262769980 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.519467 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.470356 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.519467 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299082 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299082 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 612.470356 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299058 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45149000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45149000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45149000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45149000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45149000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45149000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44120000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44120000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44120000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44120000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44120000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44120000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56295.511222 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56295.511222 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56295.511222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56295.511222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56295.511222 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55012.468828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55012.468828 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42743000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42743000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42743000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42743000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42743000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42743000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42516000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42516000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53295.511222 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53295.511222 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53295.511222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53295.511222 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.366966 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.313701 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40989979000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.366966 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995939 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995939 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40977019000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.313701 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995926 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995926 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 158759423000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 158759423000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59584620000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59584620000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218344043000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218344043000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218344043000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218344043000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151059345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151059345000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57691387000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57691387000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 208750732000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 208750732000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 208750732000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 208750732000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21981.490261 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21981.490261 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31537.600830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31537.600830 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23962.951838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23962.951838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23962.951838 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20915.353925 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22910.099439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22910.099439 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137092181000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137092181000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53916660000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53916660000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191008841000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191008841000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191008841000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191008841000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136614517000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136614517000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912747000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912747000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190527264000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190527264000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190527264000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18981.490261 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18981.490261 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28537.600830 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28537.600830 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20962.951838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20962.951838 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18915.353925 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18915.353925 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.529714 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.529714 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133721 # number of replacements -system.cpu.l2cache.tagsinuse 30166.534681 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30159.988647 # Cycle average of tags in use system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 498438853000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14372.614424 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 37.649566 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15756.270691 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438617 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001149 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.480843 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.920610 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 496965874000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14375.657027 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 37.778500 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15746.553119 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.438710 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.480547 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.920410 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits @@ -301,17 +301,17 @@ system.cpu.l2cache.demand_misses::total 2150494 # nu system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2149692 # number of overall misses system.cpu.l2cache.overall_misses::total 2150494 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70765916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70807620000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018068000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41018068000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41704000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111783984000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 111825688000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41704000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111783984000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 111825688000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41714000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70776793000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70818507000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018317000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41018317000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41714000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111795110000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 111836824000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41714000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111795110000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 111836824000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) @@ -336,17 +336,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.235993 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52012.468828 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.992605 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52007.995241 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.315666 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.315666 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52005.178345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52005.178345 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,17 +368,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2150494 system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54435320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54467400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552360000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552360000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85987680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86019760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85987680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86019760000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32090000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54446197000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54478287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85998806000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86030896000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32090000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85998806000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86030896000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses @@ -390,17 +390,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.315666 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.315666 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 14d5fad91..620901a70 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.479173 # Number of seconds simulated -sim_ticks 479173106500 # Number of ticks simulated -final_tick 479173106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.454220 # Number of seconds simulated +sim_ticks 454219906500 # Number of ticks simulated +final_tick 454219906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135351 # Simulator instruction rate (inst/s) -host_op_rate 150994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41990206 # Simulator tick rate (ticks/s) -host_mem_usage 229432 # Number of bytes of host memory used -host_seconds 11411.54 # Real time elapsed on the host -sim_insts 1544563038 # Number of instructions simulated -sim_ops 1723073850 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156363136 # Number of bytes read from this memory -system.physmem.bytes_read::total 156411648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71949056 # Number of bytes written to this memory -system.physmem.bytes_written::total 71949056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2443174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2443932 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1124204 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124204 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 101241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326318681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 326419922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 150152534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 150152534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 150152534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326318681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 476572456 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 138720 # Simulator instruction rate (inst/s) +host_op_rate 154753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40794382 # Simulator tick rate (ticks/s) +host_mem_usage 234840 # Number of bytes of host memory used +host_seconds 11134.37 # Real time elapsed on the host +sim_insts 1544563043 # Number of instructions simulated +sim_ops 1723073855 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156313408 # Number of bytes read from this memory +system.physmem.bytes_read::total 156361216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71943232 # Number of bytes written to this memory +system.physmem.bytes_written::total 71943232 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2442397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443144 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124113 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124113 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 105253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344135970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344241223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 105253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158388549 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158388549 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158388549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 105253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344135970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 502629772 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,319 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 958346214 # number of cpu cycles simulated +system.cpu.numCycles 908439814 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 302436824 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248070487 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16102737 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 165612861 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 157810575 # Number of BTB hits +system.cpu.BPredUnit.lookups 299293350 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245165786 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16042294 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 167415927 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155291115 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18381050 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 257 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295095953 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2169970618 # Number of instructions fetch has processed -system.cpu.fetch.Branches 302436824 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176191625 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 431629876 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 85633501 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155381037 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 18349808 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 291155231 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2147464853 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299293350 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 173640923 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 427083963 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 82022952 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117971766 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 95 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285890160 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5533233 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 950851132 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.536857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.220630 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 282205512 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5329978 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901954385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.649183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246512 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519221373 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23554787 2.48% 57.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38911325 4.09% 61.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47909996 5.04% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 41216698 4.33% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47160592 4.96% 75.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39133251 4.12% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18348533 1.93% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175394577 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 474870538 52.65% 52.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22740626 2.52% 55.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38702218 4.29% 59.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47644255 5.28% 64.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40322718 4.47% 69.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46782649 5.19% 74.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38980366 4.32% 78.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18009770 2.00% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 173901245 19.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 950851132 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315582 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.264287 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327095784 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 132835494 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402923516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19252859 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68743479 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46256582 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2358824481 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2518 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68743479 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 349861256 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63822770 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14217 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397782583 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70626827 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2300352404 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28571 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5556438 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56486754 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 21 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2275431187 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10618596825 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10618592524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4301 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319954 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 569111233 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1538 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155721257 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 627567306 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219602180 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87405609 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68407559 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2199673736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1543 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020179794 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4995947 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 472270317 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1103060101 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1370 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 950851132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.124602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914321 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 901954385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.329459 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.363904 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 319244517 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 99044104 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402843645 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15079439 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65742680 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46017167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 685 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2336575701 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2448 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 65742680 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 340277658 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45082178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13877 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 395714637 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55123355 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2280505483 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18602 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4635517 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42073464 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2255238182 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10526656383 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10526652098 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4285 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 548918220 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1694 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1690 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 127506095 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 622196847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217942695 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85227601 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65382931 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2181344295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1719 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2010119502 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4796816 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 454085036 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1056260113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1545 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901954385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.228627 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.927984 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272421375 28.65% 28.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 149099949 15.68% 44.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161022280 16.93% 61.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117844218 12.39% 73.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124393177 13.08% 86.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74467059 7.83% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38344308 4.03% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10541348 1.11% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2717418 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 241738453 26.80% 26.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 133353594 14.78% 41.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 156367006 17.34% 58.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 115954647 12.86% 71.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125581942 13.92% 85.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75899476 8.42% 94.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39722592 4.40% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10686145 1.18% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2650530 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 950851132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901954385 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 857125 3.43% 3.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4796 0.02% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18987474 76.03% 79.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5123425 20.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 695241 2.77% 2.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4797 0.02% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19085015 76.16% 78.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5273410 21.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236499214 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 932103 0.05% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 78 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 35 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588851338 29.15% 90.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193897003 9.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1230459115 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 930103 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 33 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 585119298 29.11% 90.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193610861 9.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020179794 # Type of FU issued -system.cpu.iq.rate 2.107985 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24972820 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012362 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021178993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2672131610 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1961102368 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 494 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 800 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2045152363 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 251 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63608304 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2010119502 # Type of FU issued +system.cpu.iq.rate 2.212716 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25058463 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012466 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4952048213 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2635615257 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1952750313 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 782 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2035177734 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63595770 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 141640534 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 283255 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189454 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 44755132 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 136270074 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 285522 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187812 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43095646 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1142386 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 118212 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68743479 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28058898 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1485147 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2199675446 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5559671 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 627567306 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219602180 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1479 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343072 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56281 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189454 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8595611 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10221674 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18817285 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1990434220 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574229120 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29745574 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65742680 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 20161039 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1080033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2181346094 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5536242 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 622196847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217942695 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1653 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 177278 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 42353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187812 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8595145 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10187661 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18782806 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1980860321 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 570725685 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29259181 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 167 # number of nop insts executed -system.cpu.iew.exec_refs 765174747 # number of memory reference insts executed -system.cpu.iew.exec_branches 238396251 # Number of branches executed -system.cpu.iew.exec_stores 190945627 # Number of stores executed -system.cpu.iew.exec_rate 2.076947 # Inst execution rate -system.cpu.iew.wb_sent 1969970289 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1961102553 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296676707 # num instructions producing a value -system.cpu.iew.wb_consumers 2069059836 # num instructions consuming a value +system.cpu.iew.exec_nop 80 # number of nop insts executed +system.cpu.iew.exec_refs 761335906 # number of memory reference insts executed +system.cpu.iew.exec_branches 237528825 # Number of branches executed +system.cpu.iew.exec_stores 190610221 # Number of stores executed +system.cpu.iew.exec_rate 2.180508 # Inst execution rate +system.cpu.iew.wb_sent 1961779173 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1952750482 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1293463699 # num instructions producing a value +system.cpu.iew.wb_consumers 2065510739 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.046340 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626699 # average fanout of values written-back +system.cpu.iew.wb_rate 2.149565 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626220 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 476677558 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 173 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16102047 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882107654 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953360 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727618 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 458335863 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16041632 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 836211706 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.060571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763665 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 391464028 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194903618 22.10% 66.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73864004 8.37% 74.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35187525 3.99% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19179450 2.17% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30712235 3.48% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19231414 2.18% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11310832 1.28% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106254548 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 346444317 41.43% 41.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193987468 23.20% 64.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73877669 8.83% 73.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35342489 4.23% 77.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18524109 2.22% 79.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30984795 3.71% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19692342 2.35% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10738999 1.28% 87.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106619518 12.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882107654 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563056 # Number of instructions committed -system.cpu.commit.committedOps 1723073868 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 836211706 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563061 # Number of instructions committed +system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773820 # Number of memory references committed -system.cpu.commit.loads 485926772 # Number of loads committed +system.cpu.commit.refs 660773822 # Number of memory references committed +system.cpu.commit.loads 485926773 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462429 # Number of branches committed +system.cpu.commit.branches 213462430 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106254548 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106619518 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2975603933 # The number of ROB reads -system.cpu.rob.rob_writes 4468410288 # The number of ROB writes -system.cpu.timesIdled 802202 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7495082 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563038 # Number of Instructions Simulated -system.cpu.committedOps 1723073850 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563038 # Number of Instructions Simulated -system.cpu.cpi 0.620464 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.620464 # CPI: Total CPI of All Threads -system.cpu.ipc 1.611696 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.611696 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9970442228 # number of integer regfile reads -system.cpu.int_regfile_writes 1940974329 # number of integer regfile writes -system.cpu.fp_regfile_reads 200 # number of floating regfile reads -system.cpu.fp_regfile_writes 218 # number of floating regfile writes -system.cpu.misc_regfile_reads 2910515379 # number of misc regfile reads -system.cpu.misc_regfile_writes 130 # number of misc regfile writes -system.cpu.icache.replacements 28 # number of replacements -system.cpu.icache.tagsinuse 630.233308 # Cycle average of tags in use -system.cpu.icache.total_refs 285889001 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 361427.308470 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2911001325 # The number of ROB reads +system.cpu.rob.rob_writes 4428720797 # The number of ROB writes +system.cpu.timesIdled 678798 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6485429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563043 # Number of Instructions Simulated +system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated +system.cpu.cpi 0.588153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588153 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700237 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700237 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9924440864 # number of integer regfile reads +system.cpu.int_regfile_writes 1932829114 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.fp_regfile_writes 197 # number of floating regfile writes +system.cpu.misc_regfile_reads 2885564305 # number of misc regfile reads +system.cpu.misc_regfile_writes 132 # number of misc regfile writes +system.cpu.icache.replacements 18 # number of replacements +system.cpu.icache.tagsinuse 627.769502 # Cycle average of tags in use +system.cpu.icache.total_refs 282204371 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 363197.388674 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 630.233308 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.307731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.307731 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285889001 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285889001 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285889001 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285889001 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285889001 # number of overall hits -system.cpu.icache.overall_hits::total 285889001 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses -system.cpu.icache.overall_misses::total 1159 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40537500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40537500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40537500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40537500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40537500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40537500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285890160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285890160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285890160 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285890160 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285890160 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285890160 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 627.769502 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306528 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306528 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 282204371 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 282204371 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 282204371 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 282204371 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 282204371 # number of overall hits +system.cpu.icache.overall_hits::total 282204371 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses +system.cpu.icache.overall_misses::total 1141 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38891500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38891500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38891500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38891500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38891500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38891500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 282205512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 282205512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 282205512 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 282205512 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 282205512 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 282205512 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34976.272649 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34976.272649 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34976.272649 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34976.272649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34976.272649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34976.272649 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34085.451358 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34085.451358 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34085.451358 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34085.451358 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,313 +398,313 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 366 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 366 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 366 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 366 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 366 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28758000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28758000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28758000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28758000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28758000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28758000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28274000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28274000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36264.817150 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36264.817150 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36264.817150 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36264.817150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36264.817150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36264.817150 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36341.902314 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36341.902314 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9619744 # number of replacements -system.cpu.dcache.tagsinuse 4087.812260 # Cycle average of tags in use -system.cpu.dcache.total_refs 661842215 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9623840 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.771116 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3371762000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.812260 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998001 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 494447214 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 494447214 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167394841 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167394841 # number of WriteReq hits +system.cpu.dcache.replacements 9617276 # number of replacements +system.cpu.dcache.tagsinuse 4087.426616 # Cycle average of tags in use +system.cpu.dcache.total_refs 660019994 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9621372 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.599363 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.426616 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 492609527 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 492609527 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167410308 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167410308 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 64 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 64 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 661842055 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 661842055 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 661842055 # number of overall hits -system.cpu.dcache.overall_hits::total 661842055 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10786587 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10786587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5191206 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5191206 # number of WriteReq misses +system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 660019835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 660019835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 660019835 # number of overall hits +system.cpu.dcache.overall_hits::total 660019835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10110221 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10110221 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5175739 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5175739 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15977793 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15977793 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15977793 # number of overall misses -system.cpu.dcache.overall_misses::total 15977793 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 258796358500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 258796358500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 196312102576 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 196312102576 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 455108461076 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 455108461076 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 455108461076 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 455108461076 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 505233801 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 505233801 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15285960 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15285960 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15285960 # number of overall misses +system.cpu.dcache.overall_misses::total 15285960 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152096766000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152096766000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119863517075 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119863517075 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 271960283075 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 271960283075 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 271960283075 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 271960283075 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 502719748 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 502719748 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 96 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 96 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 64 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 64 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 677819848 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 677819848 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 677819848 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 677819848 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021350 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021350 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030079 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030079 # miss rate for WriteReq accesses +system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 675305795 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 675305795 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 675305795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 675305795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020111 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020111 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029989 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031250 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023572 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023572 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023572 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023572 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23992.423044 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23992.423044 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37816.280567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37816.280567 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28483.812569 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28483.812569 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28483.812569 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28483.812569 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2524022061 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 152500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 425271 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5935.090944 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19062.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.022636 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022636 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022636 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022636 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15043.861652 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15043.861652 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23158.725174 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23158.725174 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17791.508226 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17791.508226 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 277962262 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 153500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 60300 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4609.656086 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17055.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3474670 # number of writebacks -system.cpu.dcache.writebacks::total 3474670 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3056668 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3056668 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3297283 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3473158 # number of writebacks +system.cpu.dcache.writebacks::total 3473158 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2383078 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2383078 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281509 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3281509 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6353951 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6353951 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6353951 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6353951 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729919 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7729919 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893923 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893923 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9623842 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9623842 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9623842 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9623842 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124459960000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 124459960000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91541598892 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91541598892 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216001558892 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 216001558892 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216001558892 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 216001558892 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015300 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015300 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014198 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014198 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014198 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014198 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16101.069106 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16101.069106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48334.382597 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48334.382597 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22444.420731 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22444.420731 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22444.420731 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22444.420731 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 5664587 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5664587 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5664587 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5664587 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727143 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7727143 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894230 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894230 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9621373 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9621373 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9621373 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9621373 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75156431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75156431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39462683260 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 39462683260 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114619114760 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114619114760 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114619114760 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114619114760 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015371 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015371 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010976 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010976 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014247 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014247 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9726.289717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9726.289717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20833.100130 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20833.100130 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2428430 # number of replacements -system.cpu.l2cache.tagsinuse 31166.069824 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8746727 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2458142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.558268 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 81035522000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14015.954126 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.241585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17134.874112 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.427733 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33987.089385 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1124113 # number of writebacks +system.cpu.l2cache.writebacks::total 1124113 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 747 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611373 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1612120 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 831024 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 747 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2442397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2443144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 747 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2442397 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2443144 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25029000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54213758000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54238787000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33085952005 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33085952005 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25029000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87299710005 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87324739005 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25029000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87299710005 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87324739005 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208534 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253908 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33506.024096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33644.449795 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33644.385654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39813.473504 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39813.473504 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index becebde6e..49ea5f586 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.409361 # Number of seconds simulated -sim_ticks 2409361491000 # Number of ticks simulated -final_tick 2409361491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.399400 # Number of seconds simulated +sim_ticks 2399400439000 # Number of ticks simulated +final_tick 2399400439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1043020 # Simulator instruction rate (inst/s) -host_op_rate 1164020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633141547 # Simulator tick rate (ticks/s) -host_mem_usage 227940 # Number of bytes of host memory used -host_seconds 1475.29 # Real time elapsed on the host +host_inst_rate 994913 # Simulator instruction rate (inst/s) +host_op_rate 1110332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1551375376 # Simulator tick rate (ticks/s) +host_mem_usage 233816 # Number of bytes of host memory used +host_seconds 1546.63 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 2153435 # Nu system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57201811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57218174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16363 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16363 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27899999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27899999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27899999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57201811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 85118173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 16431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57439283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57455713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 28015825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28015825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 28015825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57439283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 85471539 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4818722982 # number of cpu cycles simulated +system.cpu.numCycles 4798800878 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 660773815 # nu system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4818722982 # Number of busy cycles +system.cpu.num_busy_cycles 4798800878 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 515.026762 # Cycle average of tags in use +system.cpu.icache.tagsinuse 514.980115 # Cycle average of tags in use system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 515.026762 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251478 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251478 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 514.980115 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251455 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251455 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34951000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34951000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34951000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34951000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34951000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34951000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34189000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34189000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34189000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34189000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34189000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34189000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54782.131661 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54782.131661 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54782.131661 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54782.131661 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54782.131661 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53587.774295 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53587.774295 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53587.774295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53587.774295 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33037000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33037000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33037000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33037000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33037000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33037000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32913000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32913000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51782.131661 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51782.131661 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51782.131661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51782.131661 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51587.774295 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51587.774295 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.605959 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4083.564925 # Cycle average of tags in use system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25924036000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.605959 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996974 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996974 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 25914432000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.564925 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996964 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996964 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 158944725000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 158944725000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59599499000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59599499000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218544224000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218544224000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218544224000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218544224000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151247261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151247261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57698979000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57698979000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 208946240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 208946240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 208946240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 208946240000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21995.960608 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21995.960608 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31548.331550 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31548.331550 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23975.706608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23975.706608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23975.706608 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20930.727931 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20930.727931 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30542.312438 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30542.312438 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22922.746048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22922.746048 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137266464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137266464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53932052000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53932052000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191198516000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191198516000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191198516000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191198516000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136795087000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 136795087000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53920681000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53920681000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190715768000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 190715768000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190715768000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 190715768000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18995.960608 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18995.960608 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28548.331550 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28548.331550 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20975.706608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20975.706608 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.727931 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.727931 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28542.312438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28542.312438 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.746048 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2138446 # number of replacements -system.cpu.l2cache.tagsinuse 30629.012311 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30623.782374 # Cycle average of tags in use system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 437178443000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14783.850246 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.711580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15829.450485 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.451167 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000479 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.483076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.934723 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 435858689000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14787.769987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.768959 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15820.243429 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.451287 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000481 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.482796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.934564 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 2154051 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70949164000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70981196000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41029456000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41029456000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111978620000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 112010652000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111978620000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 112010652000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32055000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70952200000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 70984255000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41030322000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41030322000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32055000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 111982522000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 112014577000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32055000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 111982522000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 112014577000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.236297 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52037.337662 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.225142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.240988 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.097553 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.097553 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.822148 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.822148 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2154051 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54576280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54600920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86137400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86162040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86137400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86162040000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24663000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54579316000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54603979000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24663000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86141302000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86165965000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24663000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86141302000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86165965000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40037.337662 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.225142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.240988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.097553 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.097553 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index a47f0fd8f..04d920eee 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.901049 # Number of seconds simulated -sim_ticks 5901048883000 # Number of ticks simulated -final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.891582 # Number of seconds simulated +sim_ticks 5891581948000 # Number of ticks simulated +final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582820 # Simulator instruction rate (inst/s) -host_op_rate 908086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1143336514 # Simulator tick rate (ticks/s) -host_mem_usage 274832 # Number of bytes of host memory used -host_seconds 5161.25 # Real time elapsed on the host +host_inst_rate 701685 # Simulator instruction rate (inst/s) +host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1374310212 # Simulator tick rate (ticks/s) +host_mem_usage 228764 # Number of bytes of host memory used +host_seconds 4286.94 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 2172556 # Nu system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11802097766 # number of cpu cycles simulated +system.cpu.numCycles 11783163896 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713082 # nu system.cpu.num_load_insts 1239184745 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11802097766 # Number of busy cycles +system.cpu.num_busy_cycles 11783163896 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37868000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37868000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37868000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56100.740741 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56100.740741 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35843000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 159195313000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59631053000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59631053000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57741123000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57741123000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 209712206000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 209712206000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 209712206000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24013.400892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24013.400892 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21040.321064 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21040.321064 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23013.238152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23013.238152 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961572000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961572000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191488335000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191488335000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525383000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525383000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961469000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486852000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486852000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191486852000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.321064 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.321064 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.655440 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.655440 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2158210 # number of replacements -system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941512 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 1315499445000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14663.466685 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 21.611649 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16164.776461 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.447493 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000660 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.493310 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.941463 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits @@ -269,17 +269,17 @@ system.cpu.l2cache.demand_misses::total 2173231 # nu system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35100000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71936280000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071732000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41071732000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35100000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112972912000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113008012000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35100000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112972912000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113008012000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35105000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901183000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71936288000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071782000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41071782000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35105000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112972965000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113008070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35105000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112972965000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113008070000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) @@ -304,17 +304,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.238467 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52007.407407 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.002170 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.005783 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.063304 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.063304 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.026688 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.026688 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -336,17 +336,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2173231 system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86929240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86929240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27005000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308603000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335608000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593690000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593690000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27005000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902293000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 86929298000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27005000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902293000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 86929298000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses @@ -358,17 +358,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index c057cfc04..aad21c6d0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042012 # Number of seconds simulated -sim_ticks 42012413000 # Number of ticks simulated -final_tick 42012413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042001 # Number of seconds simulated +sim_ticks 42001440000 # Number of ticks simulated +final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107145 # Simulator instruction rate (inst/s) -host_op_rate 107145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48980163 # Simulator tick rate (ticks/s) -host_mem_usage 222716 # Number of bytes of host memory used -host_seconds 857.74 # Real time elapsed on the host +host_inst_rate 75192 # Simulator instruction rate (inst/s) +host_op_rate 75192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34364250 # Simulator tick rate (ticks/s) +host_mem_usage 223172 # Number of bytes of host memory used +host_seconds 1222.24 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4256266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3266082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7522348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4256266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4256266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4256266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3266082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7522348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -43,10 +43,10 @@ system.cpu.dtb.data_hits 26498122 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498155 # DTB accesses -system.cpu.itb.fetch_hits 10034924 # ITB hits +system.cpu.itb.fetch_hits 10035828 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10034973 # ITB accesses +system.cpu.itb.fetch_accesses 10035877 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84024827 # number of cpu cycles simulated +system.cpu.numCycles 84002881 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564834 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782438 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4497092 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7991226 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3849853 # Number of BTB hits +system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 121 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.176000 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999065 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7565769 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73744929 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320401 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38529057 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26768938 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3519911 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 976323 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4496234 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5744468 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.905525 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57470438 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26769096 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83640241 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11659 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7743859 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76280968 # Number of cycles cpu stages are processed. -system.cpu.activity 90.783844 # Percentage of cycles cpu is active +system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed. +system.cpu.activity 90.809399 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -107,144 +107,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914277 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914277 # CPI: Total CPI of All Threads -system.cpu.ipc 1.093761 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads +system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.093761 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27805541 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56219286 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.907946 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34577681 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447146 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.848257 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34047365 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49977462 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.479399 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65995198 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029629 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.457502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30080947 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53943880 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.199930 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 8128 # number of replacements -system.cpu.icache.tagsinuse 1492.257079 # Cycle average of tags in use -system.cpu.icache.total_refs 10023168 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10013 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.015480 # Average number of references to valid blocks. +system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8127 # number of replacements +system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use +system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.257079 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728641 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10023168 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10023168 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10023168 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10023168 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10023168 # number of overall hits -system.cpu.icache.overall_hits::total 10023168 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11752 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11752 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11752 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11752 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11752 # number of overall misses -system.cpu.icache.overall_misses::total 11752 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 302404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 302404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 302404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 302404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 302404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 302404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10034920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10034920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10034920 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10034920 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10034920 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10034920 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits +system.cpu.icache.overall_hits::total 10024070 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses +system.cpu.icache.overall_misses::total 11754 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25732.173247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25732.173247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25732.173247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25732.173247 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 91000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10013 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10013 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10013 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10013 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234933000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 234933000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234933000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 234933000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234933000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 234933000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23462.798362 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23462.798362 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.425760 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491190 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.864597 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.425760 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351911 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995640 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995640 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491190 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491190 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491190 # number of overall hits -system.cpu.dcache.overall_hits::total 26491190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 558 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 558 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits +system.cpu.dcache.overall_hits::total 26491189 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6111 # number of overall misses -system.cpu.dcache.overall_misses::total 6111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29911500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29911500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 335932500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 335932500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 365844000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 365844000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 365844000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 365844000 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses +system.cpu.dcache.overall_misses::total 6112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -261,32 +261,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53604.838710 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53604.838710 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60495.678012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60495.678012 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59866.470299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59866.470299 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41291000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49928.657799 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3888 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3888 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3888 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3888 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24206500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24206500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 96919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121125500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 121125500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121125500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 121125500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50961.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50961.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55445.652174 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55445.652174 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066822 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7219 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279037 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.403563 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279037 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.403563 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53431.460272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54700.236967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53597.947761 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54835.365854 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54835.365854 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54029.465371 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54029.465371 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115196500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17936000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133132500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73235000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73235000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115196500 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.403563 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.403563 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41229.957051 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42502.369668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41396.921642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42529.036005 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42529.036005 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 79c8453b1..4339a22dc 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023661 # Number of seconds simulated -sim_ticks 23661066000 # Number of ticks simulated -final_tick 23661066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023660 # Number of seconds simulated +sim_ticks 23659827000 # Number of ticks simulated +final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163409 # Simulator instruction rate (inst/s) -host_op_rate 163409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45930776 # Simulator tick rate (ticks/s) -host_mem_usage 223740 # Number of bytes of host memory used -host_seconds 515.15 # Real time elapsed on the host +host_inst_rate 114539 # Simulator instruction rate (inst/s) +host_op_rate 114539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32192844 # Simulator tick rate (ticks/s) +host_mem_usage 224192 # Number of bytes of host memory used +host_seconds 734.94 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 335744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3083 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3088 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5246 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8339100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5850624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14189724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8339100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8339100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8339100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5850624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14189724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8353062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5850930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14203992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8353062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8353062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8353062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5850930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14203992 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23226472 # DTB read hits -system.cpu.dtb.read_misses 199471 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23425943 # DTB read accesses -system.cpu.dtb.write_hits 7079215 # DTB write hits -system.cpu.dtb.write_misses 1341 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 7080556 # DTB write accesses -system.cpu.dtb.data_hits 30305687 # DTB hits -system.cpu.dtb.data_misses 200812 # DTB misses -system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 30506499 # DTB accesses -system.cpu.itb.fetch_hits 14950241 # ITB hits -system.cpu.itb.fetch_misses 107 # ITB misses +system.cpu.dtb.read_hits 23229098 # DTB read hits +system.cpu.dtb.read_misses 198676 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23427774 # DTB read accesses +system.cpu.dtb.write_hits 7078776 # DTB write hits +system.cpu.dtb.write_misses 1365 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7080141 # DTB write accesses +system.cpu.dtb.data_hits 30307874 # DTB hits +system.cpu.dtb.data_misses 200041 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30507915 # DTB accesses +system.cpu.itb.fetch_hits 14959914 # ITB hits +system.cpu.itb.fetch_misses 83 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14950348 # ITB accesses +system.cpu.itb.fetch_accesses 14959997 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47322133 # number of cpu cycles simulated +system.cpu.numCycles 47319655 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15026940 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10894124 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964629 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8768677 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7072325 # Number of BTB hits +system.cpu.BPredUnit.lookups 15036576 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10900203 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 965407 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8822625 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7081383 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1489344 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3225 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15650036 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128237375 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15026940 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8561669 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22385381 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4637420 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5548184 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2165 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14950241 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 337394 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47225069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.715451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372476 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1488044 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3227 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15623244 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128299344 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15036576 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8569427 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22397875 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4641617 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5564099 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1980 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14959914 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 337946 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47229880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.716487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372485 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24839688 52.60% 52.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2391446 5.06% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1209126 2.56% 60.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776446 3.76% 63.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2802962 5.94% 69.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1171165 2.48% 72.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1227887 2.60% 75.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 787448 1.67% 76.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11018901 23.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24832005 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2392801 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1209799 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776867 3.76% 63.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2804961 5.94% 69.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1173464 2.48% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1230763 2.61% 75.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 789158 1.67% 76.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11020062 23.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47225069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317546 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.709882 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17490874 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4250840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20765641 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090220 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3627494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2542741 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12176 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125152088 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32110 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3627494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18655906 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 966254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8182 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20668416 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3298817 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122169743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 401900 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2424267 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89702215 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158657740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148914395 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9743345 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47229880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317766 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.711333 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17466031 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4264969 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20777128 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090965 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3630787 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2547167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12222 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125218187 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32252 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3630787 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18637244 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 968362 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8091 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20675127 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3310269 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122217574 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 404537 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2431302 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89737060 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158727741 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148984302 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9743439 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21274854 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1100 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8739612 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25558040 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8300974 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2604808 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106164029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2236 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96990974 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 187003 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21520200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16153199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1847 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47225069 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875376 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21309699 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1072 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1080 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762996 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25566964 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8306109 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2633900 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 924738 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106206807 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2480 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 97009064 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188398 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21564802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16193043 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2091 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47229880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053977 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.874944 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12469931 26.41% 26.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9437048 19.98% 46.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8469534 17.93% 64.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6320288 13.38% 77.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4943441 10.47% 88.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2849790 6.03% 94.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723941 3.65% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801134 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209962 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12465875 26.39% 26.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9434862 19.98% 46.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8477387 17.95% 64.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6321383 13.38% 77.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4949351 10.48% 88.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2846830 6.03% 94.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1724266 3.65% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801279 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 208647 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47225069 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47229880 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187127 11.94% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 172 0.01% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5609 0.36% 12.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843370 53.79% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445220 28.40% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79228 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189791 12.08% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 221 0.01% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5711 0.36% 12.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843066 53.68% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445505 28.36% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79246 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58991306 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480706 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59007350 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480907 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802495 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115483 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386219 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311493 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759735 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2801835 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115568 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386144 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311424 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759643 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,84 +221,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23972181 24.72% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7171030 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23975074 24.71% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7170793 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96990974 # Type of FU issued -system.cpu.iq.rate 2.049590 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1567853 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016165 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227829224 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118898019 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87368354 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15132649 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8823096 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7068677 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90563080 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7995740 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518780 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 97009064 # Type of FU issued +system.cpu.iq.rate 2.050080 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1570667 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016191 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227877046 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118983933 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87385352 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15130027 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8824854 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7067767 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90585387 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7994337 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520935 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5561842 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19579 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34790 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1799871 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5570766 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20063 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34811 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1805006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10523 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3627494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132338 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17118 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116467170 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 392102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25558040 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8300974 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2929 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 49 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34790 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 570155 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508194 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1078349 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95694648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23426609 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1296326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3630787 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133855 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17474 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116506957 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 391259 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25566964 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8306109 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2480 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3139 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34811 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 570809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1079005 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95710462 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23428475 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1298602 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10300905 # number of nop insts executed -system.cpu.iew.exec_refs 30507339 # number of memory reference insts executed -system.cpu.iew.exec_branches 12077728 # Number of branches executed -system.cpu.iew.exec_stores 7080730 # Number of stores executed -system.cpu.iew.exec_rate 2.022196 # Inst execution rate -system.cpu.iew.wb_sent 94980194 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94437031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64621172 # num instructions producing a value -system.cpu.iew.wb_consumers 90003030 # num instructions consuming a value +system.cpu.iew.exec_nop 10297670 # number of nop insts executed +system.cpu.iew.exec_refs 30508815 # number of memory reference insts executed +system.cpu.iew.exec_branches 12080088 # Number of branches executed +system.cpu.iew.exec_stores 7080340 # Number of stores executed +system.cpu.iew.exec_rate 2.022637 # Inst execution rate +system.cpu.iew.wb_sent 94996847 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94453119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64630172 # num instructions producing a value +system.cpu.iew.wb_consumers 90018458 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.995621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717989 # average fanout of values written-back +system.cpu.iew.wb_rate 1.996065 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24565165 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24605076 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952869 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43597575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.107985 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.734489 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43599093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.107912 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.734433 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17052737 39.11% 39.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9973933 22.88% 61.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4509329 10.34% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2295130 5.26% 77.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1618190 3.71% 81.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123694 2.58% 83.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722585 1.66% 85.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 817482 1.88% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5484495 12.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17053308 39.11% 39.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9978024 22.89% 62.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4508053 10.34% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2287531 5.25% 77.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1622514 3.72% 81.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125878 2.58% 83.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721380 1.65% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820634 1.88% 87.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5481771 12.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43597575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43599093 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +309,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5484495 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5481771 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154580260 # The number of ROB reads -system.cpu.rob.rob_writes 236588154 # The number of ROB writes -system.cpu.timesIdled 2240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 97064 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154624413 # The number of ROB reads +system.cpu.rob.rob_writes 236671244 # The number of ROB writes +system.cpu.timesIdled 1995 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 89775 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.562156 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.562156 # CPI: Total CPI of All Threads -system.cpu.ipc 1.778865 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.778865 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129472042 # number of integer regfile reads -system.cpu.int_regfile_writes 70778136 # number of integer regfile writes -system.cpu.fp_regfile_reads 6192217 # number of floating regfile reads -system.cpu.fp_regfile_writes 6050128 # number of floating regfile writes -system.cpu.misc_regfile_reads 714420 # number of misc regfile reads +system.cpu.cpi 0.562127 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.562127 # CPI: Total CPI of All Threads +system.cpu.ipc 1.778959 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.778959 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129495815 # number of integer regfile reads +system.cpu.int_regfile_writes 70794338 # number of integer regfile writes +system.cpu.fp_regfile_reads 6191717 # number of floating regfile reads +system.cpu.fp_regfile_writes 6049387 # number of floating regfile writes +system.cpu.misc_regfile_reads 714327 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10236 # number of replacements -system.cpu.icache.tagsinuse 1604.355346 # Cycle average of tags in use -system.cpu.icache.total_refs 14936697 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12175 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1226.833429 # Average number of references to valid blocks. +system.cpu.icache.replacements 10388 # number of replacements +system.cpu.icache.tagsinuse 1605.369069 # Cycle average of tags in use +system.cpu.icache.total_refs 14946221 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12326 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1212.576748 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1604.355346 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.783377 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.783377 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14936697 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14936697 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14936697 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14936697 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14936697 # number of overall hits -system.cpu.icache.overall_hits::total 14936697 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13544 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13544 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13544 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13544 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13544 # number of overall misses -system.cpu.icache.overall_misses::total 13544 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214516500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214516500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214516500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214516500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214516500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214516500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14950241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14950241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14950241 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14950241 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14950241 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14950241 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000906 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000906 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000906 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15838.489368 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15838.489368 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15838.489368 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15838.489368 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1605.369069 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.783872 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.783872 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14946221 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14946221 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14946221 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14946221 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14946221 # number of overall hits +system.cpu.icache.overall_hits::total 14946221 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13693 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13693 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13693 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13693 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13693 # number of overall misses +system.cpu.icache.overall_misses::total 13693 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 189030000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 189030000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 189030000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 189030000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 189030000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 189030000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14959914 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14959914 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14959914 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14959914 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14959914 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14959914 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13804.863799 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13804.863799 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13804.863799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13804.863799 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,300 +381,300 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1369 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1369 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1369 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1369 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1369 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1369 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12175 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12175 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12175 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12175 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12175 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12175 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 142455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 142455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 142455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 142455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 142455000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 142455000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000814 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000814 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000814 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.616016 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.616016 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12326 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12326 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12326 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12326 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12326 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12326 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130707500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130707500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130707500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130707500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130707500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130707500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000824 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000824 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000824 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10604.210612 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10604.210612 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.tagsinuse 1456.192464 # Cycle average of tags in use -system.cpu.dcache.total_refs 28189208 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.278820 # Cycle average of tags in use +system.cpu.dcache.total_refs 28189701 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12567.636202 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12567.855996 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1456.192464 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.355516 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.355516 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21695723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21695723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493020 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 465 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 465 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28188743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28188743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28188743 # number of overall hits -system.cpu.dcache.overall_hits::total 28188743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 984 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8083 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8083 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1458.278820 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.356025 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.356025 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21696214 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21696214 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493021 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493021 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 466 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 466 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28189235 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28189235 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28189235 # number of overall hits +system.cpu.dcache.overall_hits::total 28189235 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8082 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8082 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9067 # number of overall misses -system.cpu.dcache.overall_misses::total 9067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32711000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32711000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 344620000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 344620000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 45000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 45000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377331000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377331000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377331000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377331000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21696707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21696707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9040 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9040 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9040 # number of overall misses +system.cpu.dcache.overall_misses::total 9040 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29562000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29562000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 293120000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 293120000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 322682000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 322682000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 322682000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 322682000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21697172 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21697172 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28197810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28197810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28197810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28197810 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28198275 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28198275 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28198275 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28198275 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001243 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001243 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000322 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000322 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000322 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000322 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33242.886179 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33242.886179 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42635.160213 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42635.160213 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41615.859711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41615.859711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12500 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002141 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002141 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000321 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000321 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000321 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000321 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30858.037578 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30858.037578 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36268.250433 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36268.250433 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6351 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6351 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6825 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 510 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 510 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 446 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 446 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6352 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6798 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6798 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6798 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6798 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1730 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1730 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2242 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68881000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 68881000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68210000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 68210000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86985500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 86985500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86985500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 86985500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 86285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86285000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 86285000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002146 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002141 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002141 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35499.019608 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35499.019608 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39769.630485 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39769.630485 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35302.734375 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35302.734375 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39427.745665 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39427.745665 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38798.171276 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38798.171276 # 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Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.540211 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2420.789907 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9306 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3612 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.576412 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.697335 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2024.265560 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 375.671774 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.694475 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2023.389229 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 379.706203 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061776 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011465 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073780 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9092 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.061749 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011588 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073877 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 9238 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9146 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 9292 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12838 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1732 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1732 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12175 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12326 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2243 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 14418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12175 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14569 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12326 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2243 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 14418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253224 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894325 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.279048 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984988 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.984988 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253224 # miss rate for demand accesses +system.cpu.l2cache.overall_accesses::total 14569 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.250527 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.276211 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.250527 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964333 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.363851 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253224 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.360423 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.250527 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964333 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.363851 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35309.601038 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38040.481400 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35662.146893 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38893.610785 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38893.610785 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35309.601038 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38713.361073 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36713.019443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35309.601038 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38713.361073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36713.019443 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::total 0.360423 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35341.806995 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38200.873362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35711.082910 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38910.557185 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38910.557185 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35341.806995 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38760.286639 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36749.952390 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35341.806995 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38760.286639 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36749.952390 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3083 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3540 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3083 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3088 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3546 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3088 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5246 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3083 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3088 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5246 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 98880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15955500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 114835500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60925000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60925000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 175760500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76880500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 175760500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894325 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279048 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984988 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984988 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 99150000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16063500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 115213500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61053000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61053000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99150000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77116500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 176266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99150000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77116500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 176266500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.276211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.363851 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360423 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.363851 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32072.656503 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34913.566740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32439.406780 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35712.192263 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35712.192263 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360423 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32108.160622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35073.144105 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32491.116751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35808.211144 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35808.211144 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index d3e99f110..220e3a05f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118780 # Number of seconds simulated -sim_ticks 118779533000 # Number of ticks simulated -final_tick 118779533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118729 # Number of seconds simulated +sim_ticks 118729316000 # Number of ticks simulated +final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1503058 # Simulator instruction rate (inst/s) -host_op_rate 1503057 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1942616372 # Simulator tick rate (ticks/s) -host_mem_usage 222720 # Number of bytes of host memory used -host_seconds 61.14 # Real time elapsed on the host +host_inst_rate 979371 # Simulator instruction rate (inst/s) +host_op_rate 979371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1265246648 # Simulator tick rate (ticks/s) +host_mem_usage 223148 # Number of bytes of host memory used +host_seconds 93.84 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237559066 # number of cpu cycles simulated +system.cpu.numCycles 237458632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237559066 # Number of busy cycles +system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1417.992791 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1417.992791 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692379 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692379 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229226000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229226000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229226000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229226000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229226000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229226000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26936.075206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26936.075206 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203696000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203696000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203696000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203696000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203696000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203696000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.982871 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.982871 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352047 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352047 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24380000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24380000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121176000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121176000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54510.121457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54510.121457 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22955000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22955000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114507000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114507000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114507000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114507000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2073.981313 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1704.943449 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.242515 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063293 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e95f937b3..e11bd02ec 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.076020 # Number of seconds simulated -sim_ticks 76020082000 # Number of ticks simulated -final_tick 76020082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.075929 # Number of seconds simulated +sim_ticks 75929256000 # Number of ticks simulated +final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108434 # Simulator instruction rate (inst/s) -host_op_rate 118724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47832871 # Simulator tick rate (ticks/s) -host_mem_usage 232824 # Number of bytes of host memory used -host_seconds 1589.29 # Real time elapsed on the host -sim_insts 172333166 # Number of instructions simulated -sim_ops 188686648 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112256 # Number of bytes read from this memory -system.physmem.bytes_read::total 244672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1754 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3823 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1741856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3218518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1741856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1741856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1741856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3218518 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 99785 # Simulator instruction rate (inst/s) +host_op_rate 109254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43964821 # Simulator tick rate (ticks/s) +host_mem_usage 238132 # Number of bytes of host memory used +host_seconds 1727.05 # Real time elapsed on the host +sim_insts 172333091 # Number of instructions simulated +sim_ops 188686573 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112384 # Number of bytes read from this memory +system.physmem.bytes_read::total 245248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 132864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 132864 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2076 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1756 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3832 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1749839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1480115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3229954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1749839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1749839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1749839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1480115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3229954 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,141 +70,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 152040165 # number of cpu cycles simulated +system.cpu.numCycles 151858513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96858484 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76060964 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6563923 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46433794 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44260375 # Number of BTB hits +system.cpu.BPredUnit.lookups 96795637 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76023233 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6554345 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46458722 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44211681 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4475068 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89115 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40665802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388394971 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96858484 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48735443 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82285186 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28468460 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7130109 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9134 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4476295 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89485 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40599440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388212036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96795637 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48687976 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82231847 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28434690 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7095448 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8914 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37715921 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1893970 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151978869 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.797548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37656314 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1885789 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 151799953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799634 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153355 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69866943 45.97% 45.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5495765 3.62% 49.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10729414 7.06% 56.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10452168 6.88% 63.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8790327 5.78% 69.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6826108 4.49% 73.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6308927 4.15% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8362057 5.50% 83.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25147160 16.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69738143 45.94% 45.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5498940 3.62% 49.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10708649 7.05% 56.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10436622 6.88% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8785452 5.79% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6828707 4.50% 73.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6299043 4.15% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8356617 5.51% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25147780 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151978869 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637059 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.554555 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46697521 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5834788 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76594287 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1116884 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21735389 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14843189 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162820 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401520259 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 676254 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21735389 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52210117 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 723485 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 695226 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72137663 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4476989 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 379210260 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 151799953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.637407 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.556406 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46621790 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5807519 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76550031 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109408 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21711205 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14812709 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162826 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401248063 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 743977 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21711205 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52126095 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 710072 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 694282 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72094443 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4463856 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 378978195 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 320036 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3584710 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 642738695 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1615361151 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1597815620 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17545531 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092371 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344646324 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33437 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33435 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12677945 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44005038 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16906133 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5806665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3723076 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 335023972 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55533 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252928025 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 900898 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145168889 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 374298631 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4288 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151978869 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.664232 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759052 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 318341 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3575220 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 642418416 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1614444989 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1596851669 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17593320 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092251 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344326165 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33370 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33366 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12643089 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43991113 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16880527 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5791698 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3695359 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334838724 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55508 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252834206 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 902162 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144982237 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 373879643 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4278 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151799953 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.665575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58441388 38.45% 38.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23049169 15.17% 53.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25167243 16.56% 70.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20506081 13.49% 83.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12879623 8.47% 92.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6582625 4.33% 96.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4058401 2.67% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1110608 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 183731 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58349265 38.44% 38.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22992328 15.15% 53.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25145387 16.56% 70.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20486668 13.50% 83.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12884605 8.49% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6585084 4.34% 96.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4053755 2.67% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1118158 0.74% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 184703 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151978869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151799953 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 958151 37.34% 37.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5590 0.22% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 28 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1196632 46.64% 84.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 405192 15.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 967156 37.45% 37.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5599 0.22% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1198375 46.40% 84.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411308 15.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197423347 78.06% 78.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995576 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197345283 78.05% 78.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 996010 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -223,167 +223,167 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33191 0.01% 78.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 163925 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254716 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467079 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206343 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71849 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39030082 15.43% 94.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14205161 5.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164019 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254959 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76456 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467688 0.18% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206418 0.08% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71860 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39024792 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14193209 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252928025 # Type of FU issued -system.cpu.iq.rate 1.663561 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2565688 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010144 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657530631 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 478025695 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240682393 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3770874 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2241416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1850793 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253600335 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1893378 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2031332 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252834206 # Type of FU issued +system.cpu.iq.rate 1.664933 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2582566 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010214 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657177755 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477646556 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240591983 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3775338 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2248788 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1851684 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253520354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1896418 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2029780 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14149525 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17193 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19478 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4255470 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14135615 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17349 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19653 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4229879 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21735389 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15851 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 335097391 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 841360 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44005038 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16906133 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32986 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 165 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19478 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4108816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3932770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8041586 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245927260 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37410682 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7000765 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21711205 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12896 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334912035 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 838129 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43991113 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16880527 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32938 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 266 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19653 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4103971 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3924992 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8028963 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245839126 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37402304 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6995080 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17886 # number of nop insts executed -system.cpu.iew.exec_refs 51227779 # number of memory reference insts executed -system.cpu.iew.exec_branches 54055496 # Number of branches executed -system.cpu.iew.exec_stores 13817097 # Number of stores executed -system.cpu.iew.exec_rate 1.617515 # Inst execution rate -system.cpu.iew.wb_sent 243665877 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242533186 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150106940 # num instructions producing a value -system.cpu.iew.wb_consumers 269220391 # num instructions consuming a value +system.cpu.iew.exec_nop 17803 # number of nop insts executed +system.cpu.iew.exec_refs 51215601 # number of memory reference insts executed +system.cpu.iew.exec_branches 54034095 # Number of branches executed +system.cpu.iew.exec_stores 13813297 # Number of stores executed +system.cpu.iew.exec_rate 1.618870 # Inst execution rate +system.cpu.iew.wb_sent 243576806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242443667 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150073604 # num instructions producing a value +system.cpu.iew.wb_consumers 269189037 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.595192 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557562 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596510 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557503 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146396335 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6410682 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130243481 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.448833 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.161152 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 146211047 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51230 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6401258 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130088749 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.450556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.162504 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59985952 46.06% 46.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32109376 24.65% 70.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13980234 10.73% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7652770 5.88% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4424001 3.40% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1333573 1.02% 91.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1734640 1.33% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1282307 0.98% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7740628 5.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59880842 46.03% 46.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32046581 24.63% 70.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13987597 10.75% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7657894 5.89% 87.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4414755 3.39% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1334314 1.03% 91.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1737378 1.34% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1284458 0.99% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7744930 5.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130243481 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347554 # Number of instructions committed -system.cpu.commit.committedOps 188701036 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130088749 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347479 # Number of instructions committed +system.cpu.commit.committedOps 188700961 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506176 # Number of memory references committed -system.cpu.commit.loads 29855513 # Number of loads committed +system.cpu.commit.refs 42506146 # Number of memory references committed +system.cpu.commit.loads 29855498 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306340 # Number of branches committed +system.cpu.commit.branches 40306325 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130333 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130273 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7740628 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7744930 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457595023 # The number of ROB reads -system.cpu.rob.rob_writes 692049675 # The number of ROB writes -system.cpu.timesIdled 1805 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61296 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333166 # Number of Instructions Simulated -system.cpu.committedOps 188686648 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333166 # Number of Instructions Simulated -system.cpu.cpi 0.882246 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.882246 # CPI: Total CPI of All Threads -system.cpu.ipc 1.133471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.133471 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092342028 # number of integer regfile reads -system.cpu.int_regfile_writes 388769433 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911784 # number of floating regfile reads -system.cpu.fp_regfile_writes 2509539 # number of floating regfile writes -system.cpu.misc_regfile_reads 474699170 # number of misc regfile reads -system.cpu.misc_regfile_writes 832094 # number of misc regfile writes -system.cpu.icache.replacements 2665 # number of replacements -system.cpu.icache.tagsinuse 1365.695198 # Cycle average of tags in use -system.cpu.icache.total_refs 37710725 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4406 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8558.948025 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457250626 # The number of ROB reads +system.cpu.rob.rob_writes 691654263 # The number of ROB writes +system.cpu.timesIdled 1589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58560 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333091 # Number of Instructions Simulated +system.cpu.committedOps 188686573 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333091 # Number of Instructions Simulated +system.cpu.cpi 0.881192 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881192 # CPI: Total CPI of All Threads +system.cpu.ipc 1.134827 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.134827 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091994433 # number of integer regfile reads +system.cpu.int_regfile_writes 388620965 # number of integer regfile writes +system.cpu.fp_regfile_reads 2912840 # number of floating regfile reads +system.cpu.fp_regfile_writes 2511233 # number of floating regfile writes +system.cpu.misc_regfile_reads 474441039 # number of misc regfile reads +system.cpu.misc_regfile_writes 832064 # number of misc regfile writes +system.cpu.icache.replacements 2657 # number of replacements +system.cpu.icache.tagsinuse 1370.154308 # Cycle average of tags in use +system.cpu.icache.total_refs 37651093 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4401 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8555.122245 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1365.695198 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.666843 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.666843 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37710725 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37710725 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37710725 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37710725 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37710725 # number of overall hits -system.cpu.icache.overall_hits::total 37710725 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5196 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5196 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5196 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5196 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5196 # number of overall misses -system.cpu.icache.overall_misses::total 5196 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114882000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114882000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114882000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114882000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114882000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114882000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37715921 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37715921 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37715921 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37715921 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37715921 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37715921 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000138 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000138 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000138 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000138 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22109.699769 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22109.699769 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22109.699769 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22109.699769 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1370.154308 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.669021 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.669021 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37651093 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37651093 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37651093 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37651093 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37651093 # number of overall hits +system.cpu.icache.overall_hits::total 37651093 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5221 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5221 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5221 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5221 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5221 # number of overall misses +system.cpu.icache.overall_misses::total 5221 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 109554000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 109554000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 109554000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 109554000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 109554000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 109554000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37656314 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37656314 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37656314 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37656314 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37656314 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37656314 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000139 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000139 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000139 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000139 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000139 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000139 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20983.336526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20983.336526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20983.336526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20983.336526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,146 +392,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 790 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 790 # 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number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18278.143441 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18278.143441 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18196.160836 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18196.160836 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18196.160836 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18196.160836 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18196.160836 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18196.160836 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 59 # 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miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36811.179804 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36811.179804 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36974.493769 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36974.493769 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 40250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 40250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36941.627786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36941.627786 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000203 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31819.191919 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31819.191919 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30808.528757 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30808.528757 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31016.696141 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1165 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1165 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6614 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6614 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6550 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6550 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7779 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 776 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 776 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89586000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33945000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33945000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66628500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56902500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 123531000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66628500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56902500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 123531000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.531829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941050 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.611359 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941050 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.611359 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32094.653179 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33711.453744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32494.015234 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31576.744186 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31576.744186 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32094.653179 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32404.612756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32236.691023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32094.653179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32404.612756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32236.691023 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index ee5d7fbdb..fea3635fb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232090 # Number of seconds simulated -sim_ticks 232089948000 # Number of ticks simulated -final_tick 232089948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.232072 # Number of seconds simulated +sim_ticks 232072304000 # Number of ticks simulated +final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108463 # Simulator instruction rate (inst/s) -host_op_rate 1213886 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1497086914 # Simulator tick rate (ticks/s) -host_mem_usage 230968 # Number of bytes of host memory used -host_seconds 155.03 # Real time elapsed on the host +host_inst_rate 603492 # Simulator instruction rate (inst/s) +host_op_rate 660888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 815011792 # Simulator tick rate (ticks/s) +host_mem_usage 237088 # Number of bytes of host memory used +host_seconds 284.75 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 476781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 952183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 952183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 464179896 # number of cpu cycles simulated +system.cpu.numCycles 464144608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 42494119 # nu system.cpu.num_load_insts 29849484 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 464179896 # Number of busy cycles +system.cpu.num_busy_cycles 464144608 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.971530 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.971530 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.560533 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.560533 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115332000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115332000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37801.376598 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.590777 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.590777 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332908 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332908 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 1789 # n system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36195000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36195000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97459000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97459000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97459000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97459000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52532.656023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52532.656023 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54476.802683 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54476.802683 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54476.802683 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1789 system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34128000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34128000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92092000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92092000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92092000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92092000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49532.656023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49532.656023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51476.802683 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51476.802683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.633213 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.038052 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.018140 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.577021 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.051136 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 9d89c8f58..5837aae11 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270629 # Number of seconds simulated -sim_ticks 270628667000 # Number of ticks simulated -final_tick 270628667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.270563 # Number of seconds simulated +sim_ticks 270563082000 # Number of ticks simulated +final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1532509 # Simulator instruction rate (inst/s) -host_op_rate 1532510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2143977461 # Simulator tick rate (ticks/s) -host_mem_usage 235212 # Number of bytes of host memory used -host_seconds 126.23 # Real time elapsed on the host +host_inst_rate 662631 # Simulator instruction rate (inst/s) +host_op_rate 662631 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 926794797 # Simulator tick rate (ticks/s) +host_mem_usage 226156 # Number of bytes of host memory used +host_seconds 291.93 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 230208 # Nu system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541257334 # number of cpu cycles simulated +system.cpu.numCycles 541126164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 541257334 # Number of busy cycles +system.cpu.num_busy_cycles 541126164 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.550018 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.579171 # Cycle average of tags in use system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.550018 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 323106000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 323106000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26294.433594 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.179149 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.179149 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27888000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27888000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60312000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 56000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 56000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 88200000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) @@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -249,18 +249,18 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.289604 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.240623 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.048526 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.081735 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 344b3932c..d3a442923 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,269 +1,269 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084417 # Number of seconds simulated -sim_ticks 84416735500 # Number of ticks simulated -final_tick 84416735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084599 # Number of seconds simulated +sim_ticks 84599483500 # Number of ticks simulated +final_tick 84599483500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63787 # Simulator instruction rate (inst/s) -host_op_rate 106913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40771301 # Simulator tick rate (ticks/s) -host_mem_usage 285396 # Number of bytes of host memory used -host_seconds 2070.49 # Real time elapsed on the host +host_inst_rate 50330 # Simulator instruction rate (inst/s) +host_op_rate 84358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32239425 # Simulator tick rate (ticks/s) +host_mem_usage 239332 # Number of bytes of host memory used +host_seconds 2624.10 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 220032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory -system.physmem.bytes_read::total 344064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219392 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3428 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 344704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3438 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5376 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2598916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4075779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2598916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2598916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2598916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4075779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 5386 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2600867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1473673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4074540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2600867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2600867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2600867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1473673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4074540 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 168833472 # number of cpu cycles simulated +system.cpu.numCycles 169198968 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20699953 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20699953 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2254791 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15116204 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13734495 # Number of BTB hits +system.cpu.BPredUnit.lookups 20690463 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20690463 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2250102 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15079710 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13739283 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27236198 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227395589 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20699953 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13734495 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59717541 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19334489 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64998537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 379 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2980 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25696290 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 472102 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 168753880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.217952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336457 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27218141 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227440359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20690463 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13739283 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59726319 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19306281 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 65395131 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1651 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25701311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 473765 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169122323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.213301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.334482 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 110699150 65.60% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3224321 1.91% 67.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2475319 1.47% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3099058 1.84% 70.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3522120 2.09% 72.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3727832 2.21% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4580737 2.71% 77.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2798912 1.66% 79.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34626431 20.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 111062519 65.67% 65.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3230504 1.91% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2469579 1.46% 69.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3091757 1.83% 70.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3527779 2.09% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3730060 2.21% 75.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4582508 2.71% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2803800 1.66% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34623817 20.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 168753880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122606 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346863 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40114666 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55275027 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46754888 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9811054 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16798245 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365144878 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16798245 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47659212 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14495562 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48366883 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41410934 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355937871 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17144692 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22141197 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 410198872 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 987348929 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977397781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9951148 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169122323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122285 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.344218 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40123368 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55633776 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46741593 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9842729 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16780857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365282924 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16780857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47679812 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14629061 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22937 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48366453 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41643203 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356095908 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17377193 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22149388 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 410376112 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 987879370 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977929387 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9949983 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150770269 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1731 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1722 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89681152 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89661303 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32849139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58579836 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19046101 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343008159 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4651 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 272074168 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 315487 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 121115880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 246174480 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 168753880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.612254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.516605 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 150947509 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1877 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1873 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89979833 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89683170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32866708 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59054771 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19177166 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343137266 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5038 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271920674 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 307949 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 121254430 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 247003349 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3792 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169122323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.607834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.514763 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47246333 28.00% 28.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46593223 27.61% 55.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33100078 19.61% 75.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20197900 11.97% 87.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13442909 7.97% 95.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5008835 2.97% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2434360 1.44% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 576818 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 153424 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47444811 28.05% 28.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46907027 27.74% 55.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33033517 19.53% 75.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20154930 11.92% 87.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13461767 7.96% 95.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4965301 2.94% 98.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2426983 1.44% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 577544 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 150443 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 168753880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169122323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133668 5.05% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2245630 84.89% 89.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 265941 10.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 134207 5.09% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2238473 84.87% 89.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 264949 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212775 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177115116 65.10% 65.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1587982 0.58% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68640688 25.23% 91.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23517607 8.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212573 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177106081 65.13% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1583088 0.58% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68507215 25.19% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23511717 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 272074168 # Type of FU issued -system.cpu.iq.rate 1.611494 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2645239 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009722 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710552167 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 459825601 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264280356 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5310775 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4610743 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2547999 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270845077 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2661555 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19085225 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271920674 # Type of FU issued +system.cpu.iq.rate 1.607106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2637629 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009700 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710614385 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 460072874 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264170911 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5294864 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4624558 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2540762 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270691856 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2653874 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19027871 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33011717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33669 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 313308 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12333423 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33033584 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33172 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306303 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12350992 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49764 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49574 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16798245 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 578433 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 255971 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343012810 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 262853 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89661303 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32849139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1696 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 171518 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 28262 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 313308 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1334034 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1025575 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2359609 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268880206 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67501088 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3193962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16780857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 570141 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 256886 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343142304 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 262882 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89683170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32866708 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1845 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 170649 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30071 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306303 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1331965 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1023841 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2355806 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268743201 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67386869 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3177473 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90609613 # number of memory reference insts executed -system.cpu.iew.exec_branches 14778913 # Number of branches executed -system.cpu.iew.exec_stores 23108525 # Number of stores executed -system.cpu.iew.exec_rate 1.592576 # Inst execution rate -system.cpu.iew.wb_sent 267790153 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266828355 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215466239 # num instructions producing a value -system.cpu.iew.wb_consumers 378707057 # num instructions consuming a value +system.cpu.iew.exec_refs 90490770 # number of memory reference insts executed +system.cpu.iew.exec_branches 14773340 # Number of branches executed +system.cpu.iew.exec_stores 23103901 # Number of stores executed +system.cpu.iew.exec_rate 1.588326 # Inst execution rate +system.cpu.iew.wb_sent 267665043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266711673 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215305025 # num instructions producing a value +system.cpu.iew.wb_consumers 378544002 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.580423 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568952 # average fanout of values written-back +system.cpu.iew.wb_rate 1.576320 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568771 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121732782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121862932 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2255092 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151955635 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.456760 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.933041 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2250269 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 152341466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.453071 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.928588 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52584491 34.61% 34.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57288776 37.70% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13942421 9.18% 81.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11933178 7.85% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4288993 2.82% 92.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2988620 1.97% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1076250 0.71% 94.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 990012 0.65% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6862894 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52729760 34.61% 34.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57497101 37.74% 72.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14043120 9.22% 81.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11929275 7.83% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4291590 2.82% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2949185 1.94% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1071112 0.70% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 989747 0.65% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6840576 4.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151955635 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 152341466 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,70 +274,70 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6862894 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6840576 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488188483 # The number of ROB reads -system.cpu.rob.rob_writes 703031879 # The number of ROB writes -system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79592 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488726782 # The number of ROB reads +system.cpu.rob.rob_writes 703273689 # The number of ROB writes +system.cpu.timesIdled 1665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76645 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.278352 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.278352 # CPI: Total CPI of All Threads -system.cpu.ipc 0.782257 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.782257 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 568126600 # number of integer regfile reads -system.cpu.int_regfile_writes 302940757 # number of integer regfile writes -system.cpu.fp_regfile_reads 3504532 # number of floating regfile reads -system.cpu.fp_regfile_writes 2218521 # number of floating regfile writes -system.cpu.misc_regfile_reads 139578385 # number of misc regfile reads +system.cpu.cpi 1.281119 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.281119 # CPI: Total CPI of All Threads +system.cpu.ipc 0.780567 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.780567 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 567776084 # number of integer regfile reads +system.cpu.int_regfile_writes 302793169 # number of integer regfile writes +system.cpu.fp_regfile_reads 3492670 # number of floating regfile reads +system.cpu.fp_regfile_writes 2212557 # number of floating regfile writes +system.cpu.misc_regfile_reads 139469476 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5271 # number of replacements -system.cpu.icache.tagsinuse 1637.773069 # Cycle average of tags in use -system.cpu.icache.total_refs 25687510 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7238 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3548.979000 # Average number of references to valid blocks. +system.cpu.icache.replacements 5445 # number of replacements +system.cpu.icache.tagsinuse 1641.882453 # Cycle average of tags in use +system.cpu.icache.total_refs 25692314 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7414 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3465.378203 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1637.773069 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.799694 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.799694 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25687510 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25687510 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25687510 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25687510 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25687510 # number of overall hits -system.cpu.icache.overall_hits::total 25687510 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8780 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8780 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8780 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8780 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8780 # number of overall misses -system.cpu.icache.overall_misses::total 8780 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 192794500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 192794500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 192794500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 192794500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 192794500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 192794500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25696290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25696290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25696290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25696290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25696290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25696290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000342 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000342 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000342 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000342 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000342 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21958.371298 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21958.371298 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21958.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21958.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21958.371298 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1641.882453 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.801700 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.801700 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25692314 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25692314 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25692314 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25692314 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25692314 # number of overall hits +system.cpu.icache.overall_hits::total 25692314 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8997 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8997 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8997 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8997 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8997 # number of overall misses +system.cpu.icache.overall_misses::total 8997 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180939500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180939500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180939500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180939500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180939500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180939500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25701311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25701311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25701311 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25701311 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20111.092586 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20111.092586 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,94 +346,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1357 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1357 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 135764500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 135764500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 135764500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 135764500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000289 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000289 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000289 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000289 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 68703636 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34593.975831 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1420.532831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.346810 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.346810 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48246578 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48246578 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513979 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513979 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68760557 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68760557 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66966000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95065500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95065500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95065500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95065500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48247389 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48247389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1423.300553 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.347485 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.347485 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48189408 # 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number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68763119 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68763119 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68763119 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68763119 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 68705957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68705957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68705957 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68705957 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34647.965475 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34647.965475 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38244.431753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38244.431753 # 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average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32180.708181 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37331.190609 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37331.190609 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35713.765337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35713.765337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,138 +444,138 @@ system.cpu.dcache.fast_writes 0 # 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number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1787 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1787 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2212 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2212 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2212 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2212 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14781500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14781500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63139500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 63139500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77921000 # 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average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3428 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 391 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3819 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 184 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3438 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 393 # 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number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1948 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5376 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109517000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12953500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 122470500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5704000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5704000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48730500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48730500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109517000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61684000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 171201000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109517000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61684000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 171201000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.928741 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.498629 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994595 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994595 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.582891 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.473611 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981360 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.582891 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31947.782964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33129.156010 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32068.735271 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31297.687861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31297.687861 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31947.782964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31665.297741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31845.424107 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 5386 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109859500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13039500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 122899000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6951000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6951000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48724500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48724500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109859500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61764000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 171623500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109859500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61764000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 171623500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926887 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.488835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.995556 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.995556 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.572979 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463780 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.572979 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31954.479348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33179.389313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32080.135735 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31334.083601 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31334.083601 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31954.479348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31706.365503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31864.741924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31954.479348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31706.365503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31864.741924 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 2dc96ffd3..82f566301 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250981 # Number of seconds simulated -sim_ticks 250980994000 # Number of ticks simulated -final_tick 250980994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.250954 # Number of seconds simulated +sim_ticks 250953955000 # Number of ticks simulated +final_tick 250953955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540200 # Simulator instruction rate (inst/s) -host_op_rate 905422 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1026566177 # Simulator tick rate (ticks/s) -host_mem_usage 281300 # Number of bytes of host memory used -host_seconds 244.49 # Real time elapsed on the host +host_inst_rate 366685 # Simulator instruction rate (inst/s) +host_op_rate 614596 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 696753053 # Simulator tick rate (ticks/s) +host_mem_usage 236244 # Number of bytes of host memory used +host_seconds 360.18 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 181760 # Nu system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501961988 # number of cpu cycles simulated +system.cpu.numCycles 501907910 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 77165302 # nu system.cpu.num_load_insts 56649586 # Number of load instructions system.cpu.num_store_insts 20515716 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 501961988 # Number of busy cycles +system.cpu.num_busy_cycles 501907910 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.271959 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1455.296654 # Cycle average of tags in use system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.271959 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.710582 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.710582 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1455.296654 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185042500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185042500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185042500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185042500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185042500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185042500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39421.069450 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39421.069450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39421.069450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39421.069450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39421.069450 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170929000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170929000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170929000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170929000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170929000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170929000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.358756 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.358756 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.439047 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1363.457581 # Cycle average of tags in use system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.439047 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332871 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332871 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1363.457581 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits @@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 1905 # n system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88243000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88243000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106263000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106263000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106263000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106263000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) @@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.785805 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.785805 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55781.102362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55781.102362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55781.102362 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,12 +205,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1905 system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83509000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83509000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100547500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 100547500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100547500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 100547500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -221,26 +221,26 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.785805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.785805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.146468 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2058.178702 # Cycle average of tags in use system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.021788 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.948778 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.175901 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.978594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.178364 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.062811 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -265,17 +265,17 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) @@ -300,17 +300,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.905063 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52003.273495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52003.273495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 88df9e22a..23658f386 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,222 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920895 # Number of seconds simulated -sim_ticks 1920895294000 # Number of ticks simulated -final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.914421 # Number of seconds simulated +sim_ticks 1914420945000 # Number of ticks simulated +final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1271848 # Simulator instruction rate (inst/s) -host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43474553061 # Simulator tick rate (ticks/s) -host_mem_usage 295012 # Number of bytes of host memory used -host_seconds 44.18 # Real time elapsed on the host -sim_insts 56195754 # Number of instructions simulated -sim_ops 56195754 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 336257 # number of replacements -system.cpu.l2cache.tagsinuse 65308.063316 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2448454 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401419 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.099497 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.996522 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814985 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1731448 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835257 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835257 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187565 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002550 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1919013 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916463 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002550 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +host_inst_rate 1284205 # Simulator instruction rate (inst/s) +host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43773036105 # Simulator tick rate (ticks/s) +host_mem_usage 295308 # Number of bytes of host memory used +host_seconds 43.74 # Real time elapsed on the host +sim_insts 56164879 # Number of instructions simulated +sim_ops 56164879 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory +system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.347775 # Cycle average of tags in use +system.iocache.tagsinuse 1.347664 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1748614160000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.347664 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084229 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084229 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +57,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11444054806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11444054806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11464727804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11464727804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11464727804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11464727804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +81,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +107,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +123,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +146,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066995 # DTB read hits +system.cpu.dtb.read_hits 9062432 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357563 # DTB write hits +system.cpu.dtb.write_hits 6354530 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15424558 # DTB hits +system.cpu.dtb.data_hits 15416962 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975749 # ITB hits +system.cpu.itb.fetch_hits 4974475 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980755 # ITB accesses +system.cpu.itb.fetch_accesses 4979481 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +174,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3841790588 # number of cpu cycles simulated +system.cpu.numCycles 3828841890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195754 # Number of instructions committed -system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses +system.cpu.committedInsts 56164879 # Number of instructions committed +system.cpu.committedOps 56164879 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52037464 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483816 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066962 # number of integer instructions +system.cpu.num_func_calls 1482804 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6466141 # number of instructions that are conditional controls +system.cpu.num_int_insts 52037464 # number of integer instructions system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written +system.cpu.num_int_register_reads 71294843 # number of times the integer registers were read +system.cpu.num_int_register_writes 38508157 # number of times the integer registers were written system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15477180 # number of memory refs -system.cpu.num_load_insts 9103852 # Number of load instructions -system.cpu.num_store_insts 6373328 # Number of store instructions -system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles -system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles -system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933642 # Percentage of idle cycles +system.cpu.num_mem_refs 15469580 # number of memory refs +system.cpu.num_load_insts 9099291 # Number of load instructions +system.cpu.num_store_insts 6370289 # Number of store instructions +system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles +system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles +system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.937415 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814135 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -427,29 +257,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175957 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193009 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.callpal::total 192901 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1864235249000 97.38% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -482,51 +312,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 929101 # number of replacements -system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use -system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits -system.cpu.icache.overall_hits::total 55277821 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses -system.cpu.icache.overall_misses::total 929772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56207593 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56207593 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56207593 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56207593 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.572596 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14903.572596 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14903.572596 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14903.572596 # average overall miss latency +system.cpu.icache.replacements 927876 # number of replacements +system.cpu.icache.tagsinuse 508.762321 # Cycle average of tags in use +system.cpu.icache.total_refs 55248171 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928387 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.509850 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 35489468000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 508.762321 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993676 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993676 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55248171 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55248171 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55248171 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55248171 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55248171 # number of overall hits +system.cpu.icache.overall_hits::total 55248171 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928547 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928547 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928547 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928547 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928547 # number of overall misses +system.cpu.icache.overall_misses::total 928547 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12629515000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12629515000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12629515000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12629515000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12629515000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12629515000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56176718 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56176718 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56176718 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56176718 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56176718 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56176718 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016529 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016529 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016529 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016529 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016529 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016529 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13601.373975 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13601.373975 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13601.373975 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13601.373975 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,104 +365,104 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4a0324f9e..07e356a30 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629150 # Number of seconds simulated -sim_ticks 2629149747000 # Number of ticks simulated -final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.624688 # Number of seconds simulated +sim_ticks 2624688029000 # Number of ticks simulated +final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 556259 # Simulator instruction rate (inst/s) -host_op_rate 707830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24290841486 # Simulator tick rate (ticks/s) -host_mem_usage 380276 # Number of bytes of host memory used -host_seconds 108.24 # Real time elapsed on the host -sim_insts 60207390 # Number of instructions simulated -sim_ops 76612873 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory -system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 388710 # Simulator instruction rate (inst/s) +host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16947208284 # Simulator tick rate (ticks/s) +host_mem_usage 385844 # Number of bytes of host memory used +host_seconds 154.87 # Real time elapsed on the host +sim_insts 60201138 # Number of instructions simulated +sim_ops 76605123 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,244 +23,44 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 62933 # number of replacements -system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.791359 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226888 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 596416 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 596416 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113846 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484154 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8836 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844195 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484154 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340734 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10261 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20880 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2845 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10613 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144085 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154704 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10613 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144085 # number of overall misses -system.cpu.l2cache.overall_misses::total 154704 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8049111500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1495438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1495438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103451 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103451 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58379 # number of writebacks -system.cpu.l2cache.writebacks::total 58379 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154704 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory +system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -307,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14998169 # DTB read hits -system.cpu.dtb.read_misses 7372 # DTB read misses -system.cpu.dtb.write_hits 11231565 # DTB write hits -system.cpu.dtb.write_misses 2270 # DTB write misses +system.cpu.dtb.read_hits 14996726 # DTB read hits +system.cpu.dtb.read_misses 7357 # DTB read misses +system.cpu.dtb.write_hits 11231612 # DTB write hits +system.cpu.dtb.write_misses 2211 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15005541 # DTB read accesses -system.cpu.dtb.write_accesses 11233835 # DTB write accesses +system.cpu.dtb.read_accesses 15004083 # DTB read accesses +system.cpu.dtb.write_accesses 11233823 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26229734 # DTB hits -system.cpu.dtb.misses 9642 # DTB misses -system.cpu.dtb.accesses 26239376 # DTB accesses -system.cpu.itb.inst_hits 61501359 # ITB inst hits +system.cpu.dtb.hits 26228338 # DTB hits +system.cpu.dtb.misses 9568 # DTB misses +system.cpu.dtb.accesses 26237906 # DTB accesses +system.cpu.itb.inst_hits 61495107 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +105,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61505830 # ITB inst accesses -system.cpu.itb.hits 61501359 # DTB hits +system.cpu.itb.inst_accesses 61499578 # ITB inst accesses +system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61505830 # DTB accesses -system.cpu.numCycles 5258299494 # number of cpu cycles simulated +system.cpu.itb.accesses 61499578 # DTB accesses +system.cpu.numCycles 5249376058 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60207390 # Number of instructions committed -system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses +system.cpu.committedInsts 60201138 # Number of instructions committed +system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140176 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948958 # number of instructions that are conditional controls -system.cpu.num_int_insts 68878830 # number of integer instructions +system.cpu.num_func_calls 2139913 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read -system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written +system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27397151 # number of memory refs -system.cpu.num_load_insts 15662227 # Number of load instructions -system.cpu.num_store_insts 11734924 # Number of store instructions -system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles -system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles -system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.868680 # Percentage of idle cycles +system.cpu.num_mem_refs 27395681 # number of memory refs +system.cpu.num_load_insts 15660705 # Number of load instructions +system.cpu.num_store_insts 11734976 # Number of store instructions +system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles +system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles +system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.871278 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83013 # number of quiesce instructions executed -system.cpu.icache.replacements 855930 # number of replacements -system.cpu.icache.tagsinuse 510.898307 # Cycle average of tags in use -system.cpu.icache.total_refs 60644917 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856442 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.810302 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19819985000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.898307 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997848 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997848 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60644917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60644917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60644917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60644917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60644917 # number of overall hits -system.cpu.icache.overall_hits::total 60644917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856442 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856442 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856442 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856442 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856442 # number of overall misses -system.cpu.icache.overall_misses::total 856442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12566277500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12566277500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12566277500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12566277500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12566277500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12566277500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61501359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61501359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61501359 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61501359 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61501359 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61501359 # number of overall (read+write) accesses +system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed +system.cpu.icache.replacements 855878 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595968 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52124.682054 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52050.669507 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.082564 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52065.687511 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52065.687511 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 57452 # number of writebacks +system.cpu.l2cache.writebacks::total 57452 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20481 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133176 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133176 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143034 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153657 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425853000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394738000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820911000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115017000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115017000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5335717000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5335717000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425853000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5730455000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6156628000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 944044d4e..358803d5d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,264 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196023 # Number of seconds simulated -sim_ticks 5196022575000 # Number of ticks simulated -final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.187896 # Number of seconds simulated +sim_ticks 5187896410000 # Number of ticks simulated +final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1315892 # Simulator instruction rate (inst/s) -host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53344387183 # Simulator tick rate (ticks/s) -host_mem_usage 354072 # Number of bytes of host memory used -host_seconds 97.41 # Real time elapsed on the host -sim_insts 128174734 # Number of instructions simulated -sim_ops 247089109 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory +host_inst_rate 834857 # Simulator instruction rate (inst/s) +host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33766110220 # Simulator tick rate (ticks/s) +host_mem_usage 354356 # Number of bytes of host memory used +host_seconds 153.64 # Real time elapsed on the host +sim_insts 128269216 # Number of instructions simulated +sim_ops 247270559 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory -system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory -system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory +system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 826944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8107200 # Number of bytes written to this memory +system.physmem.bytes_written::total 8107200 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44802 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140567 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126675 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126675 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 552696 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1734092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2446248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1562714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1562714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1562714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 552696 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 86330 # number of replacements -system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543462 # 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number of overall hits -system.cpu.l2cache.overall_hits::total 2268886 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41237 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1338 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 112514 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140867 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153751 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.bw_total::cpu.inst 159399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1734092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4008962 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 47503 # number of replacements -system.iocache.tagsinuse 0.108744 # Cycle average of tags in use +system.iocache.tagsinuse 0.106662 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy +system.iocache.warmup_cycle 5044925516000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.106662 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006666 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006666 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses system.iocache.ReadReq_misses::total 838 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -267,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129993932 # 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average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -317,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +146,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10392045150 # number of cpu cycles simulated +system.cpu.numCycles 10375792820 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128174734 # Number of instructions committed -system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses +system.cpu.committedInsts 128269216 # Number of instructions committed +system.cpu.committedOps 247270559 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232005526 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls -system.cpu.num_int_insts 231827885 # number of integer instructions +system.cpu.num_conditional_control_insts 23152914 # number of instructions that are conditional controls +system.cpu.num_int_insts 232005526 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read -system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written +system.cpu.num_int_register_reads 567048885 # number of times the integer registers were read +system.cpu.num_int_register_writes 293217624 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22210252 # number of memory refs -system.cpu.num_load_insts 13855140 # Number of load instructions -system.cpu.num_store_insts 8355112 # Number of store instructions -system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles -system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940780 # Percentage of idle cycles +system.cpu.num_mem_refs 22238817 # number of memory refs +system.cpu.num_load_insts 13875768 # Number of load instructions +system.cpu.num_store_insts 8363049 # Number of store instructions +system.cpu.num_idle_cycles 9774979498.742117 # Number of idle cycles +system.cpu.num_busy_cycles 600813321.257884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057905 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942095 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790545 # number of replacements -system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use -system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits -system.cpu.icache.overall_hits::total 144363546 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses -system.cpu.icache.overall_misses::total 791064 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency +system.cpu.icache.replacements 793131 # number of replacements +system.cpu.icache.tagsinuse 510.350730 # Cycle average of tags in use +system.cpu.icache.total_refs 144484487 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 793643 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.052241 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 160314386000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.350730 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996779 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996779 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144484487 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144484487 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144484487 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144484487 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144484487 # number of overall hits +system.cpu.icache.overall_hits::total 144484487 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 793650 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 793650 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 793650 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 793650 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 793650 # number of overall misses +system.cpu.icache.overall_misses::total 793650 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10860662000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10860662000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10860662000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10860662000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10860662000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10860662000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145278137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145278137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145278137 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145278137 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145278137 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145278137 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13684.447804 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13684.447804 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13684.447804 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13684.447804 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,80 +223,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793650 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 793650 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 793650 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793650 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793650 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793650 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9273362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9273362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9273362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9273362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9273362000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9273362000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005463 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005463 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005463 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.447804 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.447804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3550 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3599 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.063919 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7874 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3610 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.181163 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5162043257000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.063919 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191495 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191495 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7876 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7876 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7878 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7878 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7878 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7878 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43455000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43455000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43455000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43455000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43455000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43455000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12331 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12331 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361285 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361285 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361226 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.361226 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361226 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.361226 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9754.208754 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9754.208754 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9754.208754 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,78 +305,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4455 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4455 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4455 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4455 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4455 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4455 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34545000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34545000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34545000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34545000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34545000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34545000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361285 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361285 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361226 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361226 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7754.208754 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7810 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7423 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.046109 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13594 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7438 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.827642 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5159593477000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.046109 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315382 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315382 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13598 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13598 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13598 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13598 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13598 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13598 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8635 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8635 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8635 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8635 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8635 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8635 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91582000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91582000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91582000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 91582000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91582000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 91582000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22233 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22233 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22233 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22233 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22233 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22233 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.388387 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.388387 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.388387 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.388387 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.388387 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.388387 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10605.906196 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10605.906196 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10605.906196 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,90 +385,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2904 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2904 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8635 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8635 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8635 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8635 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8635 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8635 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74312000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74312000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74312000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74312000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74312000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74312000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.388387 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.388387 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.388387 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8605.906196 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622132 # number of replacements -system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use -system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1618325 # number of replacements +system.cpu.dcache.tagsinuse 511.997377 # Cycle average of tags in use +system.cpu.dcache.total_refs 20032981 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1618837 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.374922 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 43788000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997377 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits -system.cpu.dcache.overall_hits::total 20001854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses -system.cpu.dcache.overall_misses::total 1624858 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11992560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11992560 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8038236 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8038236 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20030796 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20030796 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20030796 # number of overall hits +system.cpu.dcache.overall_hits::total 20030796 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306270 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306270 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314797 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314797 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621067 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses +system.cpu.dcache.overall_misses::total 1621067 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8353033 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21651863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21651863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21651863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21651863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098224 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098224 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037687 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037687 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,46 +477,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks -system.cpu.dcache.writebacks::total 1539490 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315369 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1624858 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1624858 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1624858 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1624858 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15957199501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15957199501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8399992000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8399992000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24357191501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24357191501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24357191501 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305699000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021630 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811218 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811218 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362308 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362308 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9447623bf..ba49bebdd 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21979500 # Number of ticks simulated -final_tick 21979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21628500 # Number of ticks simulated +final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39186 # Simulator instruction rate (inst/s) -host_op_rate 39182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134757534 # Simulator tick rate (ticks/s) -host_mem_usage 222636 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 48865 # Simulator instruction rate (inst/s) +host_op_rate 48859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165354272 # Simulator tick rate (ticks/s) +host_mem_usage 218640 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 876453059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 489183102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1365636161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 876453059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 876453059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 876453059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 489183102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1365636161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43960 # number of cpu cycles simulated +system.cpu.numCycles 43258 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1606 # Number of BP lookups @@ -90,12 +90,12 @@ system.cpu.execution_unit.executions 4463 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 12066 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 536 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36556 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7404 # Number of cycles cpu stages are processed. -system.cpu.activity 16.842584 # Percentage of cycles cpu is active +system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7403 # Number of cycles cpu stages are processed. +system.cpu.activity 17.113597 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -107,34 +107,34 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.879499 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.879499 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145359 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.145359 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 39048 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.173794 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40082 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.821656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39789 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.488171 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 42620 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.048226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 39501 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4459 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.143312 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.677707 # Cycle average of tags in use +system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use system.cpu.icache.total_refs 557 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.677707 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits @@ -149,12 +149,12 @@ system.cpu.icache.demand_misses::cpu.inst 351 # n system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses system.cpu.icache.overall_misses::total 351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19781500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19781500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19781500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19781500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19781500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19781500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses @@ -167,12 +167,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56357.549858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56357.549858 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -193,34 +193,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16493500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16493500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.489186 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.489186 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025022 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025022 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits @@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses system.cpu.dcache.overall_misses::total 348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5918000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5918000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15290000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15290000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21208000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21208000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21208000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21208000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -261,20 +261,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60942.528736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60942.528736 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1689000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits @@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5509500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9606000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9606000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9606000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9606000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,23 +309,23 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 194.900917 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.748296 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.152621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16152000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21542000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16152000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9397500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25549500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16152000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9397500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25549500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12487000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4239000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16726000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3129500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3129500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12487000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7368500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19855500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12487000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7368500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19855500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1a124af36..1c9a49b18 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12735500 # Number of ticks simulated -final_tick 12735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12394500 # Number of ticks simulated +final_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33074 # Simulator instruction rate (inst/s) -host_op_rate 33071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66088952 # Simulator tick rate (ticks/s) -host_mem_usage 223664 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 52290 # Simulator instruction rate (inst/s) +host_op_rate 52282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101684511 # Simulator tick rate (ticks/s) +host_mem_usage 219660 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory system.physmem.bytes_read::total 31296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory system.physmem.num_reads::total 489 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1572926073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 884456833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2457382906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1572926073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1572926073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1572926073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 884456833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2457382906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1978 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 1990 # DTB read hits +system.cpu.dtb.read_misses 56 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2033 # DTB read accesses -system.cpu.dtb.write_hits 1077 # DTB write hits -system.cpu.dtb.write_misses 31 # DTB write misses +system.cpu.dtb.read_accesses 2046 # DTB read accesses +system.cpu.dtb.write_hits 1084 # DTB write hits +system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1108 # DTB write accesses -system.cpu.dtb.data_hits 3055 # DTB hits +system.cpu.dtb.write_accesses 1114 # DTB write accesses +system.cpu.dtb.data_hits 3074 # DTB hits system.cpu.dtb.data_misses 86 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3141 # DTB accesses -system.cpu.itb.fetch_hits 2292 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 3160 # DTB accesses +system.cpu.itb.fetch_hits 2336 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2332 # ITB accesses +system.cpu.itb.fetch_accesses 2374 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +60,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 25472 # number of cpu cycles simulated +system.cpu.numCycles 24790 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2810 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1639 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 544 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 764 # Number of BTB hits +system.cpu.BPredUnit.lookups 2873 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 76 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8490 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16101 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1164 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2877 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1816 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 977 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2292 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14359 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.121318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.516372 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16442 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2336 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11482 79.96% 79.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 290 2.02% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 231 1.61% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 230 1.60% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 264 1.84% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 193 1.34% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 266 1.85% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 182 1.27% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 8.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14359 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.110317 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632106 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1012 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2694 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1150 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2739 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14902 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1150 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9643 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 342 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 379 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2542 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 303 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14192 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2589 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 256 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10635 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17782 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17765 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6065 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 736 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2623 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1340 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. +system.cpu.rename.skidInsts 728 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12668 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10483 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5989 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3489 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10578 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14359 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.730065 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.362537 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9920 69.09% 69.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1630 11.35% 80.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1188 8.27% 88.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 708 4.93% 93.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 458 3.19% 96.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 268 1.87% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 142 0.99% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 31 0.22% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14359 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 7.21% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 64 57.66% 64.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 35.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7098 67.71% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2226 21.23% 88.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 11.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10483 # Type of FU issued -system.cpu.iq.rate 0.411550 # Inst issue rate -system.cpu.iq.fu_busy_cnt 111 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010589 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18693 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9514 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10578 # Type of FU issued +system.cpu.iq.rate 0.426704 # Inst issue rate +system.cpu.iq.fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10581 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1440 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 475 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1150 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2623 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1340 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 149 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 397 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 546 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9926 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2044 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 557 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3155 # number of memory reference insts executed -system.cpu.iew.exec_branches 1608 # Number of branches executed -system.cpu.iew.exec_stores 1111 # Number of stores executed -system.cpu.iew.exec_rate 0.389683 # Inst execution rate -system.cpu.iew.wb_sent 9680 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5005 # num instructions producing a value -system.cpu.iew.wb_consumers 6736 # num instructions consuming a value +system.cpu.iew.exec_refs 3174 # number of memory reference insts executed +system.cpu.iew.exec_branches 1621 # Number of branches executed +system.cpu.iew.exec_stores 1117 # Number of stores executed +system.cpu.iew.exec_rate 0.403066 # Inst execution rate +system.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9591 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5054 # num instructions producing a value +system.cpu.iew.wb_consumers 6863 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.373901 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.743023 # average fanout of values written-back +system.cpu.iew.wb_rate 0.386890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6396 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 461 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.483685 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.282622 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10366 78.48% 78.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1544 11.69% 90.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 533 4.04% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 227 1.72% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.24% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.80% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 105 0.79% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 30 0.23% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 134 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,70 +308,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 134 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25509 # The number of ROB reads -system.cpu.rob.rob_writes 26731 # The number of ROB writes -system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25250 # The number of ROB reads +system.cpu.rob.rob_writes 27045 # The number of ROB writes +system.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 3.997489 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.997489 # CPI: Total CPI of All Threads -system.cpu.ipc 0.250157 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.250157 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12615 # number of integer regfile reads -system.cpu.int_regfile_writes 7161 # number of integer regfile writes +system.cpu.cpi 3.890458 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads +system.cpu.ipc 0.257039 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12699 # number of integer regfile reads +system.cpu.int_regfile_writes 7211 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 158.802415 # Cycle average of tags in use -system.cpu.icache.total_refs 1839 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.856688 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use +system.cpu.icache.total_refs 1881 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 158.802415 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077540 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1839 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1839 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1839 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1839 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1839 # number of overall hits -system.cpu.icache.overall_hits::total 1839 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses -system.cpu.icache.overall_misses::total 453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16260000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16260000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16260000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16260000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16260000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16260000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2292 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2292 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2292 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2292 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197644 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.197644 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197644 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.197644 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197644 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.197644 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35894.039735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35894.039735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35894.039735 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32758.785942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36514.204545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34110.429448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32758.785942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36514.204545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34110.429448 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.974359 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33937.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35301.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35301.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 6a791ec60..aa2f4f81d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 34409000 # Number of ticks simulated -final_tick 34409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 32544000 # Number of ticks simulated +final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55813 # Simulator instruction rate (inst/s) -host_op_rate 55804 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 300451871 # Simulator tick rate (ticks/s) -host_mem_usage 222640 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 68117 # Simulator instruction rate (inst/s) +host_op_rate 68101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 346770993 # Simulator tick rate (ticks/s) +host_mem_usage 218620 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 517074021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312476387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 829550408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517074021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517074021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517074021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312476387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 829550408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 68818 # number of cpu cycles simulated +system.cpu.numCycles 65088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 68818 # Number of busy cycles +system.cpu.num_busy_cycles 65088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 128.208060 # Cycle average of tags in use +system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 128.208060 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062602 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062602 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.892123 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.892123 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025364 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025364 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.769601 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 128.220906 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.548695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003913 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001726 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005639 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d53f6132a..7f4e477cc 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7252000 # Number of ticks simulated -final_tick 7252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7079000 # Number of ticks simulated +final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57662 # Simulator instruction rate (inst/s) -host_op_rate 57638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175044086 # Simulator tick rate (ticks/s) -host_mem_usage 217908 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 8209 # Simulator instruction rate (inst/s) +host_op_rate 8209 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24342914 # Simulator tick rate (ticks/s) +host_mem_usage 218360 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1659128516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 750137893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2409266409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1659128516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1659128516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1659128516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 750137893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2409266409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 13 # DTB read misses +system.cpu.dtb.read_misses 34 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 725 # DTB read accesses -system.cpu.dtb.write_hits 368 # DTB write hits -system.cpu.dtb.write_misses 15 # DTB write misses +system.cpu.dtb.read_accesses 746 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 383 # DTB write accesses -system.cpu.dtb.data_hits 1080 # DTB hits -system.cpu.dtb.data_misses 28 # DTB misses +system.cpu.dtb.write_accesses 387 # DTB write accesses +system.cpu.dtb.data_hits 1079 # DTB hits +system.cpu.dtb.data_misses 54 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1108 # DTB accesses -system.cpu.itb.fetch_hits 1014 # ITB hits +system.cpu.dtb.data_accesses 1133 # DTB accesses +system.cpu.itb.fetch_hits 1015 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1044 # ITB accesses +system.cpu.itb.fetch_accesses 1045 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,183 +60,183 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14505 # number of cpu cycles simulated +system.cpu.numCycles 14159 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 1131 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 573 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 253 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 782 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 218 # Number of BTB hits +system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 211 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6900 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 429 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1183 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 857 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264 # Number of cycles fetch has spent blocked +system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 948 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1014 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 172 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.939926 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.361375 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6158 83.89% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 50 0.68% 84.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.76% 86.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 101 1.38% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 139 1.89% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 62 0.84% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 66 0.90% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 61 0.83% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 575 7.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077973 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.475698 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5395 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 291 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1141 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 501 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6151 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 501 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5491 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 174 # count of cycles rename stalled for serializing inst +system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1058 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5908 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4280 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6676 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6664 # Number of integer rename lookups +system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2512 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 145 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5051 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued +system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7341 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.548427 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.241979 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5680 77.37% 77.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 617 8.40% 85.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 387 5.27% 91.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 273 3.72% 94.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 198 2.70% 97.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 114 1.55% 99.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56 0.76% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.14% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 6 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.88% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 41.46% 46.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 53.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2876 71.44% 71.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 761 18.90% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 388 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4026 # Type of FU issued -system.cpu.iq.rate 0.277559 # Inst issue rate -system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010184 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15500 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7558 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4054 # Type of FU issued +system.cpu.iq.rate 0.286320 # Inst issue rate +system.cpu.iq.fu_busy_cnt 43 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4060 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed @@ -247,57 +247,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 501 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5407 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 150 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3874 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 152 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 350 # number of nop insts executed -system.cpu.iew.exec_refs 1109 # number of memory reference insts executed -system.cpu.iew.exec_branches 649 # Number of branches executed -system.cpu.iew.exec_stores 383 # Number of stores executed -system.cpu.iew.exec_rate 0.267080 # Inst execution rate -system.cpu.iew.wb_sent 3756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3694 # cumulative count of insts written-back +system.cpu.iew.exec_nop 342 # number of nop insts executed +system.cpu.iew.exec_refs 1134 # number of memory reference insts executed +system.cpu.iew.exec_branches 652 # Number of branches executed +system.cpu.iew.exec_stores 387 # Number of stores executed +system.cpu.iew.exec_rate 0.275019 # Inst execution rate +system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3708 # cumulative count of insts written-back system.cpu.iew.wb_producers 1740 # num instructions producing a value -system.cpu.iew.wb_consumers 2202 # num instructions consuming a value +system.cpu.iew.wb_consumers 2258 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.254671 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790191 # average fanout of values written-back +system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2822 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.225423 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5956 87.08% 87.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 217 3.17% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 4.65% 94.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.68% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 0.98% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 47 0.69% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.47% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 21 0.31% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,69 +308,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11924 # The number of ROB reads -system.cpu.rob.rob_writes 11305 # The number of ROB writes -system.cpu.timesIdled 172 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7164 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11671 # The number of ROB reads +system.cpu.rob.rob_writes 11260 # The number of ROB writes +system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.076665 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.076665 # CPI: Total CPI of All Threads -system.cpu.ipc 0.164564 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.164564 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4677 # number of integer regfile reads -system.cpu.int_regfile_writes 2861 # number of integer regfile writes +system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads +system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4712 # number of integer regfile reads +system.cpu.int_regfile_writes 2874 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 94.201337 # Cycle average of tags in use -system.cpu.icache.total_refs 769 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use +system.cpu.icache.total_refs 767 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.090426 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 94.201337 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045997 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045997 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 769 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 769 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 769 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 769 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 769 # number of overall hits -system.cpu.icache.overall_hits::total 769 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 245 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 245 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 245 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 245 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 245 # number of overall misses -system.cpu.icache.overall_misses::total 245 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 9112500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 9112500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 9112500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 9112500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 9112500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 9112500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1014 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1014 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241617 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.241617 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.241617 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.241617 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.241617 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.241617 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37193.877551 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37193.877551 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37193.877551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37193.877551 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits +system.cpu.icache.overall_hits::total 767 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses +system.cpu.icache.overall_misses::total 248 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1015 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1015 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1015 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244335 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.244335 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.244335 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.244335 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.244335 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.244335 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36354.838710 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,94 +379,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6932500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6932500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6932500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6932500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6932500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6932500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185404 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.185404 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.185404 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36875 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36875 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6948500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6948500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185222 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.851495 # Cycle average of tags in use -system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.970482 # Cycle average of tags in use +system.cpu.dcache.total_refs 773 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.094118 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.851495 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011194 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011194 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits -system.cpu.dcache.overall_hits::total 774 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 773 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 773 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 773 # number of overall hits +system.cpu.dcache.overall_hits::total 773 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses -system.cpu.dcache.overall_misses::total 199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4328500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4328500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3561500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3561500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7890000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7890000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7890000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7890000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses +system.cpu.dcache.overall_misses::total 202 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4078500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4078500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3119500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3119500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7198000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7198000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7198000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7198000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 681 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 973 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 973 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 973 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 973 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.204522 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.204522 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.204522 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.204522 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36682.203390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36682.203390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43969.135802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43969.135802 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39648.241206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39648.241206 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,14 +475,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -491,42 +491,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 981000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3492500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3492500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3492500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3492500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089838 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089838 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087359 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087359 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41172.131148 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41172.131148 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 123.109780 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 94.284624 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.825156 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002877 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000880 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6740500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2447000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9187500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 950000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6740500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6740500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3397000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10137500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -571,17 +571,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35853.723404 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40114.754098 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36897.590361 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39583.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37133.699634 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37133.699634 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,17 +601,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6136500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2258000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8394500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 876000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 876000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3134000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9270500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3134000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9270500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -623,17 +623,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.957447 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37016.393443 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33712.851406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index aabb78aae..83ebc2ad9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17541000 # Number of ticks simulated -final_tick 17541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16524000 # Number of ticks simulated +final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207586 # Simulator instruction rate (inst/s) -host_op_rate 207300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1409208031 # Simulator tick rate (ticks/s) -host_mem_usage 216876 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 93431 # Simulator instruction rate (inst/s) +host_op_rate 93371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 598358642 # Simulator tick rate (ticks/s) +host_mem_usage 217312 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 594720940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299184767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 893905707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 594720940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 594720940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 594720940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299184767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 893905707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 35082 # number of cpu cycles simulated +system.cpu.numCycles 33048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 35082 # Number of busy cycles +system.cpu.num_busy_cycles 33048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.027768 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.050296 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 80.027768 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.039076 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.039076 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.039087 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.439715 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 47.439715 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011582 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011582 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.121835 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 80.139278 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.982557 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003269 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 96198ee3a..cbe28c826 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10738000 # Number of ticks simulated -final_tick 10738000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 10412000 # Number of ticks simulated +final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28410 # Simulator instruction rate (inst/s) -host_op_rate 35442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66366492 # Simulator tick rate (ticks/s) -host_mem_usage 227572 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 32172 # Simulator instruction rate (inst/s) +host_op_rate 40134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72868464 # Simulator tick rate (ticks/s) +host_mem_usage 233868 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7936 # Number of bytes read from this memory -system.physmem.bytes_read::total 25728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1656919352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 739057553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2395976904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1656919352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 739057553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2395976904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -115,243 +115,243 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 21477 # number of cpu cycles simulated +system.cpu.numCycles 20825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2491 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1789 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1964 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.lookups 2492 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6988 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12142 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 958 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2639 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1622 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2325 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.169334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.586059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10418 79.79% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223 1.71% 81.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 193 1.48% 82.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 1.66% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.60% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.18% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 109 0.83% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 131 1.00% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115985 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.565349 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7128 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 89 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 945 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2432 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13276 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7383 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12436 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 239 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12439 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56552 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56280 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2229 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6758 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 47 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 766 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2732 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 47 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11190 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 47 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8841 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5157 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13057 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.677108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.355722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9364 71.72% 71.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1488 11.40% 83.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 792 6.07% 89.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 545 4.17% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 428 3.28% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 276 2.11% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 114 0.87% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 42 0.32% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13057 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.88% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 136 63.85% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 73 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5345 60.46% 60.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2263 25.60% 86.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1222 13.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8841 # Type of FU issued -system.cpu.iq.rate 0.411650 # Inst issue rate -system.cpu.iq.fu_busy_cnt 213 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024092 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31043 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16402 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7990 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8838 # Type of FU issued +system.cpu.iq.rate 0.424394 # Inst issue rate +system.cpu.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9034 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1531 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 653 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11245 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2732 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8445 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3250 # number of memory reference insts executed -system.cpu.iew.exec_branches 1412 # Number of branches executed -system.cpu.iew.exec_stores 1169 # Number of stores executed -system.cpu.iew.exec_rate 0.393211 # Inst execution rate -system.cpu.iew.wb_sent 8142 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8006 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3825 # num instructions producing a value -system.cpu.iew.wb_consumers 7724 # num instructions consuming a value +system.cpu.iew.exec_refs 3246 # number of memory reference insts executed +system.cpu.iew.exec_branches 1415 # Number of branches executed +system.cpu.iew.exec_stores 1167 # Number of stores executed +system.cpu.iew.exec_rate 0.404994 # Inst execution rate +system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3850 # num instructions producing a value +system.cpu.iew.wb_consumers 7766 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.372771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495210 # average fanout of values written-back +system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5517 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12113 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.473376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.288273 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9737 80.38% 80.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1166 9.63% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 419 3.46% 93.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 269 2.22% 95.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 155 1.28% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 162 1.34% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 54 0.45% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.32% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 112 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -362,69 +362,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 112 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23095 # The number of ROB reads -system.cpu.rob.rob_writes 23459 # The number of ROB writes -system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22290 # The number of ROB reads +system.cpu.rob.rob_writes 23328 # The number of ROB writes +system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.672977 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.672977 # CPI: Total CPI of All Threads -system.cpu.ipc 0.213996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.213996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38788 # number of integer regfile reads -system.cpu.int_regfile_writes 7902 # number of integer regfile writes +system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 38756 # number of integer regfile reads +system.cpu.int_regfile_writes 7886 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15082 # number of misc regfile reads +system.cpu.misc_regfile_reads 15116 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 149.911543 # Cycle average of tags in use -system.cpu.icache.total_refs 1558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.210702 # Average number of references to valid blocks. +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use +system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.911543 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073199 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1558 # number of overall hits -system.cpu.icache.overall_hits::total 1558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1931 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193164 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193164 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193164 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193164 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35747.989276 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35747.989276 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35747.989276 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits +system.cpu.icache.overall_hits::total 1564 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,110 +433,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 74 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 74 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 74 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10560500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10560500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.154842 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35319.397993 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35319.397993 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # 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Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021229 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2329 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2329 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2329 # number of overall hits -system.cpu.dcache.overall_hits::total 2329 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits +system.cpu.dcache.overall_hits::total 2306 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7113500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7113500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12639500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19753000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19753000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19753000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19753000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1918 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2831 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2831 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2831 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2831 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.099583 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.099583 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.177323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.177323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.177323 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.177323 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37243.455497 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37243.455497 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40641.479100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40641.479100 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39348.605578 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,124 +545,124 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055266 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.052278 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.052278 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34834.905660 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34834.905660 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40666.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40666.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36489.864865 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36489.864865 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.052350 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.052350 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40476.190476 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40476.190476 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 187.774695 # Cycle average of tags in use -system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 360 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.108333 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.003042 # Cycle average of tags in use +system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 141.174021 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.600674 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001422 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005730 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::cpu.inst 141.702568 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.300474 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004324 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001413 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.936455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.903704 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.907731 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.936455 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.864865 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.912752 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.936455 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.864865 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.912752 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36105.357143 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39779.069767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36968.579235 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39535.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37232.843137 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37232.843137 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916479 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916479 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36189.964158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,50 +680,50 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9218000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3041500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12259500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9218000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4569000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9218000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4569000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13787000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.773585 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888889 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899329 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899329 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33158.273381 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37091.463415 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34054.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index e082161f0..4110b4ea0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10738000 # Number of ticks simulated -final_tick 10738000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 10412000 # Number of ticks simulated +final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30784 # Simulator instruction rate (inst/s) -host_op_rate 38403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71910456 # Simulator tick rate (ticks/s) -host_mem_usage 227312 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 40558 # Simulator instruction rate (inst/s) +host_op_rate 50593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91854675 # Simulator tick rate (ticks/s) +host_mem_usage 232720 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7936 # Number of bytes read from this memory -system.physmem.bytes_read::total 25728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1656919352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 739057553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2395976904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1656919352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1656919352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 739057553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2395976904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,243 +70,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 21477 # number of cpu cycles simulated +system.cpu.numCycles 20825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2491 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1789 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1964 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.lookups 2492 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6988 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12142 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 958 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2639 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1622 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2325 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.169334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.586059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10418 79.79% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223 1.71% 81.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 193 1.48% 82.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 1.66% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.60% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 285 2.18% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 109 0.83% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 131 1.00% 90.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13057 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115985 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.565349 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7128 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 89 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 945 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2432 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13276 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7383 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1669 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12436 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 239 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12439 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56552 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56280 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2229 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6758 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 47 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 766 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2732 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 47 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11190 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 47 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8841 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5157 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13057 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.677108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.355722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9364 71.72% 71.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1488 11.40% 83.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 792 6.07% 89.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 545 4.17% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 428 3.28% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 276 2.11% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 114 0.87% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 42 0.32% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13057 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.88% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 136 63.85% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 73 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5345 60.46% 60.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2263 25.60% 86.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1222 13.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8841 # Type of FU issued -system.cpu.iq.rate 0.411650 # Inst issue rate -system.cpu.iq.fu_busy_cnt 213 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024092 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31043 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16402 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7990 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8838 # Type of FU issued +system.cpu.iq.rate 0.424394 # Inst issue rate +system.cpu.iq.fu_busy_cnt 221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9034 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1531 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 653 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11245 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2732 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8445 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3250 # number of memory reference insts executed -system.cpu.iew.exec_branches 1412 # Number of branches executed -system.cpu.iew.exec_stores 1169 # Number of stores executed -system.cpu.iew.exec_rate 0.393211 # Inst execution rate -system.cpu.iew.wb_sent 8142 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8006 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3825 # num instructions producing a value -system.cpu.iew.wb_consumers 7724 # num instructions consuming a value +system.cpu.iew.exec_refs 3246 # number of memory reference insts executed +system.cpu.iew.exec_branches 1415 # Number of branches executed +system.cpu.iew.exec_stores 1167 # Number of stores executed +system.cpu.iew.exec_rate 0.404994 # Inst execution rate +system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3850 # num instructions producing a value +system.cpu.iew.wb_consumers 7766 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.372771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.495210 # average fanout of values written-back +system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5517 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12113 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.473376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.288273 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9737 80.38% 80.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1166 9.63% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 419 3.46% 93.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 269 2.22% 95.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 155 1.28% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 162 1.34% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 54 0.45% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.32% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 112 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -317,69 +317,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 112 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23095 # The number of ROB reads -system.cpu.rob.rob_writes 23459 # The number of ROB writes -system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22290 # The number of ROB reads +system.cpu.rob.rob_writes 23328 # The number of ROB writes +system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.672977 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.672977 # CPI: Total CPI of All Threads -system.cpu.ipc 0.213996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.213996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 38788 # number of integer regfile reads -system.cpu.int_regfile_writes 7902 # number of integer regfile writes +system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 38756 # number of integer regfile reads +system.cpu.int_regfile_writes 7886 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15082 # number of misc regfile reads +system.cpu.misc_regfile_reads 15116 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 149.911543 # Cycle average of tags in use -system.cpu.icache.total_refs 1558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.210702 # Average number of references to valid blocks. +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use +system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.911543 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073199 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1558 # number of overall hits -system.cpu.icache.overall_hits::total 1558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1931 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193164 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193164 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193164 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193164 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193164 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35747.989276 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35747.989276 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35747.989276 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits +system.cpu.icache.overall_hits::total 1564 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,110 +388,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 74 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 74 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 74 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10560500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10560500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10560500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10560500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154842 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.154842 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.154842 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35319.397993 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35319.397993 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.954141 # Cycle average of tags in use -system.cpu.dcache.total_refs 2354 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.905405 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use +system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.954141 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021229 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021229 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2329 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2329 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2329 # number of overall hits -system.cpu.dcache.overall_hits::total 2329 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits +system.cpu.dcache.overall_hits::total 2306 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7113500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7113500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12639500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19753000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19753000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19753000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19753000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1918 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2831 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2831 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2831 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2831 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.099583 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.099583 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.177323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.177323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.177323 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.177323 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37243.455497 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37243.455497 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40641.479100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40641.479100 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39348.605578 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,124 +500,124 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3692500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1708000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5400500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5400500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055266 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055266 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.052278 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.052278 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34834.905660 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34834.905660 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40666.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40666.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36489.864865 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36489.864865 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.052350 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.052350 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40476.190476 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40476.190476 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 187.774695 # Cycle average of tags in use -system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 360 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.108333 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.003042 # Cycle average of tags in use +system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 141.174021 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.600674 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001422 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005730 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::cpu.inst 141.702568 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.300474 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004324 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001413 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005737 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits +system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits +system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 37 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 280 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 408 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 280 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses -system.cpu.l2cache.overall_misses::total 408 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10109500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3421000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13530500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1660500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1660500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10109500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5081500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15191000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10109500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5081500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15191000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 299 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 406 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 406 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10097000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3413000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1657000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1657000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10097000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15167000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10097000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5070000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15167000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.936455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.903704 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.907731 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.936455 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.864865 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.912752 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.936455 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.864865 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.912752 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36105.357143 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39779.069767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36968.579235 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39535.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37232.843137 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37232.843137 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916479 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916479 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36189.964158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,50 +635,50 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9218000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3041500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12259500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9218000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4569000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9218000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4569000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13787000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.773585 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888889 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899329 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899329 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33158.273381 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37091.463415 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34054.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index ae539a028..059498d9f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27316000 # Number of ticks simulated -final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000026 # Number of seconds simulated +sim_ticks 25969000 # Number of ticks simulated +final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78983 # Simulator instruction rate (inst/s) -host_op_rate 98109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 472376751 # Simulator tick rate (ticks/s) -host_mem_usage 225996 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 147661 # Simulator instruction rate (inst/s) +host_op_rate 183366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 839095918 # Simulator tick rate (ticks/s) +host_mem_usage 231680 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 527163567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 292868648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 820032216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 527163567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 527163567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 527163567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 292868648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 820032216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 54632 # number of cpu cycles simulated +system.cpu.numCycles 51938 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 2138 # nu system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 54632 # Number of busy cycles +system.cpu.num_busy_cycles 51938 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.832264 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.832264 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.056070 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.056070 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53211.618257 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.122861 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.122861 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020294 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020294 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51234.042553 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 154.336658 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 106.089659 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.246999 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003238 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001472 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004710 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 28611e3d6..1d71c4fe2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20518000 # Number of ticks simulated -final_tick 20518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20184000 # Number of ticks simulated +final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56112 # Simulator instruction rate (inst/s) -host_op_rate 56102 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197957466 # Simulator tick rate (ticks/s) -host_mem_usage 223380 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 50290 # Simulator instruction rate (inst/s) +host_op_rate 50282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174536927 # Simulator tick rate (ticks/s) +host_mem_usage 219492 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 988790330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 430451311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1419241641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 988790330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 988790330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 988790330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 430451311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1419241641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1005152596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 437574316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1442726912 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1005152596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1005152596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1005152596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 437574316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1442726912 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 41037 # number of cpu cycles simulated +system.cpu.numCycles 40369 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1146 # Number of BP lookups @@ -59,13 +59,13 @@ system.cpu.branch_predictor.RASInCorrect 32 # Nu system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5095 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5096 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8491 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8492 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1321 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1320 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2235 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken). @@ -76,12 +76,12 @@ system.cpu.execution_unit.executions 3144 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9756 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35650 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5387 # Number of cycles cpu stages are processed. -system.cpu.activity 13.127178 # Percentage of cycles cpu is active +system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34984 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5385 # Number of cycles cpu stages are processed. +system.cpu.activity 13.339444 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -93,72 +93,72 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 7.058308 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.943412 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.058308 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141677 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.943412 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144021 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.141677 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37412 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.144021 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 36744 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 8.833492 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38215 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 8.979663 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 37547 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 6.876721 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2785 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 6.786558 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 39795 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 6.990513 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 37585 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 6.896381 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 39127 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.026537 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38135 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.071667 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.076618 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.193639 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 147.247157 # Cycle average of tags in use -system.cpu.icache.total_refs 411 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 147.108411 # Cycle average of tags in use +system.cpu.icache.total_refs 410 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.247157 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071898 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071898 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits -system.cpu.icache.overall_hits::total 411 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 147.108411 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071830 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071830 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits +system.cpu.icache.overall_hits::total 410 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19614000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19614000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19614000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19614000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19614000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19614000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 755 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 755 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 755 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 755 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 755 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 755 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.455629 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.455629 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.455629 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.455629 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.455629 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.455629 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57017.441860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 57017.441860 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 57017.441860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 57017.441860 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19298000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19298000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19298000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19298000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19298000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19298000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.456233 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.456233 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56098.837209 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56098.837209 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56098.837209 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -179,34 +179,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17429500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17429500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17429500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17429500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17429500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17429500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.422517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.422517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.422517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54637.931034 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54637.931034 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17456000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17456000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17456000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17456000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17456000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17456000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54721.003135 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54721.003135 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.284631 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.235833 # Cycle average of tags in use system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.284631 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021798 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021798 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.235833 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021786 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021786 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits @@ -223,14 +223,14 @@ system.cpu.dcache.demand_misses::cpu.data 254 # n system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses system.cpu.dcache.overall_misses::total 254 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5537500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5537500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10150000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10150000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15687500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15687500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15687500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15687500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5402500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5402500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9244000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9244000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14646500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14646500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14646500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14646500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -247,14 +247,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.121648 system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60851.648352 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60851.648352 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62269.938650 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62269.938650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61761.811024 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61761.811024 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59368.131868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59368.131868 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56711.656442 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56711.656442 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -279,14 +279,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2913500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2913500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8052000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8052000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8052000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8052000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5111000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5111000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2905000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2905000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8016000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8016000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8016000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8016000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -295,26 +295,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59063.218391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59063.218391 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57127.450980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58347.826087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58347.826087 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58747.126437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58747.126437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56960.784314 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56960.784314 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 204.307813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 204.139180 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 148.858961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.448851 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006235 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 148.719836 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.419344 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004539 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006230 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17061000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5022000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22083000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2843500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2843500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 17061000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7865500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24926500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 17061000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7865500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24926500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5017500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2851000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2851000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7868500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24979000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7868500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24979000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53820.189274 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57724.137931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54660.891089 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55754.901961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55754.901961 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54783.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54783.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53976.340694 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57672.413793 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54772.277228 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55901.960784 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55901.960784 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54898.901099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54898.901099 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +395,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13201000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3966500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17167500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2221000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2221000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13201000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19388500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13201000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19388500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13248500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17211000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2227500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2227500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13248500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6190000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19438500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13248500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6190000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19438500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -417,17 +417,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.533123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45591.954023 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42493.811881 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43549.019608 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43549.019608 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41793.375394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45545.977011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42601.485149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43676.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43676.470588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ad536cc25..1fd33095f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12925500 # Number of ticks simulated -final_tick 12925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12603500 # Number of ticks simulated +final_tick 12603500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52967 # Simulator instruction rate (inst/s) -host_op_rate 52957 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132735366 # Simulator tick rate (ticks/s) -host_mem_usage 224404 # Number of bytes of host memory used +host_inst_rate 49943 # Simulator instruction rate (inst/s) +host_op_rate 49935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122043566 # Simulator tick rate (ticks/s) +host_mem_usage 220512 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21696 # Nu system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 480 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1678542416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 698154810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2376697226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1678542416 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1678542416 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1678542416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 698154810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2376697226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1721426588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 715991590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2437418177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1721426588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1721426588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1721426588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 715991590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2437418177 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,101 +46,101 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25852 # number of cpu cycles simulated +system.cpu.numCycles 25208 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2052 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1365 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2076 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1377 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1625 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 468 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1640 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 471 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 254 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 262 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8806 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12660 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2052 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 722 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1287 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 809 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12782 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2076 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 733 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3147 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1298 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 705 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1908 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.923414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.233238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1923 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.958099 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.266693 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10597 77.29% 77.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1289 9.40% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 106 0.77% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 138 1.01% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 293 2.14% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 99 0.72% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 151 1.10% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 124 0.90% 93.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 913 6.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10194 76.41% 76.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1306 9.79% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 106 0.79% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 141 1.06% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 294 2.20% 90.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 100 0.75% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 154 1.15% 92.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 127 0.95% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 919 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079375 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.489711 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8966 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 966 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2934 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 143 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082355 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.507061 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8622 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 899 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2969 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11758 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11860 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9155 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 277 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2801 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 144 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11265 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13414 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13410 # Number of integer rename lookups +system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8807 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 544 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2833 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11360 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 96 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13517 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3481 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1172 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3542 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 277 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8008 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3225 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1836 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.584099 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.244040 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8869 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8060 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1840 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.604153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.265993 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10210 74.47% 74.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1436 10.47% 84.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 842 6.14% 91.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 525 3.83% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 351 2.56% 97.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 220 1.60% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.62% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9853 73.86% 73.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1401 10.50% 84.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 847 6.35% 90.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 533 4.00% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 353 2.65% 97.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 227 1.70% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 84 0.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 29 0.22% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13341 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available @@ -176,113 +176,113 @@ system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4734 59.12% 59.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2177 27.19% 86.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1088 13.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4766 59.13% 59.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2195 27.23% 86.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1090 13.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8008 # Type of FU issued -system.cpu.iq.rate 0.309763 # Inst issue rate +system.cpu.iq.FU_type_0::total 8060 # Type of FU issued +system.cpu.iq.rate 0.319740 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018981 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29921 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12064 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7226 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018859 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29653 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7261 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8158 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8210 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1209 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1225 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 247 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 94 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1172 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 170 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10299 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7665 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 343 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7692 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2065 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 368 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1409 # number of nop insts executed -system.cpu.iew.exec_refs 3123 # number of memory reference insts executed -system.cpu.iew.exec_branches 1292 # Number of branches executed +system.cpu.iew.exec_nop 1417 # number of nop insts executed +system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_branches 1305 # Number of branches executed system.cpu.iew.exec_stores 1062 # Number of stores executed -system.cpu.iew.exec_rate 0.296495 # Inst execution rate -system.cpu.iew.wb_sent 7314 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7228 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2794 # num instructions producing a value -system.cpu.iew.wb_consumers 3985 # num instructions consuming a value +system.cpu.iew.exec_rate 0.305141 # Inst execution rate +system.cpu.iew.wb_sent 7351 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7263 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2827 # num instructions producing a value +system.cpu.iew.wb_consumers 4035 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.279592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.701129 # average fanout of values written-back +system.cpu.iew.wb_rate 0.288123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.700620 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4420 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4478 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.450027 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.233846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.463668 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.253066 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10496 81.26% 81.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1026 7.94% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 636 4.92% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 301 2.33% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.15% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 90 0.70% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 76 0.59% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 38 0.29% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10143 80.90% 80.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 988 7.88% 88.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 634 5.06% 93.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 313 2.50% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.18% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 91 0.73% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 75 0.60% 98.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12537 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,67 +295,67 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23031 # The number of ROB reads -system.cpu.rob.rob_writes 21266 # The number of ROB writes +system.cpu.rob.rob_reads 22709 # The number of ROB reads +system.cpu.rob.rob_writes 21393 # The number of ROB writes system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12142 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11867 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 5.013964 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.013964 # CPI: Total CPI of All Threads -system.cpu.ipc 0.199443 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.199443 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10440 # number of integer regfile reads -system.cpu.int_regfile_writes 5074 # number of integer regfile writes +system.cpu.cpi 4.889061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.889061 # CPI: Total CPI of All Threads +system.cpu.ipc 0.204538 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.204538 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10482 # number of integer regfile reads +system.cpu.int_regfile_writes 5097 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.misc_regfile_reads 151 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.949608 # Cycle average of tags in use -system.cpu.icache.total_refs 1474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.691170 # Cycle average of tags in use +system.cpu.icache.total_refs 1486 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.309942 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.345029 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.949608 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079077 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079077 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits -system.cpu.icache.overall_hits::total 1474 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses -system.cpu.icache.overall_misses::total 434 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15909000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15909000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15909000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15909000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15909000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.227463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.227463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.227463 # 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Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1833 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 576 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2409 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2409 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2409 # number of overall hits +system.cpu.dcache.overall_hits::total 2409 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # 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number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075177 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075177 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377297 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.377297 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.171311 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.171311 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.171311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.171311 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36459.731544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36459.731544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33409.742120 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33409.742120 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34322.289157 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34322.289157 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34322.289157 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,14 +460,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 298 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 298 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 357 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 357 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 357 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 357 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -476,42 +476,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5913000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5913000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2072000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2072000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5906500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5906500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5906500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5906500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045409 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045409 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048570 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048570 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048570 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41936.170213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41936.170213 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048504 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048504 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048504 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42605.555556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42605.555556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41890.070922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41890.070922 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.306774 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.970580 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.083724 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.223050 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005007 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001746 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006754 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 163.825301 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.145280 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001744 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -529,17 +529,17 @@ system.cpu.l2cache.demand_misses::total 480 # nu system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12053000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3723500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15776500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12053000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5721500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17774500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12053000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5721500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17774500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3740000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15824000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2020500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2020500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12084000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5760500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17844500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12084000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5760500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17844500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) @@ -562,17 +562,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993789 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35554.572271 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41372.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36775.058275 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37030.208333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37030.208333 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35646.017699 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41555.555556 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36885.780886 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39617.647059 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39617.647059 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37176.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35646.017699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40854.609929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37176.041667 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,17 +592,17 @@ system.cpu.l2cache.demand_mshr_misses::total 480 system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10969500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3448000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14417500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10969500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5287500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16257000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10969500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5287500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16257000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11000500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14466000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1861500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1861500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11000500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5327000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16327500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11000500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5327000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16327500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses @@ -614,17 +614,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32358.407080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38311.111111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33607.226107 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32449.852507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38505.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33720.279720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32449.852507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37780.141844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34015.625000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 654ee7d3b..b337ea793 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 33399000 # Number of ticks simulated -final_tick 33399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 31633000 # Number of ticks simulated +final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212162 # Simulator instruction rate (inst/s) -host_op_rate 212025 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1217250605 # Simulator tick rate (ticks/s) -host_mem_usage 223376 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 284864 # Simulator instruction rate (inst/s) +host_op_rate 284628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1547353604 # Simulator tick rate (ticks/s) +host_mem_usage 219460 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 576783736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 264439055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 841222791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 576783736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 576783736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 576783736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 264439055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 841222791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 66798 # number of cpu cycles simulated +system.cpu.numCycles 63266 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5814 # Number of instructions committed @@ -65,18 +65,18 @@ system.cpu.num_mem_refs 2089 # nu system.cpu.num_load_insts 1163 # Number of load instructions system.cpu.num_store_insts 926 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 66798 # Number of busy cycles +system.cpu.num_busy_cycles 63266 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 133.141027 # Cycle average of tags in use +system.cpu.icache.tagsinuse 132.545353 # Cycle average of tags in use system.cpu.icache.total_refs 5513 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 133.141027 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.065010 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.065010 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.064719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -89,12 +89,12 @@ system.cpu.icache.demand_misses::cpu.inst 303 # n system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses system.cpu.icache.overall_misses::total 303 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses @@ -107,12 +107,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.742269 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.742269 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021421 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021421 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits @@ -171,14 +171,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -195,14 +195,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.881290 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 134.495649 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 54.385641 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004104 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001660 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index b2cd52879..233f5f73b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11763500 # Number of ticks simulated -final_tick 11763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11490500 # Number of ticks simulated +final_tick 11490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53396 # Simulator instruction rate (inst/s) -host_op_rate 53387 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108411505 # Simulator tick rate (ticks/s) -host_mem_usage 219412 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 46998 # Simulator instruction rate (inst/s) +host_op_rate 46991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93211132 # Simulator tick rate (ticks/s) +host_mem_usage 217464 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28992 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1909635738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 549496323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2459132061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1909635738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1909635738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1909635738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 549496323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2459132061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory +system.physmem.num_reads::total 453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1955006310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 568121492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2523127801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1955006310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1955006310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1955006310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 568121492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2523127801 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,243 +46,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 23528 # number of cpu cycles simulated +system.cpu.numCycles 22982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2457 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2014 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2481 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2031 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2037 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 618 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2060 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 620 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7380 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14306 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2457 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 778 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2377 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1402 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 936 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7156 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14473 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 780 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2399 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1409 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 837 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1859 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.229249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.662964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1870 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 316 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.275829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.704070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9261 79.58% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 173 1.49% 81.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 162 1.39% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 137 1.18% 83.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 198 1.70% 85.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.27% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 250 2.15% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 106 0.91% 89.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1203 10.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8945 78.85% 78.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 173 1.53% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 163 1.44% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 136 1.20% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 199 1.75% 84.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 148 1.30% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 251 2.21% 88.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.95% 89.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 10.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104429 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.608041 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7505 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1074 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2213 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 351 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12646 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 11344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107954 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.629754 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7303 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 957 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2216 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 791 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 355 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12764 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7717 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 446 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 386 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2059 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 246 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11999 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10316 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19545 # Number of integer rename lookups +system.cpu.rename.SquashCycles 791 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7518 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2068 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 254 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12054 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 208 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10357 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19653 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19598 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5318 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5359 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 543 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1909 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 528 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2068 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1915 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10820 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10860 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9196 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 160 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4145 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9235 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4823 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4140 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11638 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.790170 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.525459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.814087 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.547249 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8215 70.59% 70.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1109 9.53% 80.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 778 6.68% 86.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 515 4.43% 91.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 472 4.06% 95.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 322 2.77% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 140 1.20% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 48 0.41% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7932 69.92% 69.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1090 9.61% 79.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 771 6.80% 86.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 520 4.58% 90.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 472 4.16% 95.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 326 2.87% 97.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 145 1.28% 99.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.43% 99.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11344 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.34% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 75 43.86% 46.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.29% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 76 43.43% 45.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 95 54.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5661 61.56% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1833 19.93% 81.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1700 18.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5682 61.53% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1849 20.02% 81.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1702 18.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9196 # Type of FU issued -system.cpu.iq.rate 0.390853 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018595 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30299 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15649 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8318 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9235 # Type of FU issued +system.cpu.iq.rate 0.401836 # Inst issue rate +system.cpu.iq.fu_busy_cnt 175 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018950 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30091 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15718 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8353 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9376 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1090 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1107 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 863 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 229 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10884 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 101 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1909 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 138 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10924 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2068 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1915 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8699 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1698 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 497 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 381 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8741 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1709 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3253 # number of memory reference insts executed -system.cpu.iew.exec_branches 1376 # Number of branches executed -system.cpu.iew.exec_stores 1555 # Number of stores executed -system.cpu.iew.exec_rate 0.369730 # Inst execution rate -system.cpu.iew.wb_sent 8502 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4327 # num instructions producing a value -system.cpu.iew.wb_consumers 6939 # num instructions consuming a value +system.cpu.iew.exec_refs 3273 # number of memory reference insts executed +system.cpu.iew.exec_branches 1381 # Number of branches executed +system.cpu.iew.exec_stores 1564 # Number of stores executed +system.cpu.iew.exec_rate 0.380341 # Inst execution rate +system.cpu.iew.wb_sent 8540 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8380 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4334 # num instructions producing a value +system.cpu.iew.wb_consumers 6987 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.354684 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.623577 # average fanout of values written-back +system.cpu.iew.wb_rate 0.364633 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.620295 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5101 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5141 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.316329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.548849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.335888 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8424 77.61% 77.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1042 9.60% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 639 5.89% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 261 2.40% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.68% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 104 0.96% 98.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.62% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.38% 99.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94 0.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8133 77.07% 77.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1033 9.79% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 640 6.06% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 254 2.41% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.74% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 109 1.03% 98.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 61 0.58% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.40% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 97 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10553 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -293,68 +293,68 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21653 # The number of ROB reads -system.cpu.rob.rob_writes 22571 # The number of ROB writes -system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21389 # The number of ROB reads +system.cpu.rob.rob_writes 22658 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11638 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 4.062155 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.062155 # CPI: Total CPI of All Threads -system.cpu.ipc 0.246175 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.246175 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13809 # number of integer regfile reads -system.cpu.int_regfile_writes 7224 # number of integer regfile writes +system.cpu.cpi 3.967887 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.967887 # CPI: Total CPI of All Threads +system.cpu.ipc 0.252023 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.252023 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13882 # number of integer regfile reads +system.cpu.int_regfile_writes 7254 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.502715 # Cycle average of tags in use -system.cpu.icache.total_refs 1427 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 173.017509 # Cycle average of tags in use +system.cpu.icache.total_refs 1435 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.008427 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.030899 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.502715 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1427 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1427 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1427 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1427 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1427 # number of overall hits -system.cpu.icache.overall_hits::total 1427 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses -system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16299000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16299000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16299000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16299000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16299000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16299000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1859 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1859 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1859 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1859 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232383 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.232383 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.232383 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.232383 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.232383 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.232383 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37729.166667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37729.166667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37729.166667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37729.166667 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 173.017509 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084481 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084481 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits +system.cpu.icache.overall_hits::total 1435 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15962500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15962500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15962500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15962500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15962500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15962500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1870 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1870 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1870 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1870 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232620 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.232620 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.232620 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.232620 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.232620 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.232620 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36695.402299 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36695.402299 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36695.402299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36695.402299 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,94 +363,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 76 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 76 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 76 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13111000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13111000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191501 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191501 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191501 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36828.651685 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36828.651685 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13118500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13118500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13118500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13118500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13118500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13118500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.190374 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.190374 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.190374 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.190374 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36849.719101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36849.719101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36849.719101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36849.719101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.218136 # Cycle average of tags in use -system.cpu.dcache.total_refs 2196 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.742574 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.294290 # Cycle average of tags in use +system.cpu.dcache.total_refs 2199 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.558824 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.218136 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015434 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015434 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2196 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2196 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2196 # number of overall hits -system.cpu.dcache.overall_hits::total 2196 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses -system.cpu.dcache.overall_misses::total 420 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12824500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12824500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16557000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16557000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16557000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16557000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1570 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.294290 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015453 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015453 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1487 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1487 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 712 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 712 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits +system.cpu.dcache.overall_hits::total 2199 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 94 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 94 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 428 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 428 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 428 # number of overall misses +system.cpu.dcache.overall_misses::total 428 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3573500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3573500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11341500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14915000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14915000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14915000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14915000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1581 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2616 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2616 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2616 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2616 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.057962 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.057962 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.160550 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.160550 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.160550 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.160550 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41016.483516 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41016.483516 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38980.243161 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38980.243161 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39421.428571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39421.428571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39421.428571 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2627 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2627 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2627 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2627 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.059456 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.059456 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319312 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319312 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162923 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162923 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.162923 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.162923 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38015.957447 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38015.957447 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33956.586826 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33956.586826 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34848.130841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34848.130841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34848.130841 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,58 +459,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 37 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 282 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 282 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 39 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2168500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2168500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4254500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4254500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4254500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4254500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034395 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034395 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2204500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2204500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4252000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4252000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4252000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4252000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034788 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034788 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038609 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038609 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038609 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40157.407407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40157.407407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44382.978723 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44382.978723 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42123.762376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 42123.762376 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038828 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038828 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038828 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038828 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40081.818182 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40081.818182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43563.829787 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43563.829787 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41686.274510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41686.274510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41686.274510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41686.274510 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 203.045072 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.278770 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 405 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012346 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 406 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012315 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.614713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.430359 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005237 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006196 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.783445 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.495324 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005242 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006204 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits @@ -518,60 +518,60 @@ system.cpu.l2cache.demand_hits::total 5 # nu system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits system.cpu.l2cache.overall_hits::total 5 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 405 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 406 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 102 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 458 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 458 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987835 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.989059 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.989083 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.989059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36289.173789 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39046.296296 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36656.790123 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43159.574468 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43159.574468 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37332.964602 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36289.173789 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40960.396040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37332.964602 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.989083 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36344.729345 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39072.727273 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36714.285714 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42521.276596 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42521.276596 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36344.729345 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40661.764706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37316.777042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36344.729345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40661.764706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37316.777042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,49 +581,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 405 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 406 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11613500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1942500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13556000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1882000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1882000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11613500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3824500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15438000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11613500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3824500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15438000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 453 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11632000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1980500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13612500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1853000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1853000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11632000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3833500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11632000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3833500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15465500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33086.894587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35972.222222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33471.604938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40042.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40042.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33139.601140 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36009.090909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33528.325123 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39425.531915 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39425.531915 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 00104c1c9..9881f90a7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18878500 # Number of ticks simulated -final_tick 18878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18570500 # Number of ticks simulated +final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36734 # Simulator instruction rate (inst/s) -host_op_rate 36730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130153209 # Simulator tick rate (ticks/s) -host_mem_usage 229488 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 42410 # Simulator instruction rate (inst/s) +host_op_rate 42404 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147804999 # Simulator tick rate (ticks/s) +host_mem_usage 221464 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,35 +19,35 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 979738856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454273380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1434012236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 979738856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 979738856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 979738856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454273380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1434012236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 995988261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 461807706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1457795967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 995988261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 995988261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 995988261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 461807706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1457795967 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 37758 # number of cpu cycles simulated +system.cpu.numCycles 37142 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1630 # Number of BP lookups +system.cpu.branch_predictor.lookups 1632 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1167 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.596567 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 37.532134 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1125 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5623 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9611 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1685 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1682 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 1483 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken). @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 3966 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 10163 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9963 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 500 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31528 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6230 # Number of cycles cpu stages are processed. -system.cpu.activity 16.499815 # Percentage of cycles cpu is active +system.cpu.timesIdled 471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30915 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. +system.cpu.activity 16.765387 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -75,72 +75,72 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.088042 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.972405 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.088042 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141083 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.972405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143423 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.141083 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33195 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4563 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.084856 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34564 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.459134 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34714 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.143423 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32576 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4566 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.293361 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33943 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3199 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.612891 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34098 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.061868 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36776 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.195574 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36160 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.600773 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34592 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3166 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.384978 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.643907 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33973 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.532120 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.498326 # Cycle average of tags in use -system.cpu.icache.total_refs 829 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.328432 # Cycle average of tags in use +system.cpu.icache.total_refs 828 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.845361 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.498326 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066650 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066650 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits -system.cpu.icache.overall_hits::total 829 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 136.328432 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066567 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066567 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 828 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 828 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 828 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 828 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 828 # number of overall hits +system.cpu.icache.overall_hits::total 828 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19654500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19654500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19654500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19654500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19654500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19654500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1179 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1179 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1179 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1179 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.296862 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.296862 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.296862 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.296862 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.296862 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.296862 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56155.714286 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56155.714286 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56155.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56155.714286 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19327000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19327000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19327000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19327000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19327000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19327000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297114 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.297114 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.297114 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.297114 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.297114 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.297114 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,34 +161,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15991000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15991000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.246819 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.246819 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.246819 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.246819 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54951.890034 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54951.890034 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54951.890034 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54951.890034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54951.890034 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54951.890034 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15994000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15994000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15994000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54962.199313 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54962.199313 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.673308 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.607202 # Cycle average of tags in use system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.673308 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020184 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020184 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.607202 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020168 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020168 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits @@ -205,14 +205,14 @@ system.cpu.dcache.demand_misses::cpu.data 343 # n system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses system.cpu.dcache.overall_misses::total 343 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3569000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3569000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17304500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17304500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20873500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20873500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20873500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20873500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3485500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3485500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15720000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15720000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19205500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19205500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19205500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19205500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -229,20 +229,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.247118 system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58508.196721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58508.196721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61363.475177 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61363.475177 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60855.685131 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60855.685131 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60855.685131 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60855.685131 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57139.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57139.344262 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55744.680851 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55744.680851 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2306500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51255.555556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits @@ -261,14 +261,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3064500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3064500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3073000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3073000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4525000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4525000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7589500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7589500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7589500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7589500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7598000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7598000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7598000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7598000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -277,26 +277,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56907.407407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56907.407407 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55864.197531 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55864.197531 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56218.518519 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56218.518519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56218.518519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56218.518519 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.089529 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 161.896728 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 136.006338 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.083191 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000796 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004947 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 135.841585 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.055143 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004146 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000795 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004941 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2985000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18639000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4433500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15654000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23072500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15654000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7418500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23072500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15675500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3006500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18682000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4441500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4441500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15675500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7448000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23123500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15675500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7448000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23123500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54166.089965 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56320.754717 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54500 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54734.567901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54734.567901 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54544.917258 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54544.917258 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54240.484429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56726.415094 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54625.730994 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54833.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54833.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54665.484634 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54665.484634 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14482000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3454500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3454500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5797500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17936500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5797500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17936500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2365000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14525000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5827500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17987500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5827500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17987500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42003.460208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44207.547170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42345.029240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42076.124567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44622.641509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42470.760234 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42746.913580 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42746.913580 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 3eb56a69e..37ab13bca 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29527000 # Number of ticks simulated -final_tick 29527000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27800000 # Number of ticks simulated +final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69145 # Simulator instruction rate (inst/s) -host_op_rate 69130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 383102769 # Simulator tick rate (ticks/s) -host_mem_usage 229488 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 251441 # Simulator instruction rate (inst/s) +host_op_rate 251244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1310200039 # Simulator tick rate (ticks/s) +host_mem_usage 220428 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 552714465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 290446032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 843160497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552714465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552714465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552714465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 290446032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 843160497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 59054 # number of cpu cycles simulated +system.cpu.numCycles 55600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 59054 # Number of busy cycles +system.cpu.num_busy_cycles 55600 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 117.127109 # Cycle average of tags in use +system.cpu.icache.tagsinuse 117.043638 # Cycle average of tags in use system.cpu.icache.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 117.127109 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.057191 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.057191 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.057150 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55673.151751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.138993 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.138993 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020053 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020053 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2982000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4536000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4536000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7518000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55688.888889 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 142.279716 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 116.596239 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 25.683477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004342 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004339 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 87ffbf265..36ed22f0b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,269 +1,269 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12607000 # Number of ticks simulated -final_tick 12607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12215000 # Number of ticks simulated +final_tick 12215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20393 # Simulator instruction rate (inst/s) -host_op_rate 36936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47780701 # Simulator tick rate (ticks/s) -host_mem_usage 271708 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 33465 # Simulator instruction rate (inst/s) +host_op_rate 60609 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75963972 # Simulator tick rate (ticks/s) +host_mem_usage 227744 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9216 # Number of bytes read from this memory -system.physmem.bytes_read::total 28672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1543269612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 731022448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2274292060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1543269612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1543269612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1543269612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 731022448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2274292060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory +system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1598035203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 770200573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2368235776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1598035203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1598035203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1598035203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 770200573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2368235776 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 25215 # number of cpu cycles simulated +system.cpu.numCycles 24431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3186 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3186 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 582 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2623 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits +system.cpu.BPredUnit.lookups 3187 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3187 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 588 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2597 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8059 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15139 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4132 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2534 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3329 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1963 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 17595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.538335 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.007747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7858 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15336 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4160 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2551 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3088 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 59 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 17124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.595013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.047737 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 13576 77.16% 77.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 181 1.03% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 155 0.88% 79.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 205 1.17% 80.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 167 0.95% 81.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 166 0.94% 82.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 255 1.45% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.06% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2703 15.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13067 76.31% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 184 1.07% 77.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 158 0.92% 78.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 198 1.16% 79.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 177 1.03% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 181 1.06% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 237 1.38% 82.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 1.12% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2730 15.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 17595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126353 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.600397 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8491 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3340 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3724 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1929 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25781 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1929 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8836 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2060 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 411 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3455 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 904 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24174 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 785 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 26591 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 58087 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 58071 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 17124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130449 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.627727 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8263 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3049 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3749 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1947 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26028 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1947 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8634 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1940 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3487 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 694 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24257 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 601 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 26511 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 58176 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 58160 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 15531 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2042 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1780 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 15451 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2379 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1816 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21436 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21504 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18052 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 228 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 18146 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10979 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14783 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 17595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.025973 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.871104 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 17124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.059682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.899800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12050 68.49% 68.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1507 8.56% 77.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 947 5.38% 82.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 676 3.84% 86.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 766 4.35% 90.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 693 3.94% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 642 3.65% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 270 1.53% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11674 68.17% 68.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1321 7.71% 75.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 996 5.82% 81.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 705 4.12% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 752 4.39% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 712 4.16% 94.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 641 3.74% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 280 1.64% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 43 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 17595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 141 77.47% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21 11.54% 89.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166 80.19% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 80.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21 10.14% 90.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 20 9.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14462 80.11% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2078 11.51% 91.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1508 8.35% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14557 80.22% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2050 11.30% 91.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1535 8.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18052 # Type of FU issued -system.cpu.iq.rate 0.715923 # Inst issue rate -system.cpu.iq.fu_busy_cnt 182 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010082 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 54101 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32345 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18146 # Type of FU issued +system.cpu.iq.rate 0.742745 # Inst issue rate +system.cpu.iq.fu_busy_cnt 207 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011407 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53836 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32525 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16639 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18226 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18345 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 132 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 130 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1327 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 21 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1929 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1947 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1327 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21473 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1780 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 21541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 44 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2379 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1816 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 642 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 708 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17072 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1925 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 643 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17109 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1898 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1037 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3318 # number of memory reference insts executed +system.cpu.iew.exec_refs 3313 # number of memory reference insts executed system.cpu.iew.exec_branches 1690 # Number of branches executed -system.cpu.iew.exec_stores 1393 # Number of stores executed -system.cpu.iew.exec_rate 0.677057 # Inst execution rate -system.cpu.iew.wb_sent 16795 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16596 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10614 # num instructions producing a value -system.cpu.iew.wb_consumers 16437 # num instructions consuming a value +system.cpu.iew.exec_stores 1415 # Number of stores executed +system.cpu.iew.exec_rate 0.700299 # Inst execution rate +system.cpu.iew.wb_sent 16835 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16643 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10619 # num instructions producing a value +system.cpu.iew.wb_consumers 16444 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.658180 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.645738 # average fanout of values written-back +system.cpu.iew.wb_rate 0.681225 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.645767 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11727 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11795 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 596 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15666 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.622048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.485565 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 595 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15177 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.642090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514380 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12031 76.80% 76.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1491 9.52% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 525 3.35% 89.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 708 4.52% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 369 2.36% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 134 0.86% 97.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 127 0.81% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 76 0.49% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 205 1.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11633 76.65% 76.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1329 8.76% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 606 3.99% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 700 4.61% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 357 2.35% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 136 0.90% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 126 0.83% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 80 0.53% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 210 1.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15666 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15177 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,68 +274,68 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 205 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 210 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36933 # The number of ROB reads -system.cpu.rob.rob_writes 44901 # The number of ROB writes +system.cpu.rob.rob_reads 36507 # The number of ROB reads +system.cpu.rob.rob_writes 45058 # The number of ROB writes system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7307 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 4.686803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.686803 # CPI: Total CPI of All Threads -system.cpu.ipc 0.213365 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.213365 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 30057 # number of integer regfile reads -system.cpu.int_regfile_writes 17963 # number of integer regfile writes +system.cpu.cpi 4.541078 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.541078 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220212 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220212 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 30201 # number of integer regfile reads +system.cpu.int_regfile_writes 17927 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7481 # number of misc regfile reads +system.cpu.misc_regfile_reads 7454 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.992239 # Cycle average of tags in use -system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.134426 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 147.121871 # Cycle average of tags in use +system.cpu.icache.total_refs 1595 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.195440 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.992239 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071285 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071285 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits -system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 397 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 397 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 397 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 397 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 397 # number of overall misses -system.cpu.icache.overall_misses::total 397 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14592000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14592000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14592000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14592000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14592000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14592000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1963 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1963 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1963 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1963 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1963 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1963 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.202241 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.202241 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.202241 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.202241 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.202241 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.202241 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36755.667506 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36755.667506 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36755.667506 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36755.667506 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36755.667506 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 147.121871 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071837 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071837 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1595 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1595 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1595 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1595 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1595 # number of overall hits +system.cpu.icache.overall_hits::total 1595 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses +system.cpu.icache.overall_misses::total 399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14232000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14232000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14232000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14232000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14232000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200100 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.200100 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.200100 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.200100 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.200100 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.200100 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35669.172932 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35669.172932 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35669.172932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35669.172932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35669.172932 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,48 +350,48 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 92 system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 305 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 305 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 305 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11283000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11283000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11283000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155374 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155374 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155374 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.155374 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36993.442623 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36993.442623 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36993.442623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36993.442623 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 307 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 307 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 307 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 307 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 307 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11314000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11314000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11314000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11314000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11314000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11314000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153962 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153962 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153962 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153962 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36853.420195 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36853.420195 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36853.420195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36853.420195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.306580 # Cycle average of tags in use -system.cpu.dcache.total_refs 2452 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.146853 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.059195 # Cycle average of tags in use +system.cpu.dcache.total_refs 2428 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.630137 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.306580 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020339 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020339 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1594 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1594 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.059195 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020766 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020766 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2452 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2452 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2452 # number of overall hits -system.cpu.dcache.overall_hits::total 2452 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2428 # number of overall hits +system.cpu.dcache.overall_hits::total 2428 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses @@ -400,38 +400,38 @@ system.cpu.dcache.demand_misses::cpu.data 209 # n system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses system.cpu.dcache.overall_misses::total 209 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3068500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3068500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8232000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8232000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8232000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8232000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1727 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1727 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4790000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4790000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3017000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3017000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7807000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7807000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7807000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7807000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1703 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2661 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2661 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2661 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2661 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077012 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.077012 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2637 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2637 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078097 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078097 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.078542 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.078542 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.078542 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.078542 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38823.308271 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38823.308271 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40375 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39387.559809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39387.559809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39387.559809 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.079257 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.079257 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.079257 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.079257 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36015.037594 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36015.037594 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39697.368421 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39697.368421 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37354.066986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37354.066986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37354.066986 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -440,117 +440,117 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 65 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 68 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10010000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2437500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12447500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10010000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14979500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10010000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4969500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14979500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10035000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2539500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12574500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2558000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2558000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5097500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15132500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10035000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5097500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15132500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997319 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994709 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997773 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995595 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997773 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32927.631579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35845.588235 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33461.021505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33315.789474 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33315.789474 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995595 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.639344 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35767.605634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33442.819149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33657.894737 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33657.894737 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index c50a3998a..bc1030252 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29676000 # Number of ticks simulated -final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 28356000 # Number of ticks simulated +final_tick 28356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72347 # Simulator instruction rate (inst/s) -host_op_rate 131001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 398795084 # Simulator tick rate (ticks/s) -host_mem_usage 269536 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 134366 # Simulator instruction rate (inst/s) +host_op_rate 243261 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 707485860 # Simulator tick rate (ticks/s) +host_mem_usage 226568 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 489553848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288987734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 778541582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 489553848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 489553848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 489553848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288987734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 778541582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 512343067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302440401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814783467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512343067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512343067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512343067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302440401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814783467 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 59352 # number of cpu cycles simulated +system.cpu.numCycles 56712 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1986 # nu system.cpu.num_load_insts 1052 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 59352 # Number of busy cycles +system.cpu.num_busy_cycles 56712 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.746399 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.556077 # Cycle average of tags in use system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.746399 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051634 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051634 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 105.556077 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051541 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051541 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.866493 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.800961 # Cycle average of tags in use system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.866493 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019743 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 80.800961 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.019727 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.019727 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits @@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) @@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067472 system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 134.266314 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 134.040949 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.749768 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.516546 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003227 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000870 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.564188 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.476761 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004091 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 8a8cdff85..2a32b08b0 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 14993500 # Number of ticks simulated -final_tick 14993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 14818500 # Number of ticks simulated +final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32330 # Simulator instruction rate (inst/s) -host_op_rate 32329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38030689 # Simulator tick rate (ticks/s) -host_mem_usage 224252 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host +host_inst_rate 71701 # Simulator instruction rate (inst/s) +host_op_rate 71694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83350191 # Simulator tick rate (ticks/s) +host_mem_usage 220256 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory -system.physmem.bytes_read::total 62336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory -system.physmem.num_reads::total 974 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2659285690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1498249241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4157534932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2659285690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2659285690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2659285690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1498249241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4157534932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory +system.physmem.bytes_read::total 62720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory +system.physmem.num_reads::total 980 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2699328542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1533218612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4232547154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2699328542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2699328542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2699328542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1533218612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4232547154 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4043 # DTB read hits -system.cpu.dtb.read_misses 104 # DTB read misses +system.cpu.dtb.read_hits 4173 # DTB read hits +system.cpu.dtb.read_misses 101 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4147 # DTB read accesses -system.cpu.dtb.write_hits 2093 # DTB write hits -system.cpu.dtb.write_misses 65 # DTB write misses +system.cpu.dtb.read_accesses 4274 # DTB read accesses +system.cpu.dtb.write_hits 2094 # DTB write hits +system.cpu.dtb.write_misses 67 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2158 # DTB write accesses -system.cpu.dtb.data_hits 6136 # DTB hits -system.cpu.dtb.data_misses 169 # DTB misses +system.cpu.dtb.write_accesses 2161 # DTB write accesses +system.cpu.dtb.data_hits 6267 # DTB hits +system.cpu.dtb.data_misses 168 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6305 # DTB accesses -system.cpu.itb.fetch_hits 5063 # ITB hits -system.cpu.itb.fetch_misses 68 # ITB misses +system.cpu.dtb.data_accesses 6435 # DTB accesses +system.cpu.itb.fetch_hits 5272 # ITB hits +system.cpu.itb.fetch_misses 65 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5131 # ITB accesses +system.cpu.itb.fetch_accesses 5337 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -61,358 +61,358 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 29988 # number of cpu cycles simulated +system.cpu.numCycles 29638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6234 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3551 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1730 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4726 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits +system.cpu.BPredUnit.lookups 6610 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3711 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1792 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4939 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 751 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 185 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 34888 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6234 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1621 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5843 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1806 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5063 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24485 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.424872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.811431 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 944 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1602 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 36672 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6610 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6124 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5272 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 24286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.510006 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.874831 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18642 76.14% 76.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 463 1.89% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 348 1.42% 79.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 451 1.84% 81.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 433 1.77% 83.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 338 1.38% 84.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 497 2.03% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 532 2.17% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2781 11.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18162 74.78% 74.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 487 2.01% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 349 1.44% 78.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 481 1.98% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 433 1.78% 81.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 367 1.51% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 502 2.07% 85.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 575 2.37% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2930 12.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24485 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.207883 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.163399 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35160 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5629 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5043 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2441 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 657 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 429 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 30497 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 762 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2441 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35832 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2821 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 862 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4769 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2029 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28347 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2069 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21319 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 35425 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35391 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 24286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223024 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.237330 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34845 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5279 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5199 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2549 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 678 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 456 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 31855 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 699 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2549 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35545 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2460 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4962 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2034 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 29496 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2078 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22198 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 36809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 36775 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12179 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 54 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5554 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2631 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1322 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13058 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 56 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5621 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2720 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2538 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1270 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2704 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1337 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21355 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6343 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24485 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.872167 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446196 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26000 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21936 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12217 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6791 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 24286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.903236 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.464516 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15521 63.39% 63.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3217 13.14% 76.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2370 9.68% 86.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1453 5.93% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1034 4.22% 96.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 556 2.27% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 237 0.97% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 75 0.31% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 22 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15163 62.44% 62.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3175 13.07% 75.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2422 9.97% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1558 6.42% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1052 4.33% 96.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 575 2.37% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 252 1.04% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.26% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 25 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24485 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 24286 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.18% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 104 58.43% 64.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 35.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 6.15% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 105 58.66% 64.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63 35.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7361 67.94% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2308 21.30% 89.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1160 10.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7498 68.11% 68.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2352 21.36% 89.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1154 10.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10834 # Type of FU issued +system.cpu.iq.FU_type_0::total 11009 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7172 68.17% 68.19% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 68.20% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 68.20% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2223 21.13% 89.35% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1121 10.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7399 67.71% 67.73% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.74% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2369 21.68% 89.44% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1154 10.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10521 # Type of FU issued +system.cpu.iq.FU_type_1::total 10927 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14533 68.05% 68.07% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 68.08% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4531 21.22% 89.32% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2281 10.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14897 67.91% 67.93% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.94% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4721 21.52% 89.48% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2308 10.52% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21355 # Type of FU issued -system.cpu.iq.rate 0.712118 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 95 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 83 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 178 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004449 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003887 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008335 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 67413 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 36435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19171 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 21936 # Type of FU issued +system.cpu.iq.rate 0.740131 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 179 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004103 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004057 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008160 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 68413 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 38274 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19529 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21507 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22089 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 457 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1537 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 471 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1355 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 405 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1521 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 472 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 573 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25387 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 653 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5169 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2592 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1220 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2104 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2055 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4159 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1354 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2549 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 597 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26207 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5424 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2673 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 269 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1293 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20406 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2135 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2153 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4288 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1530 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 84 # number of nop insts executed -system.cpu.iew.exec_nop::1 78 # number of nop insts executed -system.cpu.iew.exec_nop::total 162 # number of nop insts executed -system.cpu.iew.exec_refs::0 3212 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3127 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6339 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1650 # Number of branches executed -system.cpu.iew.exec_branches::1 1625 # Number of branches executed -system.cpu.iew.exec_branches::total 3275 # Number of branches executed -system.cpu.iew.exec_stores::0 1108 # Number of stores executed -system.cpu.iew.exec_stores::1 1072 # Number of stores executed -system.cpu.iew.exec_stores::total 2180 # Number of stores executed -system.cpu.iew.exec_rate 0.666967 # Inst execution rate -system.cpu.iew.wb_sent::0 9882 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9596 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19478 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9755 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9436 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19191 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5007 # num instructions producing a value -system.cpu.iew.wb_producers::1 4861 # num instructions producing a value -system.cpu.iew.wb_producers::total 9868 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6484 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6279 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12763 # num instructions consuming a value +system.cpu.iew.exec_nop::0 78 # number of nop insts executed +system.cpu.iew.exec_nop::1 77 # number of nop insts executed +system.cpu.iew.exec_nop::total 155 # number of nop insts executed +system.cpu.iew.exec_refs::0 3247 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3223 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6470 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1671 # Number of branches executed +system.cpu.iew.exec_branches::1 1692 # Number of branches executed +system.cpu.iew.exec_branches::total 3363 # Number of branches executed +system.cpu.iew.exec_stores::0 1112 # Number of stores executed +system.cpu.iew.exec_stores::1 1070 # Number of stores executed +system.cpu.iew.exec_stores::total 2182 # Number of stores executed +system.cpu.iew.exec_rate 0.688508 # Inst execution rate +system.cpu.iew.wb_sent::0 9974 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9875 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19849 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9831 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9718 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19549 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5093 # num instructions producing a value +system.cpu.iew.wb_producers::1 5062 # num instructions producing a value +system.cpu.iew.wb_producers::total 10155 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6638 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6585 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13223 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.325297 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.314659 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.639956 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.772209 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.774168 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.773172 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.331703 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.327890 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.659592 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.767249 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.768717 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.767980 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12568 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13400 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 24431 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.523065 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.302863 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 24235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.527295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312718 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18816 77.02% 77.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2827 11.57% 88.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1198 4.90% 93.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 508 2.08% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 350 1.43% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 244 1.00% 98.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 205 0.84% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 82 0.34% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 201 0.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18649 76.95% 76.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2814 11.61% 88.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1163 4.80% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 521 2.15% 95.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 359 1.48% 96.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 238 0.98% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 198 0.82% 98.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 82 0.34% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 211 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 24431 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 24235 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -443,27 +443,27 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 201 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 117663 # The number of ROB reads -system.cpu.rob.rob_writes 53150 # The number of ROB writes -system.cpu.timesIdled 296 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5503 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 119797 # The number of ROB reads +system.cpu.rob.rob_writes 54926 # The number of ROB writes +system.cpu.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5352 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 4.706215 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.705476 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.352923 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.212485 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.212518 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.425003 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25299 # number of integer regfile reads -system.cpu.int_regfile_writes 14501 # number of integer regfile writes +system.cpu.cpi::0 4.651287 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.650557 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325461 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.214994 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.215028 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430022 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25729 # number of integer regfile reads +system.cpu.int_regfile_writes 14801 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -471,50 +471,50 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 314.927989 # Cycle average of tags in use -system.cpu.icache.total_refs 4192 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.707200 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 316.337538 # Cycle average of tags in use +system.cpu.icache.total_refs 4394 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.007974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 314.927989 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.153773 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.153773 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4192 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4192 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4192 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4192 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4192 # number of overall hits -system.cpu.icache.overall_hits::total 4192 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 871 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 871 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 871 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 871 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 871 # number of overall misses -system.cpu.icache.overall_misses::total 871 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34167000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34167000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34167000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34167000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34167000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34167000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.172032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.172032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.172032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.172032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.172032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.172032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39227.324914 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39227.324914 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39227.324914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39227.324914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39227.324914 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 316.337538 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.154462 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.154462 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4394 # number of overall hits +system.cpu.icache.overall_hits::total 4394 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24965000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24965000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24965000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118930 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.118930 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118930 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.118930 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39816.586922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39816.586922 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39816.586922 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 215.917106 # Cycle average of tags in use -system.cpu.dcache.total_refs 4606 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.160000 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 217.393335 # Cycle average of tags in use +system.cpu.dcache.total_refs 4714 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.316384 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 215.917106 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.052714 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.052714 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3594 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3594 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 217.393335 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.053075 # 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miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184490 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184490 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184490 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184490 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43279.320988 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43279.320988 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40212.395543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40212.395543 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41166.026871 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41166.026871 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41166.026871 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.183864 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.183864 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.183864 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.183864 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41382.267442 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41382.267442 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34040.389972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34040.389972 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36418.549906 # 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number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 135 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 135 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 572 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 572 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 707 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 707 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 707 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 36912500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22361500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36912500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997608 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35582.664526 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41851.219512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37134.661836 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39397.260274 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39397.260274 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35582.664526 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40830.484330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37473.819302 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35778.400000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42322.966507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37418.465228 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39078.767123 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39078.767123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 2b7ec11ce..e278da8a8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25614500 # Number of ticks simulated -final_tick 25614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25317500 # Number of ticks simulated +final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72825 # Simulator instruction rate (inst/s) -host_op_rate 72819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123010334 # Simulator tick rate (ticks/s) -host_mem_usage 229416 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 47783 # Simulator instruction rate (inst/s) +host_op_rate 47781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79779918 # Simulator tick rate (ticks/s) +host_mem_usage 220364 # Number of bytes of host memory used +host_seconds 0.32 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 744578266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344804700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1089382967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 744578266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 744578266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 744578266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344804700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1089382967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51230 # number of cpu cycles simulated +system.cpu.numCycles 50636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 5020 # Number of BP lookups @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 11058 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22262 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 524 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33874 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17356 # Number of cycles cpu stages are processed. -system.cpu.activity 33.878587 # Percentage of cycles cpu is active +system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17355 # Number of cycles cpu stages are processed. +system.cpu.activity 34.274034 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -75,36 +75,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.378842 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.378842 # CPI: Total CPI of All Threads -system.cpu.ipc 0.295959 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads +system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.295959 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38098 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37504 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 25.633418 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 42042 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.934804 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 42414 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.208667 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48346 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47752 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.629514 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41913 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9317 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.186609 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41318 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 164.536889 # Cycle average of tags in use +system.cpu.icache.tagsinuse 164.702089 # Cycle average of tags in use system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 164.536889 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080340 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080340 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 164.702089 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080421 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits @@ -117,12 +117,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20585000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20585000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20585000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20585000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20585000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20585000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20235000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20235000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20235000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20235000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20235000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses @@ -135,12 +135,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55785.907859 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55785.907859 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55785.907859 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55785.907859 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55785.907859 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54837.398374 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54837.398374 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -161,34 +161,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16326500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16329000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16329000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54240.863787 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54240.863787 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54240.863787 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54240.863787 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.169435 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54249.169435 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 96.547387 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 96.602865 # Cycle average of tags in use system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 96.547387 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023571 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023571 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 96.602865 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023585 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023585 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits @@ -207,14 +207,14 @@ system.cpu.dcache.demand_misses::cpu.data 359 # n system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses system.cpu.dcache.overall_misses::total 359 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3488000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3488000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18458000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18458000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21946000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21946000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21946000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21946000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3411000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3411000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16758500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16758500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20169500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20169500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20169500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20169500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -233,20 +233,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61322.259136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61130.919220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61130.919220 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58810.344828 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58810.344828 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55676.079734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55676.079734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2258500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50188.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2987500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2987500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4730000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4730000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7717500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7717500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7717500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7717500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7727500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7727500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -281,26 +281,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55647.058824 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55682.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.042677 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.928542 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.114135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005952 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15989500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2926500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18916000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15989500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7561500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23551000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15989500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7561500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23551000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16005500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18945500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4645500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4645500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16005500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7585500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23591000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16005500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7585500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23591000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53476.588629 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53738.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53892.448513 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53476.588629 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53892.448513 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53530.100334 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53822.443182 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54652.941176 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54652.941176 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53983.981693 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53983.981693 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12379500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14664500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5889000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18268500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5889000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18268500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12396000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14694500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3614500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12396000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18309000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12396000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18309000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -403,17 +403,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41403.010033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43113.207547 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41660.511364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42400 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41745.738636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42523.529412 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42523.529412 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index c96167523..5ed8e97b3 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,267 +1,267 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20275500 # Number of ticks simulated -final_tick 20275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19879000 # Number of ticks simulated +final_tick 19879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60587 # Simulator instruction rate (inst/s) -host_op_rate 60583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85082969 # Simulator tick rate (ticks/s) -host_mem_usage 230436 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 39676 # Simulator instruction rate (inst/s) +host_op_rate 39674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54630622 # Simulator tick rate (ticks/s) +host_mem_usage 221392 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1063746887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 460851767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1524598654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1063746887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1063746887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1063746887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 460851767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1524598654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1078525077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 470043765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1548568841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1078525077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1078525077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1078525077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 470043765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1548568841 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 40552 # number of cpu cycles simulated +system.cpu.numCycles 39759 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6886 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4580 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1118 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5120 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2601 # Number of BTB hits +system.cpu.BPredUnit.lookups 6854 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4554 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1112 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4710 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2490 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 458 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 477 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12252 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32221 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6886 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3059 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9555 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3174 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7365 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12088 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31936 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6854 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2967 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9404 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3148 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7222 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 767 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5498 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 31903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.009968 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.184021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 741 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5545 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 31399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.017102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.199996 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22348 70.05% 70.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4753 14.90% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 493 1.55% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 436 1.37% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 686 2.15% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 773 2.42% 92.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 236 0.74% 93.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 275 0.86% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1903 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21995 70.05% 70.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4682 14.91% 84.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 472 1.50% 86.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 410 1.31% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 687 2.19% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 719 2.29% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.75% 93.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 265 0.84% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1934 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 31903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.169807 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.794560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12897 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8133 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8716 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1960 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30041 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1960 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13576 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 285 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7298 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8274 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 510 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27346 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 31399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.172389 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.803240 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12738 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7939 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8587 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 195 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1940 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29749 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1940 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13426 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7130 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8156 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 488 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27133 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 172 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24383 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50854 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50854 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 140 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24210 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50486 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50486 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10564 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 704 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2903 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2471 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10391 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 723 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2887 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3597 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2432 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23123 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 669 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21711 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8357 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 31903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.680532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.296567 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 22935 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 673 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 91 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5610 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 198 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 31399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.687824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.304127 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22407 70.23% 70.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3681 11.54% 81.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2373 7.44% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 903 2.83% 97.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 494 1.55% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 242 0.76% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22002 70.07% 70.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3599 11.46% 81.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2373 7.56% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1680 5.35% 94.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 925 2.95% 97.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 497 1.58% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 251 0.80% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 31903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31399 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45 26.16% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 13.95% 40.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103 59.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 47 27.33% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27 15.70% 43.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 98 56.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16013 73.76% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2266 10.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15947 73.84% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3395 15.72% 89.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2255 10.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21711 # Type of FU issued -system.cpu.iq.rate 0.535387 # Inst issue rate +system.cpu.iq.FU_type_0::total 21597 # Type of FU issued +system.cpu.iq.rate 0.543198 # Inst issue rate system.cpu.iq.fu_busy_cnt 172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007922 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75603 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32175 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19936 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.007964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74856 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31925 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19878 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21883 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21769 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1413 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1372 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1023 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 984 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1960 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 99 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24957 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 410 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2471 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1940 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24765 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 456 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3597 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2432 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 673 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 290 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 979 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1247 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20532 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20456 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3252 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1141 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1165 # number of nop insts executed -system.cpu.iew.exec_refs 5418 # number of memory reference insts executed -system.cpu.iew.exec_branches 4292 # Number of branches executed -system.cpu.iew.exec_stores 2146 # Number of stores executed -system.cpu.iew.exec_rate 0.506313 # Inst execution rate -system.cpu.iew.wb_sent 20199 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19936 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9239 # num instructions producing a value -system.cpu.iew.wb_consumers 11338 # num instructions consuming a value +system.cpu.iew.exec_nop 1157 # number of nop insts executed +system.cpu.iew.exec_refs 5386 # number of memory reference insts executed +system.cpu.iew.exec_branches 4298 # Number of branches executed +system.cpu.iew.exec_stores 2134 # Number of stores executed +system.cpu.iew.exec_rate 0.514500 # Inst execution rate +system.cpu.iew.wb_sent 20129 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19878 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9203 # num instructions producing a value +system.cpu.iew.wb_consumers 11321 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.491616 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.814870 # average fanout of values written-back +system.cpu.iew.wb_rate 0.499962 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.812914 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9713 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9531 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1118 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.506075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.188090 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1112 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.202047 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22536 75.22% 75.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4135 13.80% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1423 4.75% 93.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 788 2.63% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 331 1.10% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 258 0.86% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 318 1.06% 99.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.24% 99.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22110 75.01% 75.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4076 13.83% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1418 4.81% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 772 2.62% 96.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 337 1.14% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 264 0.90% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 327 1.11% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.24% 99.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 100 0.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29476 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -272,68 +272,68 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 100 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 53914 # The number of ROB reads -system.cpu.rob.rob_writes 51717 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8649 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 53246 # The number of ROB reads +system.cpu.rob.rob_writes 51332 # The number of ROB writes +system.cpu.timesIdled 190 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8360 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 2.809088 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.809088 # CPI: Total CPI of All Threads -system.cpu.ipc 0.355987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.355987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32709 # number of integer regfile reads -system.cpu.int_regfile_writes 18169 # number of integer regfile writes -system.cpu.misc_regfile_reads 7069 # number of misc regfile reads +system.cpu.cpi 2.754156 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.754156 # CPI: Total CPI of All Threads +system.cpu.ipc 0.363088 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.363088 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32578 # number of integer regfile reads +system.cpu.int_regfile_writes 18091 # number of integer regfile writes +system.cpu.misc_regfile_reads 7032 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 199.209373 # Cycle average of tags in use -system.cpu.icache.total_refs 5019 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.805310 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 199.192019 # Cycle average of tags in use +system.cpu.icache.total_refs 5061 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15.017804 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 199.209373 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.097270 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.097270 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5019 # number of overall hits -system.cpu.icache.overall_hits::total 5019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16863000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16863000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16863000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16863000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16863000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16863000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5498 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5498 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5498 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5498 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5498 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087123 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.087123 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.087123 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.087123 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.087123 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.087123 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35204.592902 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35204.592902 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35204.592902 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35204.592902 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35204.592902 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 199.192019 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.097262 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.097262 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5061 # number of overall hits +system.cpu.icache.overall_hits::total 5061 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 484 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 484 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 484 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 484 # number of overall misses +system.cpu.icache.overall_misses::total 484 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16465500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16465500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16465500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16465500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16465500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16465500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5545 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087286 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.087286 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.087286 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.087286 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.087286 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.087286 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34019.628099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34019.628099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34019.628099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34019.628099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,56 +342,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 140 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 140 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 140 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 140 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 140 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 140 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12213000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12213000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061659 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.061659 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.061659 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12143500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12143500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12143500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060775 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.060775 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060775 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.060775 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36034.124629 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36034.124629 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36034.124629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36034.124629 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.759786 # Cycle average of tags in use -system.cpu.dcache.total_refs 4074 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.051665 # Cycle average of tags in use +system.cpu.dcache.total_refs 4061 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.904110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.815068 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.759786 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025088 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025088 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3035 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.051665 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025159 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025159 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3022 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3022 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4068 # number of overall hits -system.cpu.dcache.overall_hits::total 4068 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 4055 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4055 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4055 # number of overall hits +system.cpu.dcache.overall_hits::total 4055 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses @@ -400,40 +400,40 @@ system.cpu.dcache.demand_misses::cpu.data 530 # n system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses system.cpu.dcache.overall_misses::total 530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4649500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17651000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17651000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22300500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22300500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22300500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22300500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4244000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4244000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15546000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15546000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19790000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19790000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19790000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19790000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3143 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4598 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4598 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4598 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4598 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038340 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.038340 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4585 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4585 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4585 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4585 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038498 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038498 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115268 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115268 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43156.479218 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42076.415094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42076.415094 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.115594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35074.380165 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35074.380165 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38009.779951 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38009.779951 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37339.622642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37339.622642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37339.622642 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,103 +458,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5811000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5811000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5823000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5823000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5823000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5823000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020045 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020045 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031753 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031753 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031753 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39968.253968 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39674.698795 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031843 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031843 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031843 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39698.412698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39698.412698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40024.096386 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40024.096386 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39883.561644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 39883.561644 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 234.457580 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 234.574534 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 198.470180 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 35.987400 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.006057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001098 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.007155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 198.449350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 36.125184 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006056 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001102 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007159 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses +system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11867000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2431500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14298500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3194500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3194500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11867000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5626000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11867000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5626000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17493000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 481 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2437500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14242000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3238000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3238000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11804500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5675500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11804500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5675500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17480000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 400 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 337 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994100 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994065 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995000 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994100 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995859 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35213.649852 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38595.238095 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35746.250000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38487.951807 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38487.951807 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36217.391304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36217.391304 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995859 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35237.313433 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38690.476190 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35783.919598 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39012.048193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39012.048193 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36340.956341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35237.313433 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36340.956341 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,50 +563,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10794500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2238500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13033000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2937500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10794500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15970500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10794500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15970500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10738000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2244000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12982000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2981500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2981500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10738000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5225500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15963500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10738000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5225500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15963500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995859 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32031.157270 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35531.746032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32582.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35391.566265 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35391.566265 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32053.731343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35619.047619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32618.090452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35921.686747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35921.686747 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32053.731343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35791.095890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33188.149688 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 4464561a4..af9b5d77e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 43106000 # Number of ticks simulated -final_tick 43106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000041 # Number of seconds simulated +sim_ticks 41368000 # Number of ticks simulated +final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377775 # Simulator instruction rate (inst/s) -host_op_rate 377609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1073121241 # Simulator tick rate (ticks/s) -host_mem_usage 229408 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 652409 # Simulator instruction rate (inst/s) +host_op_rate 651936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1777530278 # Simulator tick rate (ticks/s) +host_mem_usage 220352 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 412749965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 204890270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 617640236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 412749965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 412749965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 412749965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 204890270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 617640236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 86212 # number of cpu cycles simulated +system.cpu.numCycles 82736 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 86212 # Number of busy cycles +system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 152.957781 # Cycle average of tags in use +system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.957781 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074686 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074686 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.669722 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.669722 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023845 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023845 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2968000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2968000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4760000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4760000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 183.688794 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.283537 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.405257 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000958 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005606 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits |