diff options
| author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-22 17:23:21 -0600 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-22 17:23:21 -0600 |
| commit | 589218168c5ae1ed143372e43dbc468369a1bb8f (patch) | |
| tree | 5e5154c08e7def83b49b16769c213b0e78ea41fb /tests | |
| parent | 1c448e2ab00acb05d368c9de62c5cf08e64c6213 (diff) | |
| parent | f7de30ab1a9e1655de8bf7d4c15007a682a2a629 (diff) | |
| download | gem5-589218168c5ae1ed143372e43dbc468369a1bb8f.tar.xz | |
Automated merge with ssh://hg@m5sim.org/m5
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/configs/memtest-ruby.py | 5 | ||||
| -rw-r--r-- | tests/configs/ruby_config.py | 3 | ||||
| -rw-r--r-- | tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats | 4028 | ||||
| -rwxr-xr-x | tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr | 148 | ||||
| -rwxr-xr-x | tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout | 12 | ||||
| -rw-r--r-- | tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt | 42 |
6 files changed, 3564 insertions, 674 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index c564ec600..d2be2791e 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -35,10 +35,7 @@ nb_cores = 8 cpus = [ MemTest() for i in xrange(nb_cores) ] import ruby_config -ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", - cores = nb_cores, - cache_size = 256, - cache_assoc = 2) +ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), diff --git a/tests/configs/ruby_config.py b/tests/configs/ruby_config.py index fec7bd36c..190337e67 100644 --- a/tests/configs/ruby_config.py +++ b/tests/configs/ruby_config.py @@ -8,10 +8,11 @@ from m5.params import * def generate(config_file, cores=1, memories=1, memory_size=1024, \ cache_size=32768, cache_assoc=8, dmas=1, - ruby_tick='1t', ports_per_cpu=2): + ruby_tick='1t', ports_per_cpu=2, protocol='MOESI_CMP_directory'): default = joinpath(dirname(__file__), '../../src/mem/ruby/config') ruby_config = os.environ.get('RUBY_CONFIG', default) args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"), + "-c", str(protocol), "-r", joinpath(ruby_config, config_file), "-p", str(cores), "-m", str(memories), "-s", str(memory_size), "-C", str(cache_size), "-A", str(cache_assoc), "-D", str(dmas)] diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index 98cf9b30f..e1968f983 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -12,189 +12,334 @@ RubySystem config: memory_size_bits: 30 DMA_Controller config: DMAController_0 version: 0 - buffer_size: 0 + buffer_size: 32 dma_sequencer: DMASequencer_0 number_of_TBEs: 256 recycle_latency: 10 - request_latency: 6 + request_latency: 14 + response_latency: 14 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 - buffer_size: 0 + buffer_size: 32 + directory: DirectoryMemory_0 directory_latency: 6 - directory_name: DirectoryMemory_0 - memory_controller_name: MemoryControl_0 + memory_control: MemoryControl_0 number_of_TBEs: 256 recycle_latency: 10 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 - buffer_size: 0 - cache: l1u_0 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_0 + icache: l1i_0 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_0 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_1 version: 1 - buffer_size: 0 - cache: l1u_1 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_1 + icache: l1i_1 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_2 version: 2 - buffer_size: 0 - cache: l1u_2 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_2 + icache: l1i_2 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_2 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_3 version: 3 - buffer_size: 0 - cache: l1u_3 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_3 + icache: l1i_3 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_3 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_4 version: 4 - buffer_size: 0 - cache: l1u_4 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_4 + icache: l1i_4 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_4 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_5 version: 5 - buffer_size: 0 - cache: l1u_5 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_5 + icache: l1i_5 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_5 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_6 version: 6 - buffer_size: 0 - cache: l1u_6 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_6 + icache: l1i_6 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_6 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_7 version: 7 - buffer_size: 0 - cache: l1u_7 - cache_response_latency: 12 - issue_latency: 2 + buffer_size: 32 + dcache: l1d_7 + icache: l1i_7 + l2_select_low_bit: 6 + l2_select_num_bits: 1 number_of_TBEs: 256 recycle_latency: 10 + request_latency: 2 sequencer: Sequencer_7 transitions_per_cycle: 32 -Cache config: l1u_0 +L2Cache_Controller config: L2CacheController_0 + version: 0 + buffer_size: 32 + cache: l2u_0 + number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 14 + response_latency: 14 + transitions_per_cycle: 32 +L2Cache_Controller config: L2CacheController_1 + version: 1 + buffer_size: 32 + cache: l2u_1 + number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 14 + response_latency: 14 + transitions_per_cycle: 32 +Cache config: l1d_0 + controller: L1CacheController_0 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_1 + controller: L1CacheController_1 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_2 + controller: L1CacheController_2 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_3 + controller: L1CacheController_3 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_4 + controller: L1CacheController_4 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_5 + controller: L1CacheController_5 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_6 + controller: L1CacheController_6 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1d_7 + controller: L1CacheController_7 + cache_associativity: 8 + num_cache_sets_bits: 4 + num_cache_sets: 16 + cache_set_size_bytes: 1024 + cache_set_size_Kbytes: 1 + cache_set_size_Mbytes: 0.000976562 + cache_size_bytes: 8192 + cache_size_Kbytes: 8 + cache_size_Mbytes: 0.0078125 +Cache config: l1i_0 controller: L1CacheController_0 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_1 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l1i_1 controller: L1CacheController_1 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_2 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l1i_2 controller: L1CacheController_2 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_3 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l1i_3 controller: L1CacheController_3 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_4 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l1i_4 controller: L1CacheController_4 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_5 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l1i_5 controller: L1CacheController_5 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_6 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l1i_6 controller: L1CacheController_6 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 -Cache config: l1u_7 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l1i_7 controller: L1CacheController_7 - cache_associativity: 2 - num_cache_sets_bits: 1 - num_cache_sets: 2 - cache_set_size_bytes: 128 - cache_set_size_Kbytes: 0.125 - cache_set_size_Mbytes: 0.00012207 - cache_size_bytes: 256 - cache_size_Kbytes: 0.25 - cache_size_Mbytes: 0.000244141 + cache_associativity: 8 + num_cache_sets_bits: 7 + num_cache_sets: 128 + cache_set_size_bytes: 8192 + cache_set_size_Kbytes: 8 + cache_set_size_Mbytes: 0.0078125 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 +Cache config: l2u_0 + controller: L2CacheController_0 + cache_associativity: 16 + num_cache_sets_bits: 12 + num_cache_sets: 4096 + cache_set_size_bytes: 262144 + cache_set_size_Kbytes: 256 + cache_set_size_Mbytes: 0.25 + cache_size_bytes: 4194304 + cache_size_Kbytes: 4096 + cache_size_Mbytes: 4 +Cache config: l2u_1 + controller: L2CacheController_1 + cache_associativity: 16 + num_cache_sets_bits: 12 + num_cache_sets: 4096 + cache_set_size_bytes: 262144 + cache_set_size_Kbytes: 256 + cache_set_size_Mbytes: 0.25 + cache_size_bytes: 4194304 + cache_size_Kbytes: 4096 + cache_size_Mbytes: 4 DirectoryMemory Global Config: number of directory memories: 1 total memory size bytes: 1073741824 @@ -253,133 +398,12 @@ Network Configuration network: SIMPLE_NETWORK topology: theTopology -virtual_net_0: active, ordered -virtual_net_1: active, ordered -virtual_net_2: active, ordered +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered virtual_net_3: inactive -virtual_net_4: active, ordered -virtual_net_5: active, ordered -virtual_net_6: inactive -virtual_net_7: inactive -virtual_net_8: inactive -virtual_net_9: inactive - ---- Begin Topology Print --- - -Topology print ONLY indicates the _NETWORK_ latency between two machines -It does NOT include the latency within the machines - -L1Cache-0 Network Latencies - L1Cache-0 -> L1Cache-1 net_lat: 7 - L1Cache-0 -> L1Cache-2 net_lat: 7 - L1Cache-0 -> L1Cache-3 net_lat: 7 - L1Cache-0 -> L1Cache-4 net_lat: 7 - L1Cache-0 -> L1Cache-5 net_lat: 7 - L1Cache-0 -> L1Cache-6 net_lat: 7 - L1Cache-0 -> L1Cache-7 net_lat: 7 - L1Cache-0 -> Directory-0 net_lat: 7 - L1Cache-0 -> DMA-0 net_lat: 7 - -L1Cache-1 Network Latencies - L1Cache-1 -> L1Cache-0 net_lat: 7 - L1Cache-1 -> L1Cache-2 net_lat: 7 - L1Cache-1 -> L1Cache-3 net_lat: 7 - L1Cache-1 -> L1Cache-4 net_lat: 7 - L1Cache-1 -> L1Cache-5 net_lat: 7 - L1Cache-1 -> L1Cache-6 net_lat: 7 - L1Cache-1 -> L1Cache-7 net_lat: 7 - L1Cache-1 -> Directory-0 net_lat: 7 - L1Cache-1 -> DMA-0 net_lat: 7 - -L1Cache-2 Network Latencies - L1Cache-2 -> L1Cache-0 net_lat: 7 - L1Cache-2 -> L1Cache-1 net_lat: 7 - L1Cache-2 -> L1Cache-3 net_lat: 7 - L1Cache-2 -> L1Cache-4 net_lat: 7 - L1Cache-2 -> L1Cache-5 net_lat: 7 - L1Cache-2 -> L1Cache-6 net_lat: 7 - L1Cache-2 -> L1Cache-7 net_lat: 7 - L1Cache-2 -> Directory-0 net_lat: 7 - L1Cache-2 -> DMA-0 net_lat: 7 - -L1Cache-3 Network Latencies - L1Cache-3 -> L1Cache-0 net_lat: 7 - L1Cache-3 -> L1Cache-1 net_lat: 7 - L1Cache-3 -> L1Cache-2 net_lat: 7 - L1Cache-3 -> L1Cache-4 net_lat: 7 - L1Cache-3 -> L1Cache-5 net_lat: 7 - L1Cache-3 -> L1Cache-6 net_lat: 7 - L1Cache-3 -> L1Cache-7 net_lat: 7 - L1Cache-3 -> Directory-0 net_lat: 7 - L1Cache-3 -> DMA-0 net_lat: 7 - -L1Cache-4 Network Latencies - L1Cache-4 -> L1Cache-0 net_lat: 7 - L1Cache-4 -> L1Cache-1 net_lat: 7 - L1Cache-4 -> L1Cache-2 net_lat: 7 - L1Cache-4 -> L1Cache-3 net_lat: 7 - L1Cache-4 -> L1Cache-5 net_lat: 7 - L1Cache-4 -> L1Cache-6 net_lat: 7 - L1Cache-4 -> L1Cache-7 net_lat: 7 - L1Cache-4 -> Directory-0 net_lat: 7 - L1Cache-4 -> DMA-0 net_lat: 7 - -L1Cache-5 Network Latencies - L1Cache-5 -> L1Cache-0 net_lat: 7 - L1Cache-5 -> L1Cache-1 net_lat: 7 - L1Cache-5 -> L1Cache-2 net_lat: 7 - L1Cache-5 -> L1Cache-3 net_lat: 7 - L1Cache-5 -> L1Cache-4 net_lat: 7 - L1Cache-5 -> L1Cache-6 net_lat: 7 - L1Cache-5 -> L1Cache-7 net_lat: 7 - L1Cache-5 -> Directory-0 net_lat: 7 - L1Cache-5 -> DMA-0 net_lat: 7 - -L1Cache-6 Network Latencies - L1Cache-6 -> L1Cache-0 net_lat: 7 - L1Cache-6 -> L1Cache-1 net_lat: 7 - L1Cache-6 -> L1Cache-2 net_lat: 7 - L1Cache-6 -> L1Cache-3 net_lat: 7 - L1Cache-6 -> L1Cache-4 net_lat: 7 - L1Cache-6 -> L1Cache-5 net_lat: 7 - L1Cache-6 -> L1Cache-7 net_lat: 7 - L1Cache-6 -> Directory-0 net_lat: 7 - L1Cache-6 -> DMA-0 net_lat: 7 - -L1Cache-7 Network Latencies - L1Cache-7 -> L1Cache-0 net_lat: 7 - L1Cache-7 -> L1Cache-1 net_lat: 7 - L1Cache-7 -> L1Cache-2 net_lat: 7 - L1Cache-7 -> L1Cache-3 net_lat: 7 - L1Cache-7 -> L1Cache-4 net_lat: 7 - L1Cache-7 -> L1Cache-5 net_lat: 7 - L1Cache-7 -> L1Cache-6 net_lat: 7 - L1Cache-7 -> Directory-0 net_lat: 7 - L1Cache-7 -> DMA-0 net_lat: 7 - -Directory-0 Network Latencies - Directory-0 -> L1Cache-0 net_lat: 7 - Directory-0 -> L1Cache-1 net_lat: 7 - Directory-0 -> L1Cache-2 net_lat: 7 - Directory-0 -> L1Cache-3 net_lat: 7 - Directory-0 -> L1Cache-4 net_lat: 7 - Directory-0 -> L1Cache-5 net_lat: 7 - Directory-0 -> L1Cache-6 net_lat: 7 - Directory-0 -> L1Cache-7 net_lat: 7 - Directory-0 -> DMA-0 net_lat: 7 - -DMA-0 Network Latencies - DMA-0 -> L1Cache-0 net_lat: 7 - DMA-0 -> L1Cache-1 net_lat: 7 - DMA-0 -> L1Cache-2 net_lat: 7 - DMA-0 -> L1Cache-3 net_lat: 7 - DMA-0 -> L1Cache-4 net_lat: 7 - DMA-0 -> L1Cache-5 net_lat: 7 - DMA-0 -> L1Cache-6 net_lat: 7 - DMA-0 -> L1Cache-7 net_lat: 7 - DMA-0 -> Directory-0 net_lat: 7 - ---- End Topology Print --- +virtual_net_4: inactive + Profiler Configuration ---------------------- @@ -388,34 +412,34 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Nov/18/2009 17:42:31 +Real time: Jan/19/2010 17:15:39 Profiler Stats -------------- -Elapsed_time_in_seconds: 3924 -Elapsed_time_in_minutes: 65.4 -Elapsed_time_in_hours: 1.09 -Elapsed_time_in_days: 0.0454167 +Elapsed_time_in_seconds: 219 +Elapsed_time_in_minutes: 3.65 +Elapsed_time_in_hours: 0.0608333 +Elapsed_time_in_days: 0.00253472 -Virtual_time_in_seconds: 3921.96 -Virtual_time_in_minutes: 65.366 -Virtual_time_in_hours: 1.08943 -Virtual_time_in_days: 0.0453931 +Virtual_time_in_seconds: 219.56 +Virtual_time_in_minutes: 3.65933 +Virtual_time_in_hours: 0.0609889 +Virtual_time_in_days: 0.0025412 -Ruby_current_time: 60455259 +Ruby_current_time: 4504973 Ruby_start_time: 1 -Ruby_cycles: 60455258 +Ruby_cycles: 4504972 -mbytes_resident: 151.762 -mbytes_total: 2381.61 -resident_ratio: 0.0637255 +mbytes_resident: 157.109 +mbytes_total: 1381.15 +resident_ratio: 0.113758 Total_misses: 0 total_misses: 0 [ 0 0 0 0 0 0 0 0 ] user_misses: 0 [ 0 0 0 0 0 0 0 0 ] supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ] -ruby_cycles_executed: 483642072 [ 60455259 60455259 60455259 60455259 60455259 60455259 60455259 60455259 ] +ruby_cycles_executed: 36039784 [ 4504973 4504973 4504973 4504973 4504973 4504973 4504973 4504973 ] transactions_started: 0 [ 0 0 0 0 0 0 0 0 ] transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ] @@ -424,40 +448,41 @@ misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] Memory control MemoryControl_0: - memory_total_requests: 1497259 - memory_reads: 748631 - memory_writes: 748628 - memory_refreshes: 125949 - memory_total_request_delays: 10693878 - memory_delays_per_request: 7.1423 - memory_delays_in_input_queue: 3751785 - memory_delays_behind_head_of_bank_queue: 352863 - memory_delays_stalled_at_head_of_bank_queue: 6589230 - memory_stalls_for_bank_busy: 1322551 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 8817 - memory_stalls_for_arbitration: 1317249 - memory_stalls_for_bus: 2228686 + memory_total_requests: 3005 + memory_reads: 3005 + memory_writes: 0 + memory_refreshes: 249 + memory_total_request_delays: 44377 + memory_delays_per_request: 14.7677 + memory_delays_in_input_queue: 455 + memory_delays_behind_head_of_bank_queue: 5602 + memory_delays_stalled_at_head_of_bank_queue: 38320 + memory_stalls_for_bank_busy: 5925 + memory_stalls_for_random_busy: 3962 + memory_stalls_for_anti_starvation: 2593 + memory_stalls_for_arbitration: 7799 + memory_stalls_for_bus: 11753 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 1350744 - memory_stalls_for_read_read_turnaround: 361183 - accesses_per_bank: 46780 46744 46842 46810 46806 46792 46736 46774 46868 46766 46784 46766 46757 46844 46764 46814 46814 46756 46796 46862 46782 46782 46770 46838 46780 46720 46750 46754 46840 46760 46788 46820 + memory_stalls_for_read_write_turnaround: 0 + memory_stalls_for_read_read_turnaround: 6288 + accesses_per_bank: 94 95 94 95 95 94 91 93 92 95 94 95 96 93 95 93 92 93 92 93 93 93 94 95 93 96 94 95 94 93 96 95 Busy Controller Counts: +L2Cache-0:0 L2Cache-1:0 L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 -Directory-0:0 DMA-0:0 +Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 749581 average: 15.7532 | standard deviation: 1.38784 | 0 475 726 892 999 1179 1408 1673 2066 2371 2666 3000 3297 3618 4065 5733 715413 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 747279 average: 5.5893 | standard deviation: 1.87929 | 0 2677 17977 57793 118759 170403 177953 124824 52770 12769 2104 651 477 583 776 1441 5322 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 16 max: 2089 count: 749568 average: 1269.27 | standard deviation: 184.346 | 706 46 2 38 9 9 11 1 3 18 234 183 253 263 195 167 114 113 80 74 124 134 192 223 283 302 368 333 358 349 310 281 264 303 303 313 381 411 416 435 426 499 501 538 535 532 518 525 525 512 542 549 555 659 781 726 1112 1090 2204 3346 2562 5313 3505 7093 8407 5152 11332 6998 16292 21050 13121 29097 16803 34587 35992 18551 36492 19051 36733 37381 19033 37972 19036 35937 33738 16101 29532 14057 25324 22428 10173 18224 7932 13852 11409 4860 8441 3641 6175 4984 2172 3417 1391 2332 1751 697 1089 457 745 556 215 291 123 215 137 63 94 40 57 28 9 19 5 8 5 5 4 2 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 16 max: 2059 count: 487448 average: 1269.28 | standard deviation: 183.834 | 432 31 2 21 7 7 8 1 1 8 150 118 169 171 119 101 77 70 54 51 73 78 128 142 175 205 218 217 223 230 208 191 173 202 219 188 238 265 274 281 284 338 317 343 345 351 350 322 342 355 341 355 368 421 494 491 737 709 1423 2160 1690 3504 2280 4639 5415 3375 7314 4535 10511 13782 8565 18932 10987 22355 23465 12092 23641 12545 24045 24209 12417 24627 12375 23363 21911 10475 19320 9131 16506 14610 6581 11831 5169 8995 7363 3196 5492 2339 3969 3226 1448 2182 890 1520 1118 446 700 293 484 359 146 173 86 141 81 42 61 28 39 21 7 13 3 7 2 3 3 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 16 max: 2089 count: 262120 average: 1269.26 | standard deviation: 185.295 | 274 15 0 17 2 2 3 0 2 10 84 65 84 92 76 66 37 43 26 23 51 56 64 81 108 97 150 116 135 119 102 90 91 101 84 125 143 146 142 154 142 161 184 195 190 181 168 203 183 157 201 194 187 238 287 235 375 381 781 1186 872 1809 1225 2454 2992 1777 4018 2463 5781 7268 4556 10165 5816 12232 12527 6459 12851 6506 12688 13172 6616 13345 6661 12574 11827 5626 10212 4926 8818 7818 3592 6393 2763 4857 4046 1664 2949 1302 2206 1758 724 1235 501 812 633 251 389 164 261 197 69 118 37 74 56 21 33 12 18 7 2 6 2 1 3 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 8 max: 1069 count: 747275 average: 29.6123 | standard deviation: 22.3575 | 27052 0 0 716077 295 143 361 256 13 6 4 10 2 11 5 5 1 2 3 4 1 2 3 164 216 145 112 107 103 92 66 72 72 86 76 73 71 65 82 55 47 55 79 45 56 40 35 49 50 45 32 41 33 41 44 27 44 37 34 38 33 24 33 34 28 21 23 24 18 18 12 16 22 20 9 9 7 12 11 8 6 8 6 9 6 1 4 1 7 3 2 3 3 2 8 1 7 2 2 2 1 2 1 2 1 0 1 2 5 2 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 8 max: 1069 count: 485700 average: 29.3069 | standard deviation: 22.5252 | 17456 0 0 465505 295 1 246 160 7 6 0 8 1 7 5 0 0 1 2 4 0 1 2 111 145 94 63 67 70 67 45 42 41 53 45 49 47 45 60 38 32 35 49 26 44 23 22 40 37 29 25 20 24 31 29 16 28 26 21 33 18 18 20 19 25 15 13 15 12 13 8 12 17 12 7 4 3 8 5 8 4 4 4 9 2 1 4 1 4 2 1 2 2 0 7 1 5 1 2 0 0 0 1 1 1 0 1 1 4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 8 max: 1059 count: 261575 average: 30.1795 | standard deviation: 22.0315 | 9596 0 0 250572 0 142 115 96 6 0 4 2 1 4 0 5 1 1 1 0 1 1 1 53 71 51 49 40 33 25 21 30 31 33 31 24 24 20 22 17 15 20 30 19 12 17 13 9 13 16 7 21 9 10 15 11 16 11 13 5 15 6 13 15 3 6 10 9 6 5 4 4 5 8 2 5 4 4 6 0 2 4 2 0 4 0 0 0 3 1 1 1 1 2 1 0 2 1 0 2 1 2 0 1 0 0 0 1 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -471,26 +496,21 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 0 count: 1497256 average: 0 | standard deviation: 0 | 1497256 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1497256 average: 0 | standard deviation: 0 | 1497256 ] +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748630 average: 0 | standard deviation: 0 | 748630 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 748626 average: 0 | standard deviation: 0 | 748626 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 -user_time: 3921 +user_time: 219 system_time: 0 -page_reclaims: 40455 -page_faults: 3 +page_reclaims: 41446 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -500,14 +520,17 @@ Network Stats switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.386974 - links_utilized_percent_switch_0_link_0: 0.15479 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.619159 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 748630 53901360 [ 0 748630 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 748626 5989008 [ 0 0 748626 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 748631 5989048 [ 748631 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 748628 53901216 [ 748628 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 5.79466 + links_utilized_percent_switch_0_link_0: 1.99838 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 9.59095 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 717218 51639696 [ 0 0 717218 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 720095 5760760 [ 720095 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 720227 5761816 [ 720227 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 720094 51846768 [ 0 0 720094 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 720099 5760792 [ 720099 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 720222 5761776 [ 0 0 720222 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 @@ -560,492 +583,3365 @@ links_utilized_percent_switch_7: 0 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.386975 - links_utilized_percent_switch_8_link_0: 0.15479 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.61916 bw: 160000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Control: 748631 5989048 [ 748631 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Data: 748628 53901216 [ 748628 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 748630 53901360 [ 0 748630 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 748626 5989008 [ 0 0 748626 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 2.59681 + links_utilized_percent_switch_8_link_0: 1.20053 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 3.99309 bw: 160000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 359480 2875840 [ 359480 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 359415 25877880 [ 0 0 359415 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 359479 2875832 [ 0 0 359479 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 1508 12064 [ 0 1508 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 357972 25773984 [ 0 0 357972 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Unblock_Control: 1508 12064 [ 0 0 1508 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 0 - links_utilized_percent_switch_9_link_0: 0 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 0 bw: 160000 base_latency: 1 - - -switch_10_inlinks: 10 -switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.123832 - links_utilized_percent_switch_10_link_0: 0.61916 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.619159 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Response_Data: 748630 53901360 [ 0 748630 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Control: 748626 5989008 [ 0 0 748626 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 748631 5989048 [ 748631 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Data: 748628 53901216 [ 748628 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - -l1u_0 cache stats: - l1u_0_total_misses: 748631 - l1u_0_total_demand_misses: 748631 - l1u_0_total_prefetches: 0 - l1u_0_total_sw_prefetches: 0 - l1u_0_total_hw_prefetches: 0 - l1u_0_misses_per_transaction: inf - - l1u_0_request_type_LD: 65.0336% - l1u_0_request_type_ST: 34.9664% - - l1u_0_access_mode_type_SupervisorMode: 748631 100% - l1u_0_request_size: [binsize: log2 max: 1 count: 748631 average: 1 | standard deviation: 0 | 0 748631 ] - -l1u_1 cache stats: - l1u_1_total_misses: 0 - l1u_1_total_demand_misses: 0 - l1u_1_total_prefetches: 0 - l1u_1_total_sw_prefetches: 0 - l1u_1_total_hw_prefetches: 0 - l1u_1_misses_per_transaction: nan - - l1u_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -l1u_2 cache stats: - l1u_2_total_misses: 0 - l1u_2_total_demand_misses: 0 - l1u_2_total_prefetches: 0 - l1u_2_total_sw_prefetches: 0 - l1u_2_total_hw_prefetches: 0 - l1u_2_misses_per_transaction: nan - - l1u_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -l1u_3 cache stats: - l1u_3_total_misses: 0 - l1u_3_total_demand_misses: 0 - l1u_3_total_prefetches: 0 - l1u_3_total_sw_prefetches: 0 - l1u_3_total_hw_prefetches: 0 - l1u_3_misses_per_transaction: nan - - l1u_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -l1u_4 cache stats: - l1u_4_total_misses: 0 - l1u_4_total_demand_misses: 0 - l1u_4_total_prefetches: 0 - l1u_4_total_sw_prefetches: 0 - l1u_4_total_hw_prefetches: 0 - l1u_4_misses_per_transaction: nan - - l1u_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -l1u_5 cache stats: - l1u_5_total_misses: 0 - l1u_5_total_demand_misses: 0 - l1u_5_total_prefetches: 0 - l1u_5_total_sw_prefetches: 0 - l1u_5_total_hw_prefetches: 0 - l1u_5_misses_per_transaction: nan - - l1u_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -l1u_6 cache stats: - l1u_6_total_misses: 0 - l1u_6_total_demand_misses: 0 - l1u_6_total_prefetches: 0 - l1u_6_total_sw_prefetches: 0 - l1u_6_total_hw_prefetches: 0 - l1u_6_misses_per_transaction: nan - - l1u_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -l1u_7 cache stats: - l1u_7_total_misses: 0 - l1u_7_total_demand_misses: 0 - l1u_7_total_prefetches: 0 - l1u_7_total_sw_prefetches: 0 - l1u_7_total_hw_prefetches: 0 - l1u_7_misses_per_transaction: nan - - l1u_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +links_utilized_percent_switch_9: 2.6059 + links_utilized_percent_switch_9_link_0: 1.20471 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 4.00709 bw: 160000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 360746 2885968 [ 360746 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Data: 360679 25968888 [ 0 0 360679 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 360682 2885456 [ 360682 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Unblock_Control: 360743 2885944 [ 0 0 360743 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Request_Control: 1497 11976 [ 0 1497 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_ResponseL2hit_Data: 359247 25865784 [ 0 0 359247 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 360680 2885440 [ 360680 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Unblock_Control: 1497 11976 [ 0 0 1497 0 0 ] base_latency: 1 + +switch_10_inlinks: 2 +switch_10_outlinks: 2 +links_utilized_percent_switch_10: 0.0158422 + links_utilized_percent_switch_10_link_0: 0.0016676 bw: 640000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.0300168 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Request_Control: 3005 24040 [ 0 3005 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Unblock_Control: 3005 24040 [ 0 0 3005 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1 + +switch_11_inlinks: 2 +switch_11_outlinks: 2 +links_utilized_percent_switch_11: 0 + links_utilized_percent_switch_11_link_0: 0 bw: 640000 base_latency: 1 + links_utilized_percent_switch_11_link_1: 0 bw: 160000 base_latency: 1 + + +switch_12_inlinks: 12 +switch_12_outlinks: 12 +links_utilized_percent_switch_12: 1.46843 + links_utilized_percent_switch_12_link_0: 7.99351 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_1: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_2: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_3: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_4: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_5: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_6: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_7: 0 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_8: 4.80212 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_9: 4.81885 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_10: 0.00667041 bw: 160000 base_latency: 1 + links_utilized_percent_switch_12_link_11: 0 bw: 160000 base_latency: 1 + + outgoing_messages_switch_12_link_0_Response_Data: 3005 216360 [ 0 0 3005 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_0_ResponseL2hit_Data: 717219 51639768 [ 0 0 717219 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_0_Writeback_Control: 720096 5760768 [ 720096 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_8_Request_Control: 359480 2875840 [ 359480 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_8_Response_Data: 1508 108576 [ 0 0 1508 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_8_Writeback_Data: 359415 25877880 [ 0 0 359415 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_8_Writeback_Control: 359416 2875328 [ 359416 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_8_Unblock_Control: 359479 2875832 [ 0 0 359479 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_9_Request_Control: 360746 2885968 [ 360746 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_9_Response_Data: 1497 107784 [ 0 0 1497 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_9_Writeback_Data: 360679 25968888 [ 0 0 360679 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_9_Writeback_Control: 360682 2885456 [ 360682 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_9_Unblock_Control: 360743 2885944 [ 0 0 360743 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_10_Request_Control: 3005 24040 [ 0 3005 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_10_Unblock_Control: 3005 24040 [ 0 0 3005 0 0 ] base_latency: 1 + +Sequencer: Sequencer_0 + store_waiting_on_load_cycles: 281 + store_waiting_on_store_cycles: 133 + load_waiting_on_load_cycles: 459 + load_waiting_on_store_cycles: 265 +Sequencer: Sequencer_1 + store_waiting_on_load_cycles: 0 + store_waiting_on_store_cycles: 0 + load_waiting_on_load_cycles: 0 + load_waiting_on_store_cycles: 0 +Sequencer: Sequencer_2 + store_waiting_on_load_cycles: 0 + store_waiting_on_store_cycles: 0 + load_waiting_on_load_cycles: 0 + load_waiting_on_store_cycles: 0 +Sequencer: Sequencer_3 + store_waiting_on_load_cycles: 0 + store_waiting_on_store_cycles: 0 + load_waiting_on_load_cycles: 0 + load_waiting_on_store_cycles: 0 +Sequencer: Sequencer_4 + store_waiting_on_load_cycles: 0 + store_waiting_on_store_cycles: 0 + load_waiting_on_load_cycles: 0 + load_waiting_on_store_cycles: 0 +Sequencer: Sequencer_5 + store_waiting_on_load_cycles: 0 + store_waiting_on_store_cycles: 0 + load_waiting_on_load_cycles: 0 + load_waiting_on_store_cycles: 0 +Sequencer: Sequencer_6 + store_waiting_on_load_cycles: 0 + store_waiting_on_store_cycles: 0 + load_waiting_on_load_cycles: 0 + load_waiting_on_store_cycles: 0 +Sequencer: Sequencer_7 + store_waiting_on_load_cycles: 0 + store_waiting_on_store_cycles: 0 + load_waiting_on_load_cycles: 0 + load_waiting_on_store_cycles: 0 +l1d_0 cache stats: + l1d_0_total_misses: 0 + l1d_0_total_demand_misses: 0 + l1d_0_total_prefetches: 0 + l1d_0_total_sw_prefetches: 0 + l1d_0_total_hw_prefetches: 0 + l1d_0_misses_per_transaction: nan + + l1d_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1d_1 cache stats: + l1d_1_total_misses: 0 + l1d_1_total_demand_misses: 0 + l1d_1_total_prefetches: 0 + l1d_1_total_sw_prefetches: 0 + l1d_1_total_hw_prefetches: 0 + l1d_1_misses_per_transaction: nan + + l1d_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1d_2 cache stats: + l1d_2_total_misses: 0 + l1d_2_total_demand_misses: 0 + l1d_2_total_prefetches: 0 + l1d_2_total_sw_prefetches: 0 + l1d_2_total_hw_prefetches: 0 + l1d_2_misses_per_transaction: nan + + l1d_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1d_3 cache stats: + l1d_3_total_misses: 0 + l1d_3_total_demand_misses: 0 + l1d_3_total_prefetches: 0 + l1d_3_total_sw_prefetches: 0 + l1d_3_total_hw_prefetches: 0 + l1d_3_misses_per_transaction: nan + + l1d_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1d_4 cache stats: + l1d_4_total_misses: 0 + l1d_4_total_demand_misses: 0 + l1d_4_total_prefetches: 0 + l1d_4_total_sw_prefetches: 0 + l1d_4_total_hw_prefetches: 0 + l1d_4_misses_per_transaction: nan + + l1d_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1d_5 cache stats: + l1d_5_total_misses: 0 + l1d_5_total_demand_misses: 0 + l1d_5_total_prefetches: 0 + l1d_5_total_sw_prefetches: 0 + l1d_5_total_hw_prefetches: 0 + l1d_5_misses_per_transaction: nan + + l1d_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1d_6 cache stats: + l1d_6_total_misses: 0 + l1d_6_total_demand_misses: 0 + l1d_6_total_prefetches: 0 + l1d_6_total_sw_prefetches: 0 + l1d_6_total_hw_prefetches: 0 + l1d_6_misses_per_transaction: nan + + l1d_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1d_7 cache stats: + l1d_7_total_misses: 0 + l1d_7_total_demand_misses: 0 + l1d_7_total_prefetches: 0 + l1d_7_total_sw_prefetches: 0 + l1d_7_total_hw_prefetches: 0 + l1d_7_misses_per_transaction: nan + + l1d_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_0 cache stats: + l1i_0_total_misses: 0 + l1i_0_total_demand_misses: 0 + l1i_0_total_prefetches: 0 + l1i_0_total_sw_prefetches: 0 + l1i_0_total_hw_prefetches: 0 + l1i_0_misses_per_transaction: nan + + l1i_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_1 cache stats: + l1i_1_total_misses: 0 + l1i_1_total_demand_misses: 0 + l1i_1_total_prefetches: 0 + l1i_1_total_sw_prefetches: 0 + l1i_1_total_hw_prefetches: 0 + l1i_1_misses_per_transaction: nan + + l1i_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_2 cache stats: + l1i_2_total_misses: 0 + l1i_2_total_demand_misses: 0 + l1i_2_total_prefetches: 0 + l1i_2_total_sw_prefetches: 0 + l1i_2_total_hw_prefetches: 0 + l1i_2_misses_per_transaction: nan + + l1i_2_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_3 cache stats: + l1i_3_total_misses: 0 + l1i_3_total_demand_misses: 0 + l1i_3_total_prefetches: 0 + l1i_3_total_sw_prefetches: 0 + l1i_3_total_hw_prefetches: 0 + l1i_3_misses_per_transaction: nan + + l1i_3_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_4 cache stats: + l1i_4_total_misses: 0 + l1i_4_total_demand_misses: 0 + l1i_4_total_prefetches: 0 + l1i_4_total_sw_prefetches: 0 + l1i_4_total_hw_prefetches: 0 + l1i_4_misses_per_transaction: nan + + l1i_4_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_5 cache stats: + l1i_5_total_misses: 0 + l1i_5_total_demand_misses: 0 + l1i_5_total_prefetches: 0 + l1i_5_total_sw_prefetches: 0 + l1i_5_total_hw_prefetches: 0 + l1i_5_misses_per_transaction: nan + + l1i_5_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_6 cache stats: + l1i_6_total_misses: 0 + l1i_6_total_demand_misses: 0 + l1i_6_total_prefetches: 0 + l1i_6_total_sw_prefetches: 0 + l1i_6_total_hw_prefetches: 0 + l1i_6_misses_per_transaction: nan + + l1i_6_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l1i_7 cache stats: + l1i_7_total_misses: 0 + l1i_7_total_demand_misses: 0 + l1i_7_total_prefetches: 0 + l1i_7_total_sw_prefetches: 0 + l1i_7_total_hw_prefetches: 0 + l1i_7_misses_per_transaction: nan + + l1i_7_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l2u_0 cache stats: + l2u_0_total_misses: 0 + l2u_0_total_demand_misses: 0 + l2u_0_total_prefetches: 0 + l2u_0_total_sw_prefetches: 0 + l2u_0_total_hw_prefetches: 0 + l2u_0_misses_per_transaction: nan + + l2u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +l2u_1 cache stats: + l2u_1_total_misses: 0 + l2u_1_total_demand_misses: 0 + l2u_1_total_prefetches: 0 + l2u_1_total_sw_prefetches: 0 + l2u_1_total_hw_prefetches: 0 + l2u_1_misses_per_transaction: nan + + l2u_1_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] --- DMA 0 --- - Event Counts - ReadRequest 0 WriteRequest 0 Data 0 -Ack 0 +DMA_Ack 0 +Inv_Ack 0 +All_Acks 0 - Transitions - READY ReadRequest 0 <-- READY WriteRequest 0 <-- BUSY_RD Data 0 <-- +BUSY_RD Inv_Ack 0 <-- +BUSY_RD All_Acks 0 <-- -BUSY_WR Ack 0 <-- +BUSY_WR DMA_Ack 0 <-- +BUSY_WR Inv_Ack 0 <-- +BUSY_WR All_Acks 0 <-- --- Directory 0 --- - Event Counts - -GETX 748631 -GETS 0 -PUTX 748628 -PUTX_NotOwner 0 +GETX 1022 +GETS 1983 +PUTX 0 +PUTO 0 +PUTO_SHARERS 0 +Unblock 0 +Last_Unblock 0 +Exclusive_Unblock 3005 +Clean_Writeback 0 +Dirty_Writeback 0 +Memory_Data 3005 +Memory_Ack 0 DMA_READ 0 DMA_WRITE 0 -Memory_Data 748630 -Memory_Ack 748626 +Data 0 - Transitions - -I GETX 748631 -I PUTX_NotOwner 0 <-- +I GETX 1022 +I GETS 1983 +I PUTX 0 <-- +I PUTO 0 <-- +I Memory_Data 0 <-- +I Memory_Ack 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- +S GETX 0 <-- +S GETS 0 <-- +S PUTX 0 <-- +S PUTO 0 <-- +S Memory_Data 0 <-- +S Memory_Ack 0 <-- +S DMA_READ 0 <-- +S DMA_WRITE 0 <-- + +O GETX 0 <-- +O GETS 0 <-- +O PUTX 0 <-- +O PUTO 0 <-- +O PUTO_SHARERS 0 <-- +O Memory_Data 0 <-- +O Memory_Ack 0 <-- +O DMA_READ 0 <-- +O DMA_WRITE 0 <-- + M GETX 0 <-- -M PUTX 748628 -M PUTX_NotOwner 0 <-- +M GETS 0 <-- +M PUTX 0 <-- +M PUTO 0 <-- +M PUTO_SHARERS 0 <-- +M Memory_Data 0 <-- +M Memory_Ack 0 <-- M DMA_READ 0 <-- M DMA_WRITE 0 <-- -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- - -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- - -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- - -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- +IS GETX 0 <-- +IS GETS 0 <-- +IS PUTX 0 <-- +IS PUTO 0 <-- +IS PUTO_SHARERS 0 <-- +IS Unblock 0 <-- +IS Exclusive_Unblock 1983 +IS Memory_Data 1983 +IS Memory_Ack 0 <-- +IS DMA_READ 0 <-- +IS DMA_WRITE 0 <-- + +SS GETX 0 <-- +SS GETS 0 <-- +SS PUTX 0 <-- +SS PUTO 0 <-- +SS PUTO_SHARERS 0 <-- +SS Unblock 0 <-- +SS Last_Unblock 0 <-- +SS Memory_Data 0 <-- +SS Memory_Ack 0 <-- +SS DMA_READ 0 <-- +SS DMA_WRITE 0 <-- + +OO GETX 0 <-- +OO GETS 0 <-- +OO PUTX 0 <-- +OO PUTO 0 <-- +OO PUTO_SHARERS 0 <-- +OO Unblock 0 <-- +OO Last_Unblock 0 <-- +OO Memory_Data 0 <-- +OO Memory_Ack 0 <-- +OO DMA_READ 0 <-- +OO DMA_WRITE 0 <-- + +MO GETX 0 <-- +MO GETS 0 <-- +MO PUTX 0 <-- +MO PUTO 0 <-- +MO PUTO_SHARERS 0 <-- +MO Unblock 0 <-- +MO Exclusive_Unblock 0 <-- +MO Memory_Data 0 <-- +MO Memory_Ack 0 <-- +MO DMA_READ 0 <-- +MO DMA_WRITE 0 <-- + +MM GETX 0 <-- +MM GETS 0 <-- +MM PUTX 0 <-- +MM PUTO 0 <-- +MM PUTO_SHARERS 0 <-- +MM Exclusive_Unblock 1022 +MM Memory_Data 1022 +MM Memory_Ack 0 <-- +MM DMA_READ 0 <-- +MM DMA_WRITE 0 <-- -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 748630 MI GETX 0 <-- MI GETS 0 <-- MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- +MI PUTO 0 <-- +MI PUTO_SHARERS 0 <-- +MI Unblock 0 <-- +MI Clean_Writeback 0 <-- +MI Dirty_Writeback 0 <-- +MI Memory_Data 0 <-- +MI Memory_Ack 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 748626 - -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- - -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- + +MIS GETX 0 <-- +MIS GETS 0 <-- +MIS PUTX 0 <-- +MIS PUTO 0 <-- +MIS PUTO_SHARERS 0 <-- +MIS Unblock 0 <-- +MIS Clean_Writeback 0 <-- +MIS Dirty_Writeback 0 <-- +MIS Memory_Data 0 <-- +MIS Memory_Ack 0 <-- +MIS DMA_READ 0 <-- +MIS DMA_WRITE 0 <-- + +OS GETX 0 <-- +OS GETS 0 <-- +OS PUTX 0 <-- +OS PUTO 0 <-- +OS PUTO_SHARERS 0 <-- +OS Unblock 0 <-- +OS Clean_Writeback 0 <-- +OS Dirty_Writeback 0 <-- +OS Memory_Data 0 <-- +OS Memory_Ack 0 <-- +OS DMA_READ 0 <-- +OS DMA_WRITE 0 <-- + +OSS GETX 0 <-- +OSS GETS 0 <-- +OSS PUTX 0 <-- +OSS PUTO 0 <-- +OSS PUTO_SHARERS 0 <-- +OSS Unblock 0 <-- +OSS Clean_Writeback 0 <-- +OSS Dirty_Writeback 0 <-- +OSS Memory_Data 0 <-- +OSS Memory_Ack 0 <-- +OSS DMA_READ 0 <-- +OSS DMA_WRITE 0 <-- + +XI_M GETX 0 <-- +XI_M GETS 0 <-- +XI_M PUTX 0 <-- +XI_M PUTO 0 <-- +XI_M PUTO_SHARERS 0 <-- +XI_M Memory_Data 0 <-- +XI_M Memory_Ack 0 <-- +XI_M DMA_READ 0 <-- +XI_M DMA_WRITE 0 <-- + +XI_U GETX 0 <-- +XI_U GETS 0 <-- +XI_U PUTX 0 <-- +XI_U PUTO 0 <-- +XI_U PUTO_SHARERS 0 <-- +XI_U Exclusive_Unblock 0 <-- +XI_U Memory_Ack 0 <-- +XI_U DMA_READ 0 <-- +XI_U DMA_WRITE 0 <-- + +OI_D GETX 0 <-- +OI_D GETS 0 <-- +OI_D PUTX 0 <-- +OI_D PUTO 0 <-- +OI_D PUTO_SHARERS 0 <-- +OI_D DMA_READ 0 <-- +OI_D DMA_WRITE 0 <-- +OI_D Data 0 <-- --- L1Cache 0 --- - Event Counts - -Load 487449 +Load 486730 Ifetch 0 -Store 262120 -Data 748630 +Store 262117 +L1_Replacement 721707 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 748628 -Writeback_Ack 748626 +Ack 0 +Data 0 +Exclusive_Data 720223 +Writeback_Ack 0 +Writeback_Ack_Data 720095 Writeback_Nack 0 +All_acks 251979 +Use_Timeout 720212 - Transitions - -I Load 486862 +I Load 468247 I Ifetch 0 <-- -I Store 261769 +I Store 251980 +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- - -M Load 587 +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- + +M Load 10418 M Ifetch 0 <-- -M Store 351 +M Store 5725 +M L1_Replacement 462033 M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 748628 - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 758 +M_W Ifetch 0 <-- +M_W Store 401 +M_W L1_Replacement 22 +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 467835 + +MM Load 5853 +MM Ifetch 0 <-- +MM Store 3236 +MM L1_Replacement 258066 +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 427 +MM_W Ifetch 0 <-- +MM_W Store 234 +MM_W L1_Replacement 11 +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 252377 + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 400 +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 251979 + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 1 +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 251979 + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 1174 +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 468244 + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 1027 +MI Ifetch 0 <-- +MI Store 541 +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 748626 - -IS Data 486861 - -IM Data 261769 +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- +MI Writeback_Ack 0 <-- +MI Writeback_Ack_Data 720095 +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- --- L1Cache 1 --- - Event Counts - Load 0 Ifetch 0 Store 0 -Data 0 +L1_Replacement 0 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 0 +Ack 0 +Data 0 +Exclusive_Data 0 Writeback_Ack 0 +Writeback_Ack_Data 0 Writeback_Nack 0 +All_acks 0 +Use_Timeout 0 - Transitions - I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- +M L1_Replacement 0 <-- M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L1_Replacement 0 <-- +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 0 <-- + +MM Load 0 <-- +MM Ifetch 0 <-- +MM Store 0 <-- +MM L1_Replacement 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L1_Replacement 0 <-- +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 0 <-- + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- +MI Writeback_Ack_Data 0 <-- +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- --- L1Cache 2 --- - Event Counts - Load 0 Ifetch 0 Store 0 -Data 0 +L1_Replacement 0 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 0 +Ack 0 +Data 0 +Exclusive_Data 0 Writeback_Ack 0 +Writeback_Ack_Data 0 Writeback_Nack 0 +All_acks 0 +Use_Timeout 0 - Transitions - I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- +M L1_Replacement 0 <-- M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L1_Replacement 0 <-- +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 0 <-- + +MM Load 0 <-- +MM Ifetch 0 <-- +MM Store 0 <-- +MM L1_Replacement 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L1_Replacement 0 <-- +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 0 <-- + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- +MI Writeback_Ack_Data 0 <-- +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- --- L1Cache 3 --- - Event Counts - Load 0 Ifetch 0 Store 0 -Data 0 +L1_Replacement 0 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 0 +Ack 0 +Data 0 +Exclusive_Data 0 Writeback_Ack 0 +Writeback_Ack_Data 0 Writeback_Nack 0 +All_acks 0 +Use_Timeout 0 - Transitions - I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- +M L1_Replacement 0 <-- M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L1_Replacement 0 <-- +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 0 <-- + +MM Load 0 <-- +MM Ifetch 0 <-- +MM Store 0 <-- +MM L1_Replacement 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L1_Replacement 0 <-- +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 0 <-- + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- +MI Writeback_Ack_Data 0 <-- +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- --- L1Cache 4 --- - Event Counts - Load 0 Ifetch 0 Store 0 -Data 0 +L1_Replacement 0 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 0 +Ack 0 +Data 0 +Exclusive_Data 0 Writeback_Ack 0 +Writeback_Ack_Data 0 Writeback_Nack 0 +All_acks 0 +Use_Timeout 0 - Transitions - I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- +M L1_Replacement 0 <-- M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L1_Replacement 0 <-- +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 0 <-- + +MM Load 0 <-- +MM Ifetch 0 <-- +MM Store 0 <-- +MM L1_Replacement 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L1_Replacement 0 <-- +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 0 <-- + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- +MI Writeback_Ack_Data 0 <-- +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- --- L1Cache 5 --- - Event Counts - Load 0 Ifetch 0 Store 0 -Data 0 +L1_Replacement 0 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 0 +Ack 0 +Data 0 +Exclusive_Data 0 Writeback_Ack 0 +Writeback_Ack_Data 0 Writeback_Nack 0 +All_acks 0 +Use_Timeout 0 - Transitions - I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- +M L1_Replacement 0 <-- M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L1_Replacement 0 <-- +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 0 <-- + +MM Load 0 <-- +MM Ifetch 0 <-- +MM Store 0 <-- +MM L1_Replacement 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L1_Replacement 0 <-- +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 0 <-- + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- +MI Writeback_Ack_Data 0 <-- +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- --- L1Cache 6 --- - Event Counts - Load 0 Ifetch 0 Store 0 -Data 0 +L1_Replacement 0 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 0 +Ack 0 +Data 0 +Exclusive_Data 0 Writeback_Ack 0 +Writeback_Ack_Data 0 Writeback_Nack 0 +All_acks 0 +Use_Timeout 0 - Transitions - I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- +M L1_Replacement 0 <-- M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L1_Replacement 0 <-- +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 0 <-- + +MM Load 0 <-- +MM Ifetch 0 <-- +MM Store 0 <-- +MM L1_Replacement 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L1_Replacement 0 <-- +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 0 <-- + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- MI Writeback_Ack 0 <-- - -IS Data 0 <-- - -IM Data 0 <-- +MI Writeback_Ack_Data 0 <-- +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- --- L1Cache 7 --- - Event Counts - Load 0 Ifetch 0 Store 0 -Data 0 +L1_Replacement 0 +Own_GETX 0 Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 Inv 0 -Replacement 0 +Ack 0 +Data 0 +Exclusive_Data 0 Writeback_Ack 0 +Writeback_Ack_Data 0 Writeback_Nack 0 +All_acks 0 +Use_Timeout 0 - Transitions - I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- +I L1_Replacement 0 <-- I Inv 0 <-- -I Replacement 0 <-- -II Writeback_Nack 0 <-- +S Load 0 <-- +S Ifetch 0 <-- +S Store 0 <-- +S L1_Replacement 0 <-- +S Fwd_GETS 0 <-- +S Fwd_DMA 0 <-- +S Inv 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 0 <-- +O L1_Replacement 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- +M L1_Replacement 0 <-- M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 0 <-- - +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- + +M_W Load 0 <-- +M_W Ifetch 0 <-- +M_W Store 0 <-- +M_W L1_Replacement 0 <-- +M_W Own_GETX 0 <-- +M_W Fwd_GETX 0 <-- +M_W Fwd_GETS 0 <-- +M_W Fwd_DMA 0 <-- +M_W Inv 0 <-- +M_W Use_Timeout 0 <-- + +MM Load 0 <-- +MM Ifetch 0 <-- +MM Store 0 <-- +MM L1_Replacement 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- + +MM_W Load 0 <-- +MM_W Ifetch 0 <-- +MM_W Store 0 <-- +MM_W L1_Replacement 0 <-- +MM_W Own_GETX 0 <-- +MM_W Fwd_GETX 0 <-- +MM_W Fwd_GETS 0 <-- +MM_W Fwd_DMA 0 <-- +MM_W Inv 0 <-- +MM_W Use_Timeout 0 <-- + +IM Load 0 <-- +IM Ifetch 0 <-- +IM Store 0 <-- +IM L1_Replacement 0 <-- +IM Inv 0 <-- +IM Ack 0 <-- +IM Data 0 <-- +IM Exclusive_Data 0 <-- + +SM Load 0 <-- +SM Ifetch 0 <-- +SM Store 0 <-- +SM L1_Replacement 0 <-- +SM Fwd_GETS 0 <-- +SM Fwd_DMA 0 <-- +SM Inv 0 <-- +SM Ack 0 <-- +SM Data 0 <-- +SM Exclusive_Data 0 <-- + +OM Load 0 <-- +OM Ifetch 0 <-- +OM Store 0 <-- +OM L1_Replacement 0 <-- +OM Own_GETX 0 <-- +OM Fwd_GETX 0 <-- +OM Fwd_GETS 0 <-- +OM Fwd_DMA 0 <-- +OM Ack 0 <-- +OM All_acks 0 <-- + +IS Load 0 <-- +IS Ifetch 0 <-- +IS Store 0 <-- +IS L1_Replacement 0 <-- +IS Inv 0 <-- +IS Data 0 <-- +IS Exclusive_Data 0 <-- + +SI Load 0 <-- +SI Ifetch 0 <-- +SI Store 0 <-- +SI L1_Replacement 0 <-- +SI Fwd_GETS 0 <-- +SI Fwd_DMA 0 <-- +SI Inv 0 <-- +SI Writeback_Ack 0 <-- +SI Writeback_Ack_Data 0 <-- +SI Writeback_Nack 0 <-- + +OI Load 0 <-- +OI Ifetch 0 <-- +OI Store 0 <-- +OI L1_Replacement 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Ack_Data 0 <-- +OI Writeback_Nack 0 <-- + +MI Load 0 <-- +MI Ifetch 0 <-- +MI Store 0 <-- +MI L1_Replacement 0 <-- MI Fwd_GETX 0 <-- -MI Inv 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- MI Writeback_Ack 0 <-- +MI Writeback_Ack_Data 0 <-- +MI Writeback_Nack 0 <-- + +II Load 0 <-- +II Ifetch 0 <-- +II Store 0 <-- +II L1_Replacement 0 <-- +II Inv 0 <-- +II Writeback_Ack 0 <-- +II Writeback_Ack_Data 0 <-- +II Writeback_Nack 0 <-- -IS Data 0 <-- + --- L2Cache 0 --- + - Event Counts - +L1_GETS 233916 +L1_GETX 125680 +L1_PUTO 0 +L1_PUTX 359416 +L1_PUTS_only 0 +L1_PUTS 0 +Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 +Own_GETX 0 +Inv 0 +IntAck 0 +ExtAck 0 +All_Acks 516 +Data 516 +Data_Exclusive 992 +L1_WBCLEANDATA 2649 +L1_WBDIRTYDATA 356765 +Writeback_Ack 0 +Writeback_Nack 0 +Unblock 0 +Exclusive_Unblock 359478 +L2_Replacement 0 -IM Data 0 <-- + - Transitions - +NP L1_GETS 992 +NP L1_GETX 516 +NP L1_PUTO 0 <-- +NP L1_PUTX 0 <-- +NP L1_PUTS 0 <-- +NP Inv 0 <-- + +I L1_GETS 0 <-- +I L1_GETX 0 <-- +I L1_PUTO 0 <-- +I L1_PUTX 0 <-- +I L1_PUTS 0 <-- +I Inv 0 <-- +I L2_Replacement 0 <-- + +ILS L1_GETS 0 <-- +ILS L1_GETX 0 <-- +ILS L1_PUTO 0 <-- +ILS L1_PUTX 0 <-- +ILS L1_PUTS_only 0 <-- +ILS L1_PUTS 0 <-- +ILS Inv 0 <-- +ILS L2_Replacement 0 <-- + +ILX L1_GETS 0 <-- +ILX L1_GETX 0 <-- +ILX L1_PUTO 0 <-- +ILX L1_PUTX 359416 +ILX L1_PUTS_only 0 <-- +ILX L1_PUTS 0 <-- +ILX Fwd_GETX 0 <-- +ILX Fwd_GETS 0 <-- +ILX Fwd_DMA 0 <-- +ILX Inv 0 <-- +ILX Data 0 <-- +ILX L2_Replacement 0 <-- + +ILO L1_GETS 0 <-- +ILO L1_GETX 0 <-- +ILO L1_PUTO 0 <-- +ILO L1_PUTX 0 <-- +ILO L1_PUTS 0 <-- +ILO Fwd_GETX 0 <-- +ILO Fwd_GETS 0 <-- +ILO Fwd_DMA 0 <-- +ILO Inv 0 <-- +ILO Data 0 <-- +ILO L2_Replacement 0 <-- + +ILOX L1_GETS 0 <-- +ILOX L1_GETX 0 <-- +ILOX L1_PUTO 0 <-- +ILOX L1_PUTX 0 <-- +ILOX L1_PUTS 0 <-- +ILOX Fwd_GETX 0 <-- +ILOX Fwd_GETS 0 <-- +ILOX Fwd_DMA 0 <-- +ILOX Data 0 <-- + +ILOS L1_GETS 0 <-- +ILOS L1_GETX 0 <-- +ILOS L1_PUTO 0 <-- +ILOS L1_PUTX 0 <-- +ILOS L1_PUTS_only 0 <-- +ILOS L1_PUTS 0 <-- +ILOS Fwd_GETX 0 <-- +ILOS Fwd_GETS 0 <-- +ILOS Fwd_DMA 0 <-- +ILOS Data 0 <-- +ILOS L2_Replacement 0 <-- + +ILOSX L1_GETS 0 <-- +ILOSX L1_GETX 0 <-- +ILOSX L1_PUTO 0 <-- +ILOSX L1_PUTX 0 <-- +ILOSX L1_PUTS_only 0 <-- +ILOSX L1_PUTS 0 <-- +ILOSX Fwd_GETX 0 <-- +ILOSX Fwd_GETS 0 <-- +ILOSX Fwd_DMA 0 <-- +ILOSX Data 0 <-- + +S L1_GETS 0 <-- +S L1_GETX 0 <-- +S L1_PUTX 0 <-- +S L1_PUTS 0 <-- +S Inv 0 <-- +S L2_Replacement 0 <-- + +O L1_GETS 0 <-- +O L1_GETX 0 <-- +O L1_PUTX 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- +O L2_Replacement 0 <-- + +OLS L1_GETS 0 <-- +OLS L1_GETX 0 <-- +OLS L1_PUTX 0 <-- +OLS L1_PUTS_only 0 <-- +OLS L1_PUTS 0 <-- +OLS Fwd_GETX 0 <-- +OLS Fwd_GETS 0 <-- +OLS Fwd_DMA 0 <-- +OLS L2_Replacement 0 <-- + +OLSX L1_GETS 0 <-- +OLSX L1_GETX 0 <-- +OLSX L1_PUTO 0 <-- +OLSX L1_PUTX 0 <-- +OLSX L1_PUTS_only 0 <-- +OLSX L1_PUTS 0 <-- +OLSX Fwd_GETX 0 <-- +OLSX Fwd_GETS 0 <-- +OLSX Fwd_DMA 0 <-- +OLSX L2_Replacement 0 <-- + +SLS L1_GETS 0 <-- +SLS L1_GETX 0 <-- +SLS L1_PUTX 0 <-- +SLS L1_PUTS_only 0 <-- +SLS L1_PUTS 0 <-- +SLS Inv 0 <-- +SLS L2_Replacement 0 <-- + +M L1_GETS 232846 +M L1_GETX 125126 +M L1_PUTO 0 <-- +M L1_PUTX 0 <-- +M L1_PUTS 0 <-- +M Fwd_GETX 0 <-- +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- +M L2_Replacement 0 <-- + +IFGX L1_GETS 0 <-- +IFGX L1_GETX 0 <-- +IFGX L1_PUTO 0 <-- +IFGX L1_PUTX 0 <-- +IFGX L1_PUTS_only 0 <-- +IFGX L1_PUTS 0 <-- +IFGX Fwd_GETX 0 <-- +IFGX Fwd_GETS 0 <-- +IFGX Fwd_DMA 0 <-- +IFGX Inv 0 <-- +IFGX Data 0 <-- +IFGX Data_Exclusive 0 <-- +IFGX L2_Replacement 0 <-- + +IFGS L1_GETS 0 <-- +IFGS L1_GETX 0 <-- +IFGS L1_PUTO 0 <-- +IFGS L1_PUTX 0 <-- +IFGS L1_PUTS_only 0 <-- +IFGS L1_PUTS 0 <-- +IFGS Fwd_GETX 0 <-- +IFGS Fwd_GETS 0 <-- +IFGS Fwd_DMA 0 <-- +IFGS Inv 0 <-- +IFGS Data 0 <-- +IFGS Data_Exclusive 0 <-- +IFGS L2_Replacement 0 <-- + +ISFGS L1_GETS 0 <-- +ISFGS L1_GETX 0 <-- +ISFGS L1_PUTO 0 <-- +ISFGS L1_PUTX 0 <-- +ISFGS L1_PUTS_only 0 <-- +ISFGS L1_PUTS 0 <-- +ISFGS Fwd_GETX 0 <-- +ISFGS Fwd_GETS 0 <-- +ISFGS Fwd_DMA 0 <-- +ISFGS Inv 0 <-- +ISFGS Data 0 <-- +ISFGS L2_Replacement 0 <-- + +IFGXX L1_GETS 0 <-- +IFGXX L1_GETX 0 <-- +IFGXX L1_PUTO 0 <-- +IFGXX L1_PUTX 0 <-- +IFGXX L1_PUTS_only 0 <-- +IFGXX L1_PUTS 0 <-- +IFGXX Fwd_GETX 0 <-- +IFGXX Fwd_GETS 0 <-- +IFGXX Fwd_DMA 0 <-- +IFGXX Inv 0 <-- +IFGXX IntAck 0 <-- +IFGXX All_Acks 0 <-- +IFGXX Data_Exclusive 0 <-- +IFGXX L2_Replacement 0 <-- + +OFGX L1_GETS 0 <-- +OFGX L1_GETX 0 <-- +OFGX L1_PUTO 0 <-- +OFGX L1_PUTX 0 <-- +OFGX L1_PUTS_only 0 <-- +OFGX L1_PUTS 0 <-- +OFGX Fwd_GETX 0 <-- +OFGX Fwd_GETS 0 <-- +OFGX Fwd_DMA 0 <-- +OFGX Inv 0 <-- +OFGX L2_Replacement 0 <-- + +OLSF L1_GETS 0 <-- +OLSF L1_GETX 0 <-- +OLSF L1_PUTO 0 <-- +OLSF L1_PUTX 0 <-- +OLSF L1_PUTS_only 0 <-- +OLSF L1_PUTS 0 <-- +OLSF Fwd_GETX 0 <-- +OLSF Fwd_GETS 0 <-- +OLSF Fwd_DMA 0 <-- +OLSF Inv 0 <-- +OLSF IntAck 0 <-- +OLSF All_Acks 0 <-- +OLSF L2_Replacement 0 <-- + +ILOW L1_GETS 0 <-- +ILOW L1_GETX 0 <-- +ILOW L1_PUTO 0 <-- +ILOW L1_PUTX 0 <-- +ILOW L1_PUTS_only 0 <-- +ILOW L1_PUTS 0 <-- +ILOW Fwd_GETX 0 <-- +ILOW Fwd_GETS 0 <-- +ILOW Fwd_DMA 0 <-- +ILOW Inv 0 <-- +ILOW L1_WBCLEANDATA 0 <-- +ILOW L1_WBDIRTYDATA 0 <-- +ILOW Unblock 0 <-- +ILOW L2_Replacement 0 <-- + +ILOXW L1_GETS 0 <-- +ILOXW L1_GETX 0 <-- +ILOXW L1_PUTO 0 <-- +ILOXW L1_PUTX 0 <-- +ILOXW L1_PUTS_only 0 <-- +ILOXW L1_PUTS 0 <-- +ILOXW Fwd_GETX 0 <-- +ILOXW Fwd_GETS 0 <-- +ILOXW Fwd_DMA 0 <-- +ILOXW Inv 0 <-- +ILOXW L1_WBCLEANDATA 0 <-- +ILOXW L1_WBDIRTYDATA 0 <-- +ILOXW Unblock 0 <-- +ILOXW L2_Replacement 0 <-- + +ILOSW L1_GETS 0 <-- +ILOSW L1_GETX 0 <-- +ILOSW L1_PUTO 0 <-- +ILOSW L1_PUTX 0 <-- +ILOSW L1_PUTS_only 0 <-- +ILOSW L1_PUTS 0 <-- +ILOSW Fwd_GETX 0 <-- +ILOSW Fwd_GETS 0 <-- +ILOSW Fwd_DMA 0 <-- +ILOSW Inv 0 <-- +ILOSW L1_WBCLEANDATA 0 <-- +ILOSW L1_WBDIRTYDATA 0 <-- +ILOSW Unblock 0 <-- +ILOSW L2_Replacement 0 <-- + +ILOSXW L1_GETS 0 <-- +ILOSXW L1_GETX 0 <-- +ILOSXW L1_PUTO 0 <-- +ILOSXW L1_PUTX 0 <-- +ILOSXW L1_PUTS_only 0 <-- +ILOSXW L1_PUTS 0 <-- +ILOSXW Fwd_GETX 0 <-- +ILOSXW Fwd_GETS 0 <-- +ILOSXW Fwd_DMA 0 <-- +ILOSXW Inv 0 <-- +ILOSXW L1_WBCLEANDATA 0 <-- +ILOSXW L1_WBDIRTYDATA 0 <-- +ILOSXW Unblock 0 <-- +ILOSXW L2_Replacement 0 <-- + +SLSW L1_GETS 0 <-- +SLSW L1_GETX 0 <-- +SLSW L1_PUTO 0 <-- +SLSW L1_PUTX 0 <-- +SLSW L1_PUTS_only 0 <-- +SLSW L1_PUTS 0 <-- +SLSW Fwd_GETX 0 <-- +SLSW Fwd_GETS 0 <-- +SLSW Fwd_DMA 0 <-- +SLSW Inv 0 <-- +SLSW Unblock 0 <-- +SLSW L2_Replacement 0 <-- + +OLSW L1_GETS 0 <-- +OLSW L1_GETX 0 <-- +OLSW L1_PUTO 0 <-- +OLSW L1_PUTX 0 <-- +OLSW L1_PUTS_only 0 <-- +OLSW L1_PUTS 0 <-- +OLSW Fwd_GETX 0 <-- +OLSW Fwd_GETS 0 <-- +OLSW Fwd_DMA 0 <-- +OLSW Inv 0 <-- +OLSW Unblock 0 <-- +OLSW L2_Replacement 0 <-- + +ILSW L1_GETS 0 <-- +ILSW L1_GETX 0 <-- +ILSW L1_PUTO 0 <-- +ILSW L1_PUTX 0 <-- +ILSW L1_PUTS_only 0 <-- +ILSW L1_PUTS 0 <-- +ILSW Fwd_GETX 0 <-- +ILSW Fwd_GETS 0 <-- +ILSW Fwd_DMA 0 <-- +ILSW Inv 0 <-- +ILSW L1_WBCLEANDATA 0 <-- +ILSW Unblock 0 <-- +ILSW L2_Replacement 0 <-- + +IW L1_GETS 0 <-- +IW L1_GETX 0 <-- +IW L1_PUTO 0 <-- +IW L1_PUTX 0 <-- +IW L1_PUTS_only 0 <-- +IW L1_PUTS 0 <-- +IW Fwd_GETX 0 <-- +IW Fwd_GETS 0 <-- +IW Fwd_DMA 0 <-- +IW Inv 0 <-- +IW L1_WBCLEANDATA 0 <-- +IW L2_Replacement 0 <-- + +OW L1_GETS 0 <-- +OW L1_GETX 0 <-- +OW L1_PUTO 0 <-- +OW L1_PUTX 0 <-- +OW L1_PUTS_only 0 <-- +OW L1_PUTS 0 <-- +OW Fwd_GETX 0 <-- +OW Fwd_GETS 0 <-- +OW Fwd_DMA 0 <-- +OW Inv 0 <-- +OW Unblock 0 <-- +OW L2_Replacement 0 <-- + +SW L1_GETS 0 <-- +SW L1_GETX 0 <-- +SW L1_PUTO 0 <-- +SW L1_PUTX 0 <-- +SW L1_PUTS_only 0 <-- +SW L1_PUTS 0 <-- +SW Fwd_GETX 0 <-- +SW Fwd_GETS 0 <-- +SW Fwd_DMA 0 <-- +SW Inv 0 <-- +SW Unblock 0 <-- +SW L2_Replacement 0 <-- + +OXW L1_GETS 0 <-- +OXW L1_GETX 0 <-- +OXW L1_PUTO 0 <-- +OXW L1_PUTX 0 <-- +OXW L1_PUTS_only 0 <-- +OXW L1_PUTS 0 <-- +OXW Fwd_GETX 0 <-- +OXW Fwd_GETS 0 <-- +OXW Fwd_DMA 0 <-- +OXW Inv 0 <-- +OXW Unblock 0 <-- +OXW L2_Replacement 0 <-- + +OLSXW L1_GETS 0 <-- +OLSXW L1_GETX 0 <-- +OLSXW L1_PUTO 0 <-- +OLSXW L1_PUTX 0 <-- +OLSXW L1_PUTS_only 0 <-- +OLSXW L1_PUTS 0 <-- +OLSXW Fwd_GETX 0 <-- +OLSXW Fwd_GETS 0 <-- +OLSXW Fwd_DMA 0 <-- +OLSXW Inv 0 <-- +OLSXW Unblock 0 <-- +OLSXW L2_Replacement 0 <-- + +ILXW L1_GETS 78 +ILXW L1_GETX 38 +ILXW L1_PUTO 0 <-- +ILXW L1_PUTX 0 <-- +ILXW L1_PUTS_only 0 <-- +ILXW L1_PUTS 0 <-- +ILXW Fwd_GETX 0 <-- +ILXW Fwd_GETS 0 <-- +ILXW Fwd_DMA 0 <-- +ILXW Inv 0 <-- +ILXW Data 0 <-- +ILXW L1_WBCLEANDATA 2649 +ILXW L1_WBDIRTYDATA 356765 +ILXW Unblock 0 <-- +ILXW L2_Replacement 0 <-- + +IFLS L1_GETS 0 <-- +IFLS L1_GETX 0 <-- +IFLS L1_PUTO 0 <-- +IFLS L1_PUTX 0 <-- +IFLS L1_PUTS_only 0 <-- +IFLS L1_PUTS 0 <-- +IFLS Fwd_GETX 0 <-- +IFLS Fwd_GETS 0 <-- +IFLS Fwd_DMA 0 <-- +IFLS Inv 0 <-- +IFLS Unblock 0 <-- +IFLS L2_Replacement 0 <-- + +IFLO L1_GETS 0 <-- +IFLO L1_GETX 0 <-- +IFLO L1_PUTO 0 <-- +IFLO L1_PUTX 0 <-- +IFLO L1_PUTS_only 0 <-- +IFLO L1_PUTS 0 <-- +IFLO Fwd_GETX 0 <-- +IFLO Fwd_GETS 0 <-- +IFLO Fwd_DMA 0 <-- +IFLO Inv 0 <-- +IFLO Unblock 0 <-- +IFLO L2_Replacement 0 <-- + +IFLOX L1_GETS 0 <-- +IFLOX L1_GETX 0 <-- +IFLOX L1_PUTO 0 <-- +IFLOX L1_PUTX 0 <-- +IFLOX L1_PUTS_only 0 <-- +IFLOX L1_PUTS 0 <-- +IFLOX Fwd_GETX 0 <-- +IFLOX Fwd_GETS 0 <-- +IFLOX Fwd_DMA 0 <-- +IFLOX Inv 0 <-- +IFLOX Unblock 0 <-- +IFLOX Exclusive_Unblock 0 <-- +IFLOX L2_Replacement 0 <-- + +IFLOXX L1_GETS 0 <-- +IFLOXX L1_GETX 0 <-- +IFLOXX L1_PUTO 0 <-- +IFLOXX L1_PUTX 0 <-- +IFLOXX L1_PUTS_only 0 <-- +IFLOXX L1_PUTS 0 <-- +IFLOXX Fwd_GETX 0 <-- +IFLOXX Fwd_GETS 0 <-- +IFLOXX Fwd_DMA 0 <-- +IFLOXX Inv 0 <-- +IFLOXX Unblock 0 <-- +IFLOXX Exclusive_Unblock 0 <-- +IFLOXX L2_Replacement 0 <-- + +IFLOSX L1_GETS 0 <-- +IFLOSX L1_GETX 0 <-- +IFLOSX L1_PUTO 0 <-- +IFLOSX L1_PUTX 0 <-- +IFLOSX L1_PUTS_only 0 <-- +IFLOSX L1_PUTS 0 <-- +IFLOSX Fwd_GETX 0 <-- +IFLOSX Fwd_GETS 0 <-- +IFLOSX Fwd_DMA 0 <-- +IFLOSX Inv 0 <-- +IFLOSX Unblock 0 <-- +IFLOSX Exclusive_Unblock 0 <-- +IFLOSX L2_Replacement 0 <-- + +IFLXO L1_GETS 0 <-- +IFLXO L1_GETX 0 <-- +IFLXO L1_PUTO 0 <-- +IFLXO L1_PUTX 0 <-- +IFLXO L1_PUTS_only 0 <-- +IFLXO L1_PUTS 0 <-- +IFLXO Fwd_GETX 0 <-- +IFLXO Fwd_GETS 0 <-- +IFLXO Fwd_DMA 0 <-- +IFLXO Inv 0 <-- +IFLXO Exclusive_Unblock 0 <-- +IFLXO L2_Replacement 0 <-- + +IGS L1_GETS 0 <-- +IGS L1_GETX 0 <-- +IGS L1_PUTO 0 <-- +IGS L1_PUTX 0 <-- +IGS L1_PUTS_only 0 <-- +IGS L1_PUTS 0 <-- +IGS Fwd_GETX 0 <-- +IGS Fwd_GETS 0 <-- +IGS Fwd_DMA 0 <-- +IGS Own_GETX 0 <-- +IGS Inv 0 <-- +IGS Data 0 <-- +IGS Data_Exclusive 992 +IGS Unblock 0 <-- +IGS Exclusive_Unblock 992 +IGS L2_Replacement 0 <-- + +IGM L1_GETS 0 <-- +IGM L1_GETX 0 <-- +IGM L1_PUTO 0 <-- +IGM L1_PUTX 0 <-- +IGM L1_PUTS_only 0 <-- +IGM L1_PUTS 0 <-- +IGM Fwd_GETX 0 <-- +IGM Fwd_GETS 0 <-- +IGM Fwd_DMA 0 <-- +IGM Own_GETX 0 <-- +IGM Inv 0 <-- +IGM ExtAck 0 <-- +IGM Data 516 +IGM Data_Exclusive 0 <-- +IGM L2_Replacement 0 <-- + +IGMLS L1_GETS 0 <-- +IGMLS L1_GETX 0 <-- +IGMLS L1_PUTO 0 <-- +IGMLS L1_PUTX 0 <-- +IGMLS L1_PUTS_only 0 <-- +IGMLS L1_PUTS 0 <-- +IGMLS Inv 0 <-- +IGMLS IntAck 0 <-- +IGMLS ExtAck 0 <-- +IGMLS All_Acks 0 <-- +IGMLS Data 0 <-- +IGMLS Data_Exclusive 0 <-- +IGMLS L2_Replacement 0 <-- + +IGMO L1_GETS 0 <-- +IGMO L1_GETX 0 <-- +IGMO L1_PUTO 0 <-- +IGMO L1_PUTX 0 <-- +IGMO L1_PUTS_only 0 <-- +IGMO L1_PUTS 0 <-- +IGMO Fwd_GETX 0 <-- +IGMO Fwd_GETS 0 <-- +IGMO Fwd_DMA 0 <-- +IGMO Own_GETX 0 <-- +IGMO ExtAck 0 <-- +IGMO All_Acks 516 +IGMO Exclusive_Unblock 516 +IGMO L2_Replacement 0 <-- + +IGMIO L1_GETS 0 <-- +IGMIO L1_GETX 0 <-- +IGMIO L1_PUTO 0 <-- +IGMIO L1_PUTX 0 <-- +IGMIO L1_PUTS_only 0 <-- +IGMIO L1_PUTS 0 <-- +IGMIO Fwd_GETX 0 <-- +IGMIO Fwd_GETS 0 <-- +IGMIO Fwd_DMA 0 <-- +IGMIO Own_GETX 0 <-- +IGMIO ExtAck 0 <-- +IGMIO All_Acks 0 <-- + +OGMIO L1_GETS 0 <-- +OGMIO L1_GETX 0 <-- +OGMIO L1_PUTO 0 <-- +OGMIO L1_PUTX 0 <-- +OGMIO L1_PUTS_only 0 <-- +OGMIO L1_PUTS 0 <-- +OGMIO Fwd_GETX 0 <-- +OGMIO Fwd_GETS 0 <-- +OGMIO Fwd_DMA 0 <-- +OGMIO Own_GETX 0 <-- +OGMIO ExtAck 0 <-- +OGMIO All_Acks 0 <-- + +IGMIOF L1_GETS 0 <-- +IGMIOF L1_GETX 0 <-- +IGMIOF L1_PUTO 0 <-- +IGMIOF L1_PUTX 0 <-- +IGMIOF L1_PUTS_only 0 <-- +IGMIOF L1_PUTS 0 <-- +IGMIOF IntAck 0 <-- +IGMIOF All_Acks 0 <-- +IGMIOF Data_Exclusive 0 <-- + +IGMIOFS L1_GETS 0 <-- +IGMIOFS L1_GETX 0 <-- +IGMIOFS L1_PUTO 0 <-- +IGMIOFS L1_PUTX 0 <-- +IGMIOFS L1_PUTS_only 0 <-- +IGMIOFS L1_PUTS 0 <-- +IGMIOFS Fwd_GETX 0 <-- +IGMIOFS Fwd_GETS 0 <-- +IGMIOFS Fwd_DMA 0 <-- +IGMIOFS Inv 0 <-- +IGMIOFS Data 0 <-- +IGMIOFS L2_Replacement 0 <-- + +OGMIOF L1_GETS 0 <-- +OGMIOF L1_GETX 0 <-- +OGMIOF L1_PUTO 0 <-- +OGMIOF L1_PUTX 0 <-- +OGMIOF L1_PUTS_only 0 <-- +OGMIOF L1_PUTS 0 <-- +OGMIOF IntAck 0 <-- +OGMIOF All_Acks 0 <-- + +II L1_GETS 0 <-- +II L1_GETX 0 <-- +II L1_PUTO 0 <-- +II L1_PUTX 0 <-- +II L1_PUTS_only 0 <-- +II L1_PUTS 0 <-- +II IntAck 0 <-- +II All_Acks 0 <-- + +MM L1_GETS 0 <-- +MM L1_GETX 0 <-- +MM L1_PUTO 0 <-- +MM L1_PUTX 0 <-- +MM L1_PUTS_only 0 <-- +MM L1_PUTS 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- +MM Inv 0 <-- +MM Exclusive_Unblock 125126 +MM L2_Replacement 0 <-- + +SS L1_GETS 0 <-- +SS L1_GETX 0 <-- +SS L1_PUTO 0 <-- +SS L1_PUTX 0 <-- +SS L1_PUTS_only 0 <-- +SS L1_PUTS 0 <-- +SS Fwd_GETX 0 <-- +SS Fwd_GETS 0 <-- +SS Fwd_DMA 0 <-- +SS Inv 0 <-- +SS Unblock 0 <-- +SS L2_Replacement 0 <-- + +OO L1_GETS 0 <-- +OO L1_GETX 0 <-- +OO L1_PUTO 0 <-- +OO L1_PUTX 0 <-- +OO L1_PUTS_only 0 <-- +OO L1_PUTS 0 <-- +OO Fwd_GETX 0 <-- +OO Fwd_GETS 0 <-- +OO Fwd_DMA 0 <-- +OO Inv 0 <-- +OO Unblock 0 <-- +OO Exclusive_Unblock 232844 +OO L2_Replacement 0 <-- + +OLSS L1_GETS 0 <-- +OLSS L1_GETX 0 <-- +OLSS L1_PUTO 0 <-- +OLSS L1_PUTX 0 <-- +OLSS L1_PUTS_only 0 <-- +OLSS L1_PUTS 0 <-- +OLSS Fwd_GETX 0 <-- +OLSS Fwd_GETS 0 <-- +OLSS Fwd_DMA 0 <-- +OLSS Inv 0 <-- +OLSS Unblock 0 <-- +OLSS L2_Replacement 0 <-- + +OLSXS L1_GETS 0 <-- +OLSXS L1_GETX 0 <-- +OLSXS L1_PUTO 0 <-- +OLSXS L1_PUTX 0 <-- +OLSXS L1_PUTS_only 0 <-- +OLSXS L1_PUTS 0 <-- +OLSXS Fwd_GETX 0 <-- +OLSXS Fwd_GETS 0 <-- +OLSXS Fwd_DMA 0 <-- +OLSXS Inv 0 <-- +OLSXS Unblock 0 <-- +OLSXS L2_Replacement 0 <-- + +SLSS L1_GETS 0 <-- +SLSS L1_GETX 0 <-- +SLSS L1_PUTO 0 <-- +SLSS L1_PUTX 0 <-- +SLSS L1_PUTS_only 0 <-- +SLSS L1_PUTS 0 <-- +SLSS Fwd_GETX 0 <-- +SLSS Fwd_GETS 0 <-- +SLSS Fwd_DMA 0 <-- +SLSS Inv 0 <-- +SLSS Unblock 0 <-- +SLSS L2_Replacement 0 <-- + +OI L1_GETS 0 <-- +OI L1_GETX 0 <-- +OI L1_PUTO 0 <-- +OI L1_PUTX 0 <-- +OI L1_PUTS_only 0 <-- +OI L1_PUTS 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Nack 0 <-- +OI L2_Replacement 0 <-- + +MI L1_GETS 0 <-- +MI L1_GETX 0 <-- +MI L1_PUTO 0 <-- +MI L1_PUTX 0 <-- +MI L1_PUTS_only 0 <-- +MI L1_PUTS 0 <-- +MI Fwd_GETX 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- +MI Writeback_Ack 0 <-- +MI L2_Replacement 0 <-- + +MII L1_GETS 0 <-- +MII L1_GETX 0 <-- +MII L1_PUTO 0 <-- +MII L1_PUTX 0 <-- +MII L1_PUTS_only 0 <-- +MII L1_PUTS 0 <-- +MII Writeback_Ack 0 <-- +MII Writeback_Nack 0 <-- +MII L2_Replacement 0 <-- + +OLSI L1_GETS 0 <-- +OLSI L1_GETX 0 <-- +OLSI L1_PUTO 0 <-- +OLSI L1_PUTX 0 <-- +OLSI L1_PUTS_only 0 <-- +OLSI L1_PUTS 0 <-- +OLSI Fwd_GETX 0 <-- +OLSI Fwd_GETS 0 <-- +OLSI Fwd_DMA 0 <-- +OLSI Writeback_Ack 0 <-- +OLSI L2_Replacement 0 <-- + +ILSI L1_GETS 0 <-- +ILSI L1_GETX 0 <-- +ILSI L1_PUTO 0 <-- +ILSI L1_PUTX 0 <-- +ILSI L1_PUTS_only 0 <-- +ILSI L1_PUTS 0 <-- +ILSI IntAck 0 <-- +ILSI All_Acks 0 <-- +ILSI Writeback_Ack 0 <-- +ILSI L2_Replacement 0 <-- + + --- L2Cache 1 --- + - Event Counts - +L1_GETS 234483 +L1_GETX 126367 +L1_PUTO 0 +L1_PUTX 360682 +L1_PUTS_only 0 +L1_PUTS 0 +Fwd_GETX 0 +Fwd_GETS 0 +Fwd_DMA 0 +Own_GETX 0 +Inv 0 +IntAck 0 +ExtAck 0 +All_Acks 506 +Data 506 +Data_Exclusive 991 +L1_WBCLEANDATA 2626 +L1_WBDIRTYDATA 358053 +Writeback_Ack 0 +Writeback_Nack 0 +Unblock 0 +Exclusive_Unblock 360743 +L2_Replacement 0 + + - Transitions - +NP L1_GETS 991 +NP L1_GETX 506 +NP L1_PUTO 0 <-- +NP L1_PUTX 0 <-- +NP L1_PUTS 0 <-- +NP Inv 0 <-- + +I L1_GETS 0 <-- +I L1_GETX 0 <-- +I L1_PUTO 0 <-- +I L1_PUTX 0 <-- +I L1_PUTS 0 <-- +I Inv 0 <-- +I L2_Replacement 0 <-- + +ILS L1_GETS 0 <-- +ILS L1_GETX 0 <-- +ILS L1_PUTO 0 <-- +ILS L1_PUTX 0 <-- +ILS L1_PUTS_only 0 <-- +ILS L1_PUTS 0 <-- +ILS Inv 0 <-- +ILS L2_Replacement 0 <-- + +ILX L1_GETS 0 <-- +ILX L1_GETX 0 <-- +ILX L1_PUTO 0 <-- +ILX L1_PUTX 360682 +ILX L1_PUTS_only 0 <-- +ILX L1_PUTS 0 <-- +ILX Fwd_GETX 0 <-- +ILX Fwd_GETS 0 <-- +ILX Fwd_DMA 0 <-- +ILX Inv 0 <-- +ILX Data 0 <-- +ILX L2_Replacement 0 <-- + +ILO L1_GETS 0 <-- +ILO L1_GETX 0 <-- +ILO L1_PUTO 0 <-- +ILO L1_PUTX 0 <-- +ILO L1_PUTS 0 <-- +ILO Fwd_GETX 0 <-- +ILO Fwd_GETS 0 <-- +ILO Fwd_DMA 0 <-- +ILO Inv 0 <-- +ILO Data 0 <-- +ILO L2_Replacement 0 <-- + +ILOX L1_GETS 0 <-- +ILOX L1_GETX 0 <-- +ILOX L1_PUTO 0 <-- +ILOX L1_PUTX 0 <-- +ILOX L1_PUTS 0 <-- +ILOX Fwd_GETX 0 <-- +ILOX Fwd_GETS 0 <-- +ILOX Fwd_DMA 0 <-- +ILOX Data 0 <-- + +ILOS L1_GETS 0 <-- +ILOS L1_GETX 0 <-- +ILOS L1_PUTO 0 <-- +ILOS L1_PUTX 0 <-- +ILOS L1_PUTS_only 0 <-- +ILOS L1_PUTS 0 <-- +ILOS Fwd_GETX 0 <-- +ILOS Fwd_GETS 0 <-- +ILOS Fwd_DMA 0 <-- +ILOS Data 0 <-- +ILOS L2_Replacement 0 <-- + +ILOSX L1_GETS 0 <-- +ILOSX L1_GETX 0 <-- +ILOSX L1_PUTO 0 <-- +ILOSX L1_PUTX 0 <-- +ILOSX L1_PUTS_only 0 <-- +ILOSX L1_PUTS 0 <-- +ILOSX Fwd_GETX 0 <-- +ILOSX Fwd_GETS 0 <-- +ILOSX Fwd_DMA 0 <-- +ILOSX Data 0 <-- + +S L1_GETS 0 <-- +S L1_GETX 0 <-- +S L1_PUTX 0 <-- +S L1_PUTS 0 <-- +S Inv 0 <-- +S L2_Replacement 0 <-- + +O L1_GETS 0 <-- +O L1_GETX 0 <-- +O L1_PUTX 0 <-- +O Fwd_GETX 0 <-- +O Fwd_GETS 0 <-- +O Fwd_DMA 0 <-- +O L2_Replacement 0 <-- + +OLS L1_GETS 0 <-- +OLS L1_GETX 0 <-- +OLS L1_PUTX 0 <-- +OLS L1_PUTS_only 0 <-- +OLS L1_PUTS 0 <-- +OLS Fwd_GETX 0 <-- +OLS Fwd_GETS 0 <-- +OLS Fwd_DMA 0 <-- +OLS L2_Replacement 0 <-- + +OLSX L1_GETS 0 <-- +OLSX L1_GETX 0 <-- +OLSX L1_PUTO 0 <-- +OLSX L1_PUTX 0 <-- +OLSX L1_PUTS_only 0 <-- +OLSX L1_PUTS 0 <-- +OLSX Fwd_GETX 0 <-- +OLSX Fwd_GETS 0 <-- +OLSX Fwd_DMA 0 <-- +OLSX L2_Replacement 0 <-- + +SLS L1_GETS 0 <-- +SLS L1_GETX 0 <-- +SLS L1_PUTX 0 <-- +SLS L1_PUTS_only 0 <-- +SLS L1_PUTS 0 <-- +SLS Inv 0 <-- +SLS L2_Replacement 0 <-- + +M L1_GETS 233418 +M L1_GETX 125831 +M L1_PUTO 0 <-- +M L1_PUTX 0 <-- +M L1_PUTS 0 <-- +M Fwd_GETX 0 <-- +M Fwd_GETS 0 <-- +M Fwd_DMA 0 <-- +M L2_Replacement 0 <-- + +IFGX L1_GETS 0 <-- +IFGX L1_GETX 0 <-- +IFGX L1_PUTO 0 <-- +IFGX L1_PUTX 0 <-- +IFGX L1_PUTS_only 0 <-- +IFGX L1_PUTS 0 <-- +IFGX Fwd_GETX 0 <-- +IFGX Fwd_GETS 0 <-- +IFGX Fwd_DMA 0 <-- +IFGX Inv 0 <-- +IFGX Data 0 <-- +IFGX Data_Exclusive 0 <-- +IFGX L2_Replacement 0 <-- + +IFGS L1_GETS 0 <-- +IFGS L1_GETX 0 <-- +IFGS L1_PUTO 0 <-- +IFGS L1_PUTX 0 <-- +IFGS L1_PUTS_only 0 <-- +IFGS L1_PUTS 0 <-- +IFGS Fwd_GETX 0 <-- +IFGS Fwd_GETS 0 <-- +IFGS Fwd_DMA 0 <-- +IFGS Inv 0 <-- +IFGS Data 0 <-- +IFGS Data_Exclusive 0 <-- +IFGS L2_Replacement 0 <-- + +ISFGS L1_GETS 0 <-- +ISFGS L1_GETX 0 <-- +ISFGS L1_PUTO 0 <-- +ISFGS L1_PUTX 0 <-- +ISFGS L1_PUTS_only 0 <-- +ISFGS L1_PUTS 0 <-- +ISFGS Fwd_GETX 0 <-- +ISFGS Fwd_GETS 0 <-- +ISFGS Fwd_DMA 0 <-- +ISFGS Inv 0 <-- +ISFGS Data 0 <-- +ISFGS L2_Replacement 0 <-- + +IFGXX L1_GETS 0 <-- +IFGXX L1_GETX 0 <-- +IFGXX L1_PUTO 0 <-- +IFGXX L1_PUTX 0 <-- +IFGXX L1_PUTS_only 0 <-- +IFGXX L1_PUTS 0 <-- +IFGXX Fwd_GETX 0 <-- +IFGXX Fwd_GETS 0 <-- +IFGXX Fwd_DMA 0 <-- +IFGXX Inv 0 <-- +IFGXX IntAck 0 <-- +IFGXX All_Acks 0 <-- +IFGXX Data_Exclusive 0 <-- +IFGXX L2_Replacement 0 <-- + +OFGX L1_GETS 0 <-- +OFGX L1_GETX 0 <-- +OFGX L1_PUTO 0 <-- +OFGX L1_PUTX 0 <-- +OFGX L1_PUTS_only 0 <-- +OFGX L1_PUTS 0 <-- +OFGX Fwd_GETX 0 <-- +OFGX Fwd_GETS 0 <-- +OFGX Fwd_DMA 0 <-- +OFGX Inv 0 <-- +OFGX L2_Replacement 0 <-- + +OLSF L1_GETS 0 <-- +OLSF L1_GETX 0 <-- +OLSF L1_PUTO 0 <-- +OLSF L1_PUTX 0 <-- +OLSF L1_PUTS_only 0 <-- +OLSF L1_PUTS 0 <-- +OLSF Fwd_GETX 0 <-- +OLSF Fwd_GETS 0 <-- +OLSF Fwd_DMA 0 <-- +OLSF Inv 0 <-- +OLSF IntAck 0 <-- +OLSF All_Acks 0 <-- +OLSF L2_Replacement 0 <-- + +ILOW L1_GETS 0 <-- +ILOW L1_GETX 0 <-- +ILOW L1_PUTO 0 <-- +ILOW L1_PUTX 0 <-- +ILOW L1_PUTS_only 0 <-- +ILOW L1_PUTS 0 <-- +ILOW Fwd_GETX 0 <-- +ILOW Fwd_GETS 0 <-- +ILOW Fwd_DMA 0 <-- +ILOW Inv 0 <-- +ILOW L1_WBCLEANDATA 0 <-- +ILOW L1_WBDIRTYDATA 0 <-- +ILOW Unblock 0 <-- +ILOW L2_Replacement 0 <-- + +ILOXW L1_GETS 0 <-- +ILOXW L1_GETX 0 <-- +ILOXW L1_PUTO 0 <-- +ILOXW L1_PUTX 0 <-- +ILOXW L1_PUTS_only 0 <-- +ILOXW L1_PUTS 0 <-- +ILOXW Fwd_GETX 0 <-- +ILOXW Fwd_GETS 0 <-- +ILOXW Fwd_DMA 0 <-- +ILOXW Inv 0 <-- +ILOXW L1_WBCLEANDATA 0 <-- +ILOXW L1_WBDIRTYDATA 0 <-- +ILOXW Unblock 0 <-- +ILOXW L2_Replacement 0 <-- + +ILOSW L1_GETS 0 <-- +ILOSW L1_GETX 0 <-- +ILOSW L1_PUTO 0 <-- +ILOSW L1_PUTX 0 <-- +ILOSW L1_PUTS_only 0 <-- +ILOSW L1_PUTS 0 <-- +ILOSW Fwd_GETX 0 <-- +ILOSW Fwd_GETS 0 <-- +ILOSW Fwd_DMA 0 <-- +ILOSW Inv 0 <-- +ILOSW L1_WBCLEANDATA 0 <-- +ILOSW L1_WBDIRTYDATA 0 <-- +ILOSW Unblock 0 <-- +ILOSW L2_Replacement 0 <-- + +ILOSXW L1_GETS 0 <-- +ILOSXW L1_GETX 0 <-- +ILOSXW L1_PUTO 0 <-- +ILOSXW L1_PUTX 0 <-- +ILOSXW L1_PUTS_only 0 <-- +ILOSXW L1_PUTS 0 <-- +ILOSXW Fwd_GETX 0 <-- +ILOSXW Fwd_GETS 0 <-- +ILOSXW Fwd_DMA 0 <-- +ILOSXW Inv 0 <-- +ILOSXW L1_WBCLEANDATA 0 <-- +ILOSXW L1_WBDIRTYDATA 0 <-- +ILOSXW Unblock 0 <-- +ILOSXW L2_Replacement 0 <-- + +SLSW L1_GETS 0 <-- +SLSW L1_GETX 0 <-- +SLSW L1_PUTO 0 <-- +SLSW L1_PUTX 0 <-- +SLSW L1_PUTS_only 0 <-- +SLSW L1_PUTS 0 <-- +SLSW Fwd_GETX 0 <-- +SLSW Fwd_GETS 0 <-- +SLSW Fwd_DMA 0 <-- +SLSW Inv 0 <-- +SLSW Unblock 0 <-- +SLSW L2_Replacement 0 <-- + +OLSW L1_GETS 0 <-- +OLSW L1_GETX 0 <-- +OLSW L1_PUTO 0 <-- +OLSW L1_PUTX 0 <-- +OLSW L1_PUTS_only 0 <-- +OLSW L1_PUTS 0 <-- +OLSW Fwd_GETX 0 <-- +OLSW Fwd_GETS 0 <-- +OLSW Fwd_DMA 0 <-- +OLSW Inv 0 <-- +OLSW Unblock 0 <-- +OLSW L2_Replacement 0 <-- + +ILSW L1_GETS 0 <-- +ILSW L1_GETX 0 <-- +ILSW L1_PUTO 0 <-- +ILSW L1_PUTX 0 <-- +ILSW L1_PUTS_only 0 <-- +ILSW L1_PUTS 0 <-- +ILSW Fwd_GETX 0 <-- +ILSW Fwd_GETS 0 <-- +ILSW Fwd_DMA 0 <-- +ILSW Inv 0 <-- +ILSW L1_WBCLEANDATA 0 <-- +ILSW Unblock 0 <-- +ILSW L2_Replacement 0 <-- + +IW L1_GETS 0 <-- +IW L1_GETX 0 <-- +IW L1_PUTO 0 <-- +IW L1_PUTX 0 <-- +IW L1_PUTS_only 0 <-- +IW L1_PUTS 0 <-- +IW Fwd_GETX 0 <-- +IW Fwd_GETS 0 <-- +IW Fwd_DMA 0 <-- +IW Inv 0 <-- +IW L1_WBCLEANDATA 0 <-- +IW L2_Replacement 0 <-- + +OW L1_GETS 0 <-- +OW L1_GETX 0 <-- +OW L1_PUTO 0 <-- +OW L1_PUTX 0 <-- +OW L1_PUTS_only 0 <-- +OW L1_PUTS 0 <-- +OW Fwd_GETX 0 <-- +OW Fwd_GETS 0 <-- +OW Fwd_DMA 0 <-- +OW Inv 0 <-- +OW Unblock 0 <-- +OW L2_Replacement 0 <-- + +SW L1_GETS 0 <-- +SW L1_GETX 0 <-- +SW L1_PUTO 0 <-- +SW L1_PUTX 0 <-- +SW L1_PUTS_only 0 <-- +SW L1_PUTS 0 <-- +SW Fwd_GETX 0 <-- +SW Fwd_GETS 0 <-- +SW Fwd_DMA 0 <-- +SW Inv 0 <-- +SW Unblock 0 <-- +SW L2_Replacement 0 <-- + +OXW L1_GETS 0 <-- +OXW L1_GETX 0 <-- +OXW L1_PUTO 0 <-- +OXW L1_PUTX 0 <-- +OXW L1_PUTS_only 0 <-- +OXW L1_PUTS 0 <-- +OXW Fwd_GETX 0 <-- +OXW Fwd_GETS 0 <-- +OXW Fwd_DMA 0 <-- +OXW Inv 0 <-- +OXW Unblock 0 <-- +OXW L2_Replacement 0 <-- + +OLSXW L1_GETS 0 <-- +OLSXW L1_GETX 0 <-- +OLSXW L1_PUTO 0 <-- +OLSXW L1_PUTX 0 <-- +OLSXW L1_PUTS_only 0 <-- +OLSXW L1_PUTS 0 <-- +OLSXW Fwd_GETX 0 <-- +OLSXW Fwd_GETS 0 <-- +OLSXW Fwd_DMA 0 <-- +OLSXW Inv 0 <-- +OLSXW Unblock 0 <-- +OLSXW L2_Replacement 0 <-- + +ILXW L1_GETS 74 +ILXW L1_GETX 30 +ILXW L1_PUTO 0 <-- +ILXW L1_PUTX 0 <-- +ILXW L1_PUTS_only 0 <-- +ILXW L1_PUTS 0 <-- +ILXW Fwd_GETX 0 <-- +ILXW Fwd_GETS 0 <-- +ILXW Fwd_DMA 0 <-- +ILXW Inv 0 <-- +ILXW Data 0 <-- +ILXW L1_WBCLEANDATA 2626 +ILXW L1_WBDIRTYDATA 358053 +ILXW Unblock 0 <-- +ILXW L2_Replacement 0 <-- + +IFLS L1_GETS 0 <-- +IFLS L1_GETX 0 <-- +IFLS L1_PUTO 0 <-- +IFLS L1_PUTX 0 <-- +IFLS L1_PUTS_only 0 <-- +IFLS L1_PUTS 0 <-- +IFLS Fwd_GETX 0 <-- +IFLS Fwd_GETS 0 <-- +IFLS Fwd_DMA 0 <-- +IFLS Inv 0 <-- +IFLS Unblock 0 <-- +IFLS L2_Replacement 0 <-- + +IFLO L1_GETS 0 <-- +IFLO L1_GETX 0 <-- +IFLO L1_PUTO 0 <-- +IFLO L1_PUTX 0 <-- +IFLO L1_PUTS_only 0 <-- +IFLO L1_PUTS 0 <-- +IFLO Fwd_GETX 0 <-- +IFLO Fwd_GETS 0 <-- +IFLO Fwd_DMA 0 <-- +IFLO Inv 0 <-- +IFLO Unblock 0 <-- +IFLO L2_Replacement 0 <-- + +IFLOX L1_GETS 0 <-- +IFLOX L1_GETX 0 <-- +IFLOX L1_PUTO 0 <-- +IFLOX L1_PUTX 0 <-- +IFLOX L1_PUTS_only 0 <-- +IFLOX L1_PUTS 0 <-- +IFLOX Fwd_GETX 0 <-- +IFLOX Fwd_GETS 0 <-- +IFLOX Fwd_DMA 0 <-- +IFLOX Inv 0 <-- +IFLOX Unblock 0 <-- +IFLOX Exclusive_Unblock 0 <-- +IFLOX L2_Replacement 0 <-- + +IFLOXX L1_GETS 0 <-- +IFLOXX L1_GETX 0 <-- +IFLOXX L1_PUTO 0 <-- +IFLOXX L1_PUTX 0 <-- +IFLOXX L1_PUTS_only 0 <-- +IFLOXX L1_PUTS 0 <-- +IFLOXX Fwd_GETX 0 <-- +IFLOXX Fwd_GETS 0 <-- +IFLOXX Fwd_DMA 0 <-- +IFLOXX Inv 0 <-- +IFLOXX Unblock 0 <-- +IFLOXX Exclusive_Unblock 0 <-- +IFLOXX L2_Replacement 0 <-- + +IFLOSX L1_GETS 0 <-- +IFLOSX L1_GETX 0 <-- +IFLOSX L1_PUTO 0 <-- +IFLOSX L1_PUTX 0 <-- +IFLOSX L1_PUTS_only 0 <-- +IFLOSX L1_PUTS 0 <-- +IFLOSX Fwd_GETX 0 <-- +IFLOSX Fwd_GETS 0 <-- +IFLOSX Fwd_DMA 0 <-- +IFLOSX Inv 0 <-- +IFLOSX Unblock 0 <-- +IFLOSX Exclusive_Unblock 0 <-- +IFLOSX L2_Replacement 0 <-- + +IFLXO L1_GETS 0 <-- +IFLXO L1_GETX 0 <-- +IFLXO L1_PUTO 0 <-- +IFLXO L1_PUTX 0 <-- +IFLXO L1_PUTS_only 0 <-- +IFLXO L1_PUTS 0 <-- +IFLXO Fwd_GETX 0 <-- +IFLXO Fwd_GETS 0 <-- +IFLXO Fwd_DMA 0 <-- +IFLXO Inv 0 <-- +IFLXO Exclusive_Unblock 0 <-- +IFLXO L2_Replacement 0 <-- + +IGS L1_GETS 0 <-- +IGS L1_GETX 0 <-- +IGS L1_PUTO 0 <-- +IGS L1_PUTX 0 <-- +IGS L1_PUTS_only 0 <-- +IGS L1_PUTS 0 <-- +IGS Fwd_GETX 0 <-- +IGS Fwd_GETS 0 <-- +IGS Fwd_DMA 0 <-- +IGS Own_GETX 0 <-- +IGS Inv 0 <-- +IGS Data 0 <-- +IGS Data_Exclusive 991 +IGS Unblock 0 <-- +IGS Exclusive_Unblock 991 +IGS L2_Replacement 0 <-- + +IGM L1_GETS 0 <-- +IGM L1_GETX 0 <-- +IGM L1_PUTO 0 <-- +IGM L1_PUTX 0 <-- +IGM L1_PUTS_only 0 <-- +IGM L1_PUTS 0 <-- +IGM Fwd_GETX 0 <-- +IGM Fwd_GETS 0 <-- +IGM Fwd_DMA 0 <-- +IGM Own_GETX 0 <-- +IGM Inv 0 <-- +IGM ExtAck 0 <-- +IGM Data 506 +IGM Data_Exclusive 0 <-- +IGM L2_Replacement 0 <-- + +IGMLS L1_GETS 0 <-- +IGMLS L1_GETX 0 <-- +IGMLS L1_PUTO 0 <-- +IGMLS L1_PUTX 0 <-- +IGMLS L1_PUTS_only 0 <-- +IGMLS L1_PUTS 0 <-- +IGMLS Inv 0 <-- +IGMLS IntAck 0 <-- +IGMLS ExtAck 0 <-- +IGMLS All_Acks 0 <-- +IGMLS Data 0 <-- +IGMLS Data_Exclusive 0 <-- +IGMLS L2_Replacement 0 <-- + +IGMO L1_GETS 0 <-- +IGMO L1_GETX 0 <-- +IGMO L1_PUTO 0 <-- +IGMO L1_PUTX 0 <-- +IGMO L1_PUTS_only 0 <-- +IGMO L1_PUTS 0 <-- +IGMO Fwd_GETX 0 <-- +IGMO Fwd_GETS 0 <-- +IGMO Fwd_DMA 0 <-- +IGMO Own_GETX 0 <-- +IGMO ExtAck 0 <-- +IGMO All_Acks 506 +IGMO Exclusive_Unblock 506 +IGMO L2_Replacement 0 <-- + +IGMIO L1_GETS 0 <-- +IGMIO L1_GETX 0 <-- +IGMIO L1_PUTO 0 <-- +IGMIO L1_PUTX 0 <-- +IGMIO L1_PUTS_only 0 <-- +IGMIO L1_PUTS 0 <-- +IGMIO Fwd_GETX 0 <-- +IGMIO Fwd_GETS 0 <-- +IGMIO Fwd_DMA 0 <-- +IGMIO Own_GETX 0 <-- +IGMIO ExtAck 0 <-- +IGMIO All_Acks 0 <-- + +OGMIO L1_GETS 0 <-- +OGMIO L1_GETX 0 <-- +OGMIO L1_PUTO 0 <-- +OGMIO L1_PUTX 0 <-- +OGMIO L1_PUTS_only 0 <-- +OGMIO L1_PUTS 0 <-- +OGMIO Fwd_GETX 0 <-- +OGMIO Fwd_GETS 0 <-- +OGMIO Fwd_DMA 0 <-- +OGMIO Own_GETX 0 <-- +OGMIO ExtAck 0 <-- +OGMIO All_Acks 0 <-- + +IGMIOF L1_GETS 0 <-- +IGMIOF L1_GETX 0 <-- +IGMIOF L1_PUTO 0 <-- +IGMIOF L1_PUTX 0 <-- +IGMIOF L1_PUTS_only 0 <-- +IGMIOF L1_PUTS 0 <-- +IGMIOF IntAck 0 <-- +IGMIOF All_Acks 0 <-- +IGMIOF Data_Exclusive 0 <-- + +IGMIOFS L1_GETS 0 <-- +IGMIOFS L1_GETX 0 <-- +IGMIOFS L1_PUTO 0 <-- +IGMIOFS L1_PUTX 0 <-- +IGMIOFS L1_PUTS_only 0 <-- +IGMIOFS L1_PUTS 0 <-- +IGMIOFS Fwd_GETX 0 <-- +IGMIOFS Fwd_GETS 0 <-- +IGMIOFS Fwd_DMA 0 <-- +IGMIOFS Inv 0 <-- +IGMIOFS Data 0 <-- +IGMIOFS L2_Replacement 0 <-- + +OGMIOF L1_GETS 0 <-- +OGMIOF L1_GETX 0 <-- +OGMIOF L1_PUTO 0 <-- +OGMIOF L1_PUTX 0 <-- +OGMIOF L1_PUTS_only 0 <-- +OGMIOF L1_PUTS 0 <-- +OGMIOF IntAck 0 <-- +OGMIOF All_Acks 0 <-- + +II L1_GETS 0 <-- +II L1_GETX 0 <-- +II L1_PUTO 0 <-- +II L1_PUTX 0 <-- +II L1_PUTS_only 0 <-- +II L1_PUTS 0 <-- +II IntAck 0 <-- +II All_Acks 0 <-- + +MM L1_GETS 0 <-- +MM L1_GETX 0 <-- +MM L1_PUTO 0 <-- +MM L1_PUTX 0 <-- +MM L1_PUTS_only 0 <-- +MM L1_PUTS 0 <-- +MM Fwd_GETX 0 <-- +MM Fwd_GETS 0 <-- +MM Fwd_DMA 0 <-- +MM Inv 0 <-- +MM Exclusive_Unblock 125831 +MM L2_Replacement 0 <-- + +SS L1_GETS 0 <-- +SS L1_GETX 0 <-- +SS L1_PUTO 0 <-- +SS L1_PUTX 0 <-- +SS L1_PUTS_only 0 <-- +SS L1_PUTS 0 <-- +SS Fwd_GETX 0 <-- +SS Fwd_GETS 0 <-- +SS Fwd_DMA 0 <-- +SS Inv 0 <-- +SS Unblock 0 <-- +SS L2_Replacement 0 <-- + +OO L1_GETS 0 <-- +OO L1_GETX 0 <-- +OO L1_PUTO 0 <-- +OO L1_PUTX 0 <-- +OO L1_PUTS_only 0 <-- +OO L1_PUTS 0 <-- +OO Fwd_GETX 0 <-- +OO Fwd_GETS 0 <-- +OO Fwd_DMA 0 <-- +OO Inv 0 <-- +OO Unblock 0 <-- +OO Exclusive_Unblock 233415 +OO L2_Replacement 0 <-- + +OLSS L1_GETS 0 <-- +OLSS L1_GETX 0 <-- +OLSS L1_PUTO 0 <-- +OLSS L1_PUTX 0 <-- +OLSS L1_PUTS_only 0 <-- +OLSS L1_PUTS 0 <-- +OLSS Fwd_GETX 0 <-- +OLSS Fwd_GETS 0 <-- +OLSS Fwd_DMA 0 <-- +OLSS Inv 0 <-- +OLSS Unblock 0 <-- +OLSS L2_Replacement 0 <-- + +OLSXS L1_GETS 0 <-- +OLSXS L1_GETX 0 <-- +OLSXS L1_PUTO 0 <-- +OLSXS L1_PUTX 0 <-- +OLSXS L1_PUTS_only 0 <-- +OLSXS L1_PUTS 0 <-- +OLSXS Fwd_GETX 0 <-- +OLSXS Fwd_GETS 0 <-- +OLSXS Fwd_DMA 0 <-- +OLSXS Inv 0 <-- +OLSXS Unblock 0 <-- +OLSXS L2_Replacement 0 <-- + +SLSS L1_GETS 0 <-- +SLSS L1_GETX 0 <-- +SLSS L1_PUTO 0 <-- +SLSS L1_PUTX 0 <-- +SLSS L1_PUTS_only 0 <-- +SLSS L1_PUTS 0 <-- +SLSS Fwd_GETX 0 <-- +SLSS Fwd_GETS 0 <-- +SLSS Fwd_DMA 0 <-- +SLSS Inv 0 <-- +SLSS Unblock 0 <-- +SLSS L2_Replacement 0 <-- + +OI L1_GETS 0 <-- +OI L1_GETX 0 <-- +OI L1_PUTO 0 <-- +OI L1_PUTX 0 <-- +OI L1_PUTS_only 0 <-- +OI L1_PUTS 0 <-- +OI Fwd_GETX 0 <-- +OI Fwd_GETS 0 <-- +OI Fwd_DMA 0 <-- +OI Writeback_Ack 0 <-- +OI Writeback_Nack 0 <-- +OI L2_Replacement 0 <-- + +MI L1_GETS 0 <-- +MI L1_GETX 0 <-- +MI L1_PUTO 0 <-- +MI L1_PUTX 0 <-- +MI L1_PUTS_only 0 <-- +MI L1_PUTS 0 <-- +MI Fwd_GETX 0 <-- +MI Fwd_GETS 0 <-- +MI Fwd_DMA 0 <-- +MI Writeback_Ack 0 <-- +MI L2_Replacement 0 <-- + +MII L1_GETS 0 <-- +MII L1_GETX 0 <-- +MII L1_PUTO 0 <-- +MII L1_PUTX 0 <-- +MII L1_PUTS_only 0 <-- +MII L1_PUTS 0 <-- +MII Writeback_Ack 0 <-- +MII Writeback_Nack 0 <-- +MII L2_Replacement 0 <-- + +OLSI L1_GETS 0 <-- +OLSI L1_GETX 0 <-- +OLSI L1_PUTO 0 <-- +OLSI L1_PUTX 0 <-- +OLSI L1_PUTS_only 0 <-- +OLSI L1_PUTS 0 <-- +OLSI Fwd_GETX 0 <-- +OLSI Fwd_GETS 0 <-- +OLSI Fwd_DMA 0 <-- +OLSI Writeback_Ack 0 <-- +OLSI L2_Replacement 0 <-- + +ILSI L1_GETS 0 <-- +ILSI L1_GETX 0 <-- +ILSI L1_PUTO 0 <-- +ILSI L1_PUTX 0 <-- +ILSI L1_PUTS_only 0 <-- +ILSI L1_PUTS 0 <-- +ILSI IntAck 0 <-- +ILSI All_Acks 0 <-- +ILSI Writeback_Ack 0 <-- +ILSI L2_Replacement 0 <-- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index 8fe2d4613..1903562ea 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,76 +1,74 @@ -["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024", "-C", "256", "-A", "2", "-D", "1"] -print config: 1 -system.cpu7: completed 10000 read accesses @7023642 -system.cpu5: completed 10000 read accesses @7028438 -system.cpu3: completed 10000 read accesses @7034626 -system.cpu1: completed 10000 read accesses @7035790 -system.cpu2: completed 10000 read accesses @7062558 -system.cpu6: completed 10000 read accesses @7078882 -system.cpu0: completed 10000 read accesses @7080455 -system.cpu4: completed 10000 read accesses @7095500 -system.cpu1: completed 20000 read accesses @12915324 -system.cpu3: completed 20000 read accesses @12958052 -system.cpu5: completed 20000 read accesses @12993554 -system.cpu2: completed 20000 read accesses @13010879 -system.cpu4: completed 20000 read accesses @13014760 -system.cpu6: completed 20000 read accesses @13031684 -system.cpu7: completed 20000 read accesses @13051162 -system.cpu0: completed 20000 read accesses @13128234 -system.cpu3: completed 30000 read accesses @18784435 -system.cpu1: completed 30000 read accesses @18859194 -system.cpu5: completed 30000 read accesses @18903265 -system.cpu7: completed 30000 read accesses @18952860 -system.cpu4: completed 30000 read accesses @18981745 -system.cpu6: completed 30000 read accesses @18987772 -system.cpu0: completed 30000 read accesses @18993365 -system.cpu2: completed 30000 read accesses @18994061 -system.cpu3: completed 40000 read accesses @24748372 -system.cpu2: completed 40000 read accesses @24758090 -system.cpu1: completed 40000 read accesses @24768884 -system.cpu7: completed 40000 read accesses @24891866 -system.cpu0: completed 40000 read accesses @24907680 -system.cpu6: completed 40000 read accesses @24933908 -system.cpu5: completed 40000 read accesses @24949374 -system.cpu4: completed 40000 read accesses @24963853 -system.cpu3: completed 50000 read accesses @30655893 -system.cpu2: completed 50000 read accesses @30705287 -system.cpu1: completed 50000 read accesses @30752130 -system.cpu0: completed 50000 read accesses @30795942 -system.cpu5: completed 50000 read accesses @30809328 -system.cpu7: completed 50000 read accesses @30857254 -system.cpu6: completed 50000 read accesses @30935432 -system.cpu4: completed 50000 read accesses @30960853 -system.cpu3: completed 60000 read accesses @36647735 -system.cpu2: completed 60000 read accesses @36648110 -system.cpu1: completed 60000 read accesses @36690971 -system.cpu7: completed 60000 read accesses @36746000 -system.cpu5: completed 60000 read accesses @36746430 -system.cpu0: completed 60000 read accesses @36840602 -system.cpu6: completed 60000 read accesses @36900332 -system.cpu4: completed 60000 read accesses @36954562 -system.cpu2: completed 70000 read accesses @42614948 -system.cpu1: completed 70000 read accesses @42616200 -system.cpu5: completed 70000 read accesses @42679549 -system.cpu7: completed 70000 read accesses @42707038 -system.cpu3: completed 70000 read accesses @42725206 -system.cpu0: completed 70000 read accesses @42774272 -system.cpu6: completed 70000 read accesses @42850956 -system.cpu4: completed 70000 read accesses @42872700 -system.cpu5: completed 80000 read accesses @48577066 -system.cpu7: completed 80000 read accesses @48608169 -system.cpu2: completed 80000 read accesses @48616581 -system.cpu1: completed 80000 read accesses @48637808 -system.cpu0: completed 80000 read accesses @48726360 -system.cpu3: completed 80000 read accesses @48754087 -system.cpu4: completed 80000 read accesses @48848416 -system.cpu6: completed 80000 read accesses @48849321 -system.cpu5: completed 90000 read accesses @54536042 -system.cpu0: completed 90000 read accesses @54536954 -system.cpu7: completed 90000 read accesses @54554538 -system.cpu1: completed 90000 read accesses @54575168 -system.cpu2: completed 90000 read accesses @54648034 -system.cpu3: completed 90000 read accesses @54719200 -system.cpu6: completed 90000 read accesses @54807510 -system.cpu4: completed 90000 read accesses @54840954 -system.cpu1: completed 100000 read accesses @60455258 +["-c", "MOESI_CMP_directory", "-r", "tests/configs/../../src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb", "-p", "8", "-m", "1", "-s", "1024", "-C", "32768", "-A", "8", "-D", "1"] +system.cpu0: completed 10000 read accesses @449430 +system.cpu4: completed 10000 read accesses @459465 +system.cpu7: completed 10000 read accesses @472231 +system.cpu1: completed 10000 read accesses @477652 +system.cpu2: completed 10000 read accesses @477942 +system.cpu5: completed 10000 read accesses @490692 +system.cpu6: completed 10000 read accesses @490860 +system.cpu3: completed 10000 read accesses @498830 +system.cpu0: completed 20000 read accesses @902454 +system.cpu4: completed 20000 read accesses @921903 +system.cpu7: completed 20000 read accesses @943132 +system.cpu2: completed 20000 read accesses @963224 +system.cpu1: completed 20000 read accesses @974292 +system.cpu5: completed 20000 read accesses @979817 +system.cpu6: completed 20000 read accesses @985156 +system.cpu3: completed 20000 read accesses @1004197 +system.cpu0: completed 30000 read accesses @1354388 +system.cpu4: completed 30000 read accesses @1389321 +system.cpu7: completed 30000 read accesses @1410714 +system.cpu2: completed 30000 read accesses @1450104 +system.cpu5: completed 30000 read accesses @1465068 +system.cpu1: completed 30000 read accesses @1470940 +system.cpu6: completed 30000 read accesses @1477854 +system.cpu3: completed 30000 read accesses @1508078 +system.cpu0: completed 40000 read accesses @1811799 +system.cpu4: completed 40000 read accesses @1844299 +system.cpu7: completed 40000 read accesses @1889814 +system.cpu2: completed 40000 read accesses @1927073 +system.cpu1: completed 40000 read accesses @1953874 +system.cpu5: completed 40000 read accesses @1957168 +system.cpu6: completed 40000 read accesses @1970748 +system.cpu3: completed 40000 read accesses @2016002 +system.cpu0: completed 50000 read accesses @2262162 +system.cpu4: completed 50000 read accesses @2303172 +system.cpu7: completed 50000 read accesses @2354840 +system.cpu2: completed 50000 read accesses @2408362 +system.cpu1: completed 50000 read accesses @2441228 +system.cpu5: completed 50000 read accesses @2451414 +system.cpu6: completed 50000 read accesses @2467657 +system.cpu3: completed 50000 read accesses @2528058 +system.cpu0: completed 60000 read accesses @2711396 +system.cpu4: completed 60000 read accesses @2767668 +system.cpu7: completed 60000 read accesses @2817212 +system.cpu2: completed 60000 read accesses @2897042 +system.cpu1: completed 60000 read accesses @2926178 +system.cpu5: completed 60000 read accesses @2935676 +system.cpu6: completed 60000 read accesses @2963110 +system.cpu3: completed 60000 read accesses @3030360 +system.cpu0: completed 70000 read accesses @3162444 +system.cpu4: completed 70000 read accesses @3222154 +system.cpu7: completed 70000 read accesses @3277574 +system.cpu2: completed 70000 read accesses @3381865 +system.cpu1: completed 70000 read accesses @3415612 +system.cpu5: completed 70000 read accesses @3416504 +system.cpu6: completed 70000 read accesses @3460152 +system.cpu3: completed 70000 read accesses @3529552 +system.cpu0: completed 80000 read accesses @3611998 +system.cpu4: completed 80000 read accesses @3676108 +system.cpu7: completed 80000 read accesses @3736694 +system.cpu2: completed 80000 read accesses @3853296 +system.cpu5: completed 80000 read accesses @3905416 +system.cpu1: completed 80000 read accesses @3907045 +system.cpu6: completed 80000 read accesses @3947118 +system.cpu3: completed 80000 read accesses @4038186 +system.cpu0: completed 90000 read accesses @4055478 +system.cpu4: completed 90000 read accesses @4135882 +system.cpu7: completed 90000 read accesses @4192986 +system.cpu2: completed 90000 read accesses @4335194 +system.cpu5: completed 90000 read accesses @4388557 +system.cpu1: completed 90000 read accesses @4398614 +system.cpu6: completed 90000 read accesses @4430678 +system.cpu0: completed 100000 read accesses @4504972 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 96bce5cec..7444563ae 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 18 2009 16:36:52 -M5 revision c1d634e76817 6798 default qtip tip brad/ruby_memtest_refresh -M5 started Nov 18 2009 16:37:05 -M5 executing on cabr0354 +M5 compiled Jan 19 2010 17:11:57 +M5 revision 21fbf0412e0d 6840 default tip +M5 started Jan 19 2010 17:12:00 +M5 executing on bluedevil.cs.wisc.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 60455258 because maximum number of loads reached +Exiting @ tick 4504972 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 9b0c24527..83402b5fb 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 2438776 # Number of bytes of host memory used -host_seconds 3924.24 # Real time elapsed on the host -host_tick_rate 15406 # Simulator tick rate (ticks/s) +host_mem_usage 1414304 # Number of bytes of host memory used +host_seconds 219.48 # Real time elapsed on the host +host_tick_rate 20525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000060 # Number of seconds simulated -sim_ticks 60455258 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4504972 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99982 # number of read accesses completed -system.cpu0.num_writes 53168 # number of write accesses completed +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54115 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 53657 # number of write accesses completed +system.cpu1.num_reads 92132 # number of read accesses completed +system.cpu1.num_writes 49991 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99758 # number of read accesses completed -system.cpu2.num_writes 53630 # number of write accesses completed +system.cpu2.num_reads 93521 # number of read accesses completed +system.cpu2.num_writes 50418 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99707 # number of read accesses completed -system.cpu3.num_writes 53628 # number of write accesses completed +system.cpu3.num_reads 89205 # number of read accesses completed +system.cpu3.num_writes 48106 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99425 # number of read accesses completed -system.cpu4.num_writes 53969 # number of write accesses completed +system.cpu4.num_reads 97961 # number of read accesses completed +system.cpu4.num_writes 52598 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99810 # number of read accesses completed -system.cpu5.num_writes 53444 # number of write accesses completed +system.cpu5.num_reads 92452 # number of read accesses completed +system.cpu5.num_writes 49744 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99532 # number of read accesses completed -system.cpu6.num_writes 53907 # number of write accesses completed +system.cpu6.num_reads 91570 # number of read accesses completed +system.cpu6.num_writes 49935 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99819 # number of read accesses completed -system.cpu7.num_writes 53668 # number of write accesses completed +system.cpu7.num_reads 96862 # number of read accesses completed +system.cpu7.num_writes 51935 # number of write accesses completed ---------- End Simulation Statistics ---------- |